CN201039406Y - DSP firmware system for TD-SCDMA/3G/4G terminal - Google Patents

Abstract

The utility model provides an advanced TD-SCDMA and DSP firmware system with 3G mobile communication terminal (comprising cdma2000, UMTS, and TD-SCDMA, etc.) and 4G mobile communication terminal, in particular to a front-back (upper-lower) channel processing process which is used for achieving the main functions of the physical level protocol of the TD-SCDMA /3G /4G. The front-back (upper-lower) channel processing process mainly comprises physical level control, baseband demodulation, baseband modulation, channel coding, pilot frequency researching, physical level multiplexing/dis-multiplexing, sound coding and decoding, and audio processing. The TD-SCDMA /3G /4G terminal front-back(upper-lower) channel processing process, the dispatching mode and method which comprise theses processing processes by adopting a front-back(upper-lower) channel state device and a three-stage task operation mechanism so as to gain better TD-SCDMA /3G /4G terminal DSP and firmware system, wherein, all the processing processes relating to the hard core DSP firmware output(comprising multi-path receiving front end hard core, audio simulate front end hard core, baseband modulator hard core, searcher hard core, Viterbi decoder hard core, DSP timer hard core, Turbo/CRC decoder hard core and email sending and receiving hard core, etc.) are all dispatched and executed alternately. All forward and downward channel firmware processing processes and functions are dispatched and executed through a foreground task mode; while all the backward and upward channel firmware processing processes and functions are dispatched and executed through a background task mode.

Description

The DSP fixer system of TD-SCDMA/3G/4G terminal

Technical field

The utility model relates to the DSP fixer system of a kind of TD-SCDMA of novel, technological precedence and 3G (Third Generation) Moblie (3G contains cdma2000, UMTS, TD-SCDMA etc.), the 4th third-generation mobile communication (4G) terminal, belongs to mobile communication technology and makes the field.

Background technology

The composition of terminal D SP fixer system: terminal D SP fixer system promptly is the software systems that operate in the DSP nuclear of terminal digital baseband chip.Usually, the DSP fixer system of TD-SCDMA, 3G, 4G terminal mainly is made of following subsystem: DSP operating system (VDOS); CPU-DSP interface (CPU-DSP Interface); Layer one (physical layer) control (Layerl Control); Base band demodulator (Demodulator); Baseband modulator (Modulator); Channel coding-decoder (Channel Codec); Searcher (Searcher); Physical layer multiplex sublayer (Multiplex Sublayer); Audio coder ﹠ decoder (codec) (Vocoders); Audio Processing (AudioProcessing); Stone business (Hardware Services).

Summary of the invention

Purpose of design: the DSP fixer system that designs a kind of TD-SCDMA of novel, technological precedence and 3G (Third Generation) Moblie (3G contains cdma2000, UMTS, TD-SCDMA etc.), the 4th third-generation mobile communication (4G) terminal.

Design: in order to realize above-mentioned purpose of design.In the design of DSP fixer system, the function of terminal D SP fixer system: (1) DSP operating system (VDOS): DSP operating system (note is made VDOS) be one with use irrelevant firmware subsystem, it provides following business: signal processing task scheduling and calling; Non-interrupt task is seized-preemptive type multitasking mechanism; The priority of interrupting layer subtask and seizing; The management of internal memory and DSP nuclear stone resource.(2) CPU-DSP interface: CPU-DSP interface firmware subsystem provides following full duplex asynchronous CPU-DSP messaging protocol function: stone is shaken hands; Message communicating between DSP and CPU; The DSP application interface, it has defined between the inner different firmware subsystems of DSP and the transfer of data rule of CPU-DSP interface firmware; The CPU-DSP interface firmware transmission mechanism that gives information, but do not contain and the structure of using relevant message.3) physical layer control (L1D): physical layer control firmware management subsystem state machine and the operation of base band firmware handle.It carries out following function: dual microprocessor control system is safeguarded; The scheduling of the signal processing tasks between the different DSP firmware subsystems and transfer of data synchronously; Firmware subsystem initialization control; Different disposal state at the DSP firmware is controlled relevant peripheral hardware.(4) demodulator firmware: firmware subsystem demodulator is carried out multipath reception front end (FFE) Processing Algorithm of multipath signal receiver and is carried out controlled in wireless, comprises following function: the time unifying that is controlled at multipath reception front end FFE stone module with the time track algorithm; The multipath reception lock-in detection; The deflection of elimination phase place and the merging of multipath reception symbol; The gain of the symbol of receiving and phasing (channel estimating); Carry out descrambling with personal attendant's machine sequence code to being subjected to symbol; AFE (analog front end) is used for the adjustment of direct current (DC) biasing of i/q signal A/D (mould/number) conversion; Receive automatic gain controlling (Rx AGC); The demultiplexing and the checking of forward direction (descending) channel power control bit; Transmission power control based on open loop and closed loop estimation; Be used to control the system time tracking of the time unifying in the band receiver of base master timing stone module; Regularly the stone module is synchronous with the band receiver of base master for frame synchronization one; Frequency error estimates and VCTCXO (voltage controlled temperature compensated crystal oscillator) control (AFC, automatic frequency control); Calculate and receive (Rx) and send (Tx) signal strength signal intensity (received signal intensity indication RSSI and strength of transmitted signals indication TSSI); The estimation of signal interference ratio (signal bit energy/interference power) Eb/Nt.(5) channel coding-decoder: channel decoder firmware subsystem is divided into channel decoder firmware (processing of forward direction (descending) channel signal) and chnnel coding firmware (oppositely (up) channel signal is handled) 1) the chnnel coding firmware.The chnnel coding firmware is accepted to realize following function from the data of decoder firmware and based on frame: the frame deinterleaving; Frame is eliminated the bit punching; Frame is eliminated bit and is repeated; Dynamic (frame by frame) speed of forward direction (descending) traffic channel data is determined; Adopt Viterbi stone accelerator to finish the deconvolution coding; Finish the Turbo decoding with Turbo decoder stone module; CRC calculates.2) channel encoder firmware: the channel encoder firmware receives from the frame data of physical layer multiplex sublayer firmware and realizes following function: frame is CRC calculates and insert the tail bit; Convolution forward direction (descending) error correction coding; Adopt Turbo encoder stone module to finish the Turbo coding; Coded identification repeats; The coded identification punching; Coded identification interweaves.(6) modulator firmware: modulator firmware subsystem is used to provide data and control information to the modulator stone. and it carries out following function: symbol data is issued the modulator stone; Realize the data burst randomization with modulator personal attendant machine sequence code; Carry out the control of ON/OFF gate power packages by modulator stone interface; Reverse (up) power control sub-channel of support-provide power control bit (PCB) information to give the modulator stone; The code channel gain calculating.(7) searcher firmware (SMD, state-maintenance detects): searcher firmware (being also referred to as SMD) is carried out best forward direction (descending) pilot signal of Energy Estimation algorithm removal search, and the multipath reception of assignment FFE stone and the control of main regularly stone.The searcher firmware is controlled by CPU, only starts initialization and search multipath signal under the CPU request.Each search is all asynchronous with the other parts that DSP estimates, when not having the CPU indication, Search Results can not influence firmware data stream.Forward direction (descending) pilot tone that the CPU basis searches and the analysis that forward direction (descending) pilot tone multipath signal strength is distributed start multipath reception assignment process each time, to guarantee the multipath signal receiver performance.1) searcher firmware function of search comprises: the correct startup of a pair of searcher stone of searcher initialization module; By searching for the analysis that the stone module provides to the calculating of forward direction (descending) pilot energy; To CPU report forward direction (descending) pilot energy distribution situation.2) the multipath reception assignment function of searcher firmware comprises: send current active RX path distribution situation (current side-play amount, forward direction (descending) pilot signal strength level etc.); Request assignment RX path (heavily assignment) based on CPU.3) the main timing controlled function of searcher firmware comprises: the main timing alignment of forward direction (descending) pilot tone acquisition process; According to shifting to an earlier date or delay of the multipath signal executive system master time block that arrives the earliest.(8) physical layer multiplex sublayer (MAD): physical layer multiplex sublayer firmware subsystem provides multiplex sublayer among the CPU, the speech business based on DSP, the data transmission mechanism between the channel decoder.Comprise following function: at forward direction (descending) link: will send to CPU from the data that channel encoder is received, and the data of demultiplexing are sent to Voice decoder based on DSP.At reverse (up) link: multiplexing from the CPU multiplex sublayer with based on the data of DSP speech coder, and with transfer of data to channel encoder.(9) audio coder ﹠ decoder (codec): audio coder ﹠ decoder (codec) firmware subsystem is carried out the compress speech and the audio frequency output decompress(ion) (Voice decoder) of input audio stream (speech coder).Each audio coder ﹠ decoder (codec) is supported variable Rate compression. it mean can be according to speech activity with the voice of input by 1 of full rate, 1/2,1/4 or 1/8 carries out compressed encoding and output. simultaneously, also can reduce pattern by the audio coder ﹠ decoder (codec) firmware being provided with speed, or stipulate minimum, the highest code rate, control speed. (10) Audio Processing: Audio Processing firmware subsystem provides the Audio Signal Processing algorithm, and linear PCM sampling source one audio frequency simulation front end (VBAFE) or the synchronous serial interface (SSP) of selecting the audio signal route.1) the Audio Processing subsystem is supported following algorithm: tone produces algorithm one general tone generator provides tone signal to local loud speaker (in ring, the dtmf tone that busy tone etc. are used is transferred); The PCM sampling volume of numeral volume control-VBAFE or SSP transmitting-receiving is regulated; Lateral generation algorithm one sends back loud speaker with the regular value of the PCM sampling of microphone input; Earmuff echo canceller (5ms playbacks the path).2) function of Audio Processing subsystem can expand to and support extra optional algorithm: speech recognition; Noise suppression; Sound store; Optional algorithm can download on the DSP program storage, and audio firmware is also supported this algorithm.(11) stone business: the professional firmware subsystem of stone is realized following function: the read of DSP program storage and data storage.

The function of above-mentioned TD-SCDMA/3G/4G terminal D SP fixer system relates to and realizes complicated TD-SCDMA/3G/4G physical layer protocol, simultaneously, also there is very high demand aspects such as the management of terminal D SP firmware resource, processing speed, real-time on the other hand.

Therefore, for obtaining robustness TD-SCDMA/3G/4G terminal D SP fixer system preferably, before we adopt-oppositely (on-descending) channel status machine and three grades of task operation mechanisms are realized oppositely (on-descending) channel treatment processes and scheduling mode and method to comprising the task of finishing these processing procedures of the major function one of above-mentioned TD-SCDMA/3G/4G terminal D SP fixer system-last.

Technical scheme: the DSP fixer system that is used for the TD-SCDMA/3G/4G terminal, it comprises DSP operating system (18), the signal output part one tunnel of demodulator (10) connects the signal input part that symbol aligned merges normalizer (3), one the tunnel connects the signal input part output of demodulator firmware (9), one the tunnel connects the signal input part of searcher firmware (14), the signal input output end of searcher firmware (14) connects the signal input output end of buffer (21), the signal input output end of buffer (21) connects the CPU-DSP interface, the signal output part of demodulator firmware (9) connects the signal input part of buffer (38), the signal output of buffer (38) connects the signal input part of channel decoder (8), the signal output part of channel decoder (8) connects the signal input part of buffer (13), the signal output part of buffer (13) connects the signal input part of decoder (15), the signal output part that connects decoder (15) connects the signal input part of buffer (12), the signal output part of buffer (12) connects the signal input part of speed determiner (7), the signal output part of speed determiner (7) connects the signal input part of physical layer demodulation multiplexer (6), the signal output part one tunnel of physical layer demodulation multiplexer (6) connects the signal input part of buffer (20), one the tunnel connects the signal input part of buffer (5), the signal output part of buffer (20) connects the CPU-DSP interface, the signal output part of buffer (5) connects the signal input part of Voice decoder (4), the signal output part of Voice decoder (4) connects the signal input part of forward link speech processor (11), the signal output part of forward link speech processor (11) connects the signal input part of buffer (16), the signal output part of buffer (16) connects the signal input part of audio base-band analog front-end device (17), the signal output part of audio base-band analog front-end device (17) connects the signal input part of buffer (22), the signal output part of buffer (22) connects the signal input part of reverse link speech processor (27), the signal output part of reverse link speech processor (27) connects the signal input part of speech coder (31), the signal output part of speech coder (31) connects the signal input part of buffer (32), the signal output part that connects buffer (32) connects the signal input part of physical layer multiplex device (33), the signal output part of physical layer multiplex device (33) connects the signal input part of buffer (34), the signal output part one tunnel of buffer (34) connects the signal input part of channel encoder (35), the signal output part of channel encoder (35) connects the signal input part of buffer (36), the signal output part of buffer (36) connects the signal input part of modulator firmware (37), the signal output part of modulator firmware (37) connects the signal input part of modulator (30), another road of signal output part of buffer (34) connects the signal input part of hardware channel encoder (29), the signal output part of hardware channel encoder (29) connects the signal input part of modulator (30), the signal output part of symbol aligned merging normalizer (3) connects the signal input part of deinterleaver (2), the signal output part of deinterleaver (2) connects the signal input part of decoder (1), the signal output part of decoder (1) connects the signal input part of physical layer demodulation multiplexer (6), the signal input of hardware service apparatus (19) and phy controller (23), output is connected with the two-way communication of CPU-DSP interface, the signal input output end of CPU (26) is connected with the signal input output end of hardware mailbox (25), the signal input output end of hardware mailbox (25) is connected with the two-way communication of CPU-DSP interface, the CPU-DSP interface is connected with CPU (28) signal of communication input, the signal input part of CPU (28) signal of communication output termination physical layer multiplex device (33), the signal input output end of phy controller (23) is connected with the two-way communication of CPU-DSP interface.

Description of drawings

Fig. 1 is the block architecture diagram of the DSP fixer system of TD-SCDMA, 3G, 4G terminal.

Fig. 2 is three grades of task operation mechanism block diagrams.

Fig. 3 is the priority block diagram of three grades of task operation mechanisms.

Fig. 4 is forward direction (descending) channel status machine basic status redirect block diagram.

Fig. 5 is forward direction (descending) synchronizing channel firmware handle process block diagram.

Fig. 6 is a paging channel firmware handle process block diagram.

Fig. 7 is idle condition firmware handle Common Control Channel/broadcast channel process block diagram.

Fig. 8 is forward direction/downlink traffic channel firmware handle process block diagram.

Fig. 9 is reverse (up) channel status machine basic status redirect block diagram.

Figure 10 is an access channel firmware handle process block diagram.

Figure 11 is reverse (up) Common Control Channel firmware handle process block diagram.

Figure 12 is reverse (up) Traffic Channel firmware handle process block diagram.

Embodiment

Embodiment 1: with reference to accompanying drawing 1～12.The DSP fixer system that is used for the TD-SCDMA/3G/4G terminal, it comprises DSP operating system 18, the signal output part one tunnel of demodulator 10 connects the signal input part that symbol aligned merges normalizer 3, one the tunnel connects the signal input part output of demodulator firmware 9, one the tunnel connects the signal input part of searcher firmware 14, the signal input output end of searcher firmware 14 connects the signal input output end of buffer 21, the signal input output end of buffer 21 connects the CPU-DSP interface, the signal output part of demodulator firmware 9 connects the signal input part of buffer 38, the signal output of buffer 38 connects the signal input part of channel decoder 8, the signal output part of channel decoder 8 connects the signal input part of buffer 13, the signal output part of buffer 13 connects the signal input part of decoder 15, the signal output part that connects decoder 15 connects the signal input part of buffer 12, the signal output part of buffer 12 connects the signal input part of speed determiner 7, the signal output part of speed determiner 7 connects the signal input part of physical layer demodulation multiplexer 6, the signal output part one tunnel of physical layer demodulation multiplexer 6 connects the signal input part of buffer 20, one the tunnel connects the signal input part of buffer 5, the signal output part of buffer 20 connects the CPU-DSP interface, the signal output part of buffer 5 connects the signal input part of Voice decoder 4, the signal output part of Voice decoder 4 connects the signal input part of forward link speech processor 11, the signal output part of forward link speech processor 11 connects the signal input part of buffer 16, the signal output part of buffer 16 connects the signal input part of audio base-band analog front-end device 17, the signal output part of audio base-band analog front-end device 17 connects the signal input part of buffer 22, the signal output part of buffer 22 connects the signal input part of reverse link speech processor 27, the signal output part of reverse link speech processor 27 connects the signal input part of speech coder 31, the signal output part of speech coder 31 connects the signal input part of buffer 32, the signal output part that connects buffer 32 connects the signal input part of physical layer multiplex device 33, the signal output part of physical layer multiplex device 33 connects the signal input part of buffer 34, the signal output part one tunnel of buffer 34 connects the signal input part of channel encoder 35, the signal output part of channel encoder 35 connects the signal input part of buffer 36, the signal output part of buffer 36 connects the signal input part of modulator firmware 37, the signal output part of modulator firmware 37 connects the signal input part of modulator 30, another road of the signal output part of buffer 34 connects the signal input part of hardware channel encoder 29, the signal output part of hardware channel encoder 29 connects the signal input part of modulator 30, the signal output part of symbol aligned merging normalizer 3 connects the signal input part of deinterleaver 2, the signal output part of deinterleaver 2 connects the signal input part of decoder 1, the signal output part of decoder 1 connects the signal input part of physical layer demodulation multiplexer 6, the signal input of hardware service apparatus 19 and phy controller 23, output is connected with the two-way communication of CPU-DSP interface, the signal input output end of CPU26 is connected with the signal input output end of hardware mailbox 25, the signal input output end of hardware mailbox 25 is connected with the two-way communication of CPU-DSP interface, the CPU-DSP interface is connected with CPU28 signal of communication input, the signal input part of CPU28 signal of communication output termination physical layer multiplex device 33, the signal input output end of phy controller 23 is connected with the two-way communication of CPU-DSP interface.

Before design terminal DSP fixer system, according to of regulation and the requirement of TD-SCDMA/3G/4G terminal physical layer agreement, each DSP firmware subsystem of describing at aforementioned chapters and sections is all determined the demand of a cover to the firmware resource management to terminal D SP fixer system function, performance.(1) the base band demodulator firmware should be carried out under interrupt condition, and interrupt rate is that 19.2 KHz. firmwares should handle 1,2 in each interruption, or 4 symbols (depending on character rate). and all processing should be finished before next interruption arrives.(2) the channel encoder signal processing should be carried out frame by frame.(3) the modulator firmware should send to data on the modulator stone when 4.8 KHz interrupt.(4) the searcher firmware should be carried out with the data transmit-receive operation exception according to CPU request and associated parameter.(5) transfer of data between DSP physical layer multiplex sublayer subsystem and the CPU is asynchronous carries out, but must finish in same frame.(6) carry out frame by frame in the operation of audio coder ﹠ decoder (codec) firmware.(7) operation of Audio Processing subsystem had both been sampled to PCM and had been carried out one by one, also carried out frame by frame, and this is realized by the specific signal Processing Algorithm.(8) the professional firmware of stone is asked and asynchronous execution according to CPU.

Each DSP firmware module/subsystem is rationally proposed the restriction that the .DSP firmware framework is not subjected to task size and content as different tasks. should subsystem function be assigned in the independent task modestly; the flexibility of protection system; avoid producing too much task, because too much task will make the task scheduling of L1D very complicated.

1. three grades of task operation mechanisms: for effective above-mentioned different demands of management, VDOS operating system allows three grades of operations: interrupt class one is used for requiring highstrung task to handling real-time.Do one's utmost, reduce to full capacity the demand of this generic task to MIPS; Foreground level one is used for requiring less task to handling real-time.The demand of this generic task to MIPS need be limited within the specific limits; Backstage level one is used for requiring minimum to handling real-time, but MIPS is required more task.The common every frame of this other task of level is carried out and need be finished before next frame arrives.

Every grade of operation of VDOS all goes to dispatch and carry out the task of requirement with task list.In interrupt class, be to use the task list related to realize with interrupt control unit.In backstage and foreground level, and use relevant firmware and send request to VDOS and go to dispatch the task of corresponding task in tabulating.The VDOS scheduler task is according to interruption order and the priority that it is received, initiating task and updating task tabulation when task is finished from task list.As shown in Figure 2.VDOS realizes that in order to following strategy interrupt class is highest, and the foreground level is an intergrade, and the backstage level is lowermost level (referring to Fig. 3): as long as the interruption of hang-up is arranged in the system, VDOS just remains on the handling interrupt state; VDOS carries out the task in the tabulation of foreground, is empty up to this task list; The interruption and the foreground task that only do not have to hang up in system are tabulated when being empty, and VDOS just begins to carry out the task in the background task tabulation.The priority of three grades of task operation mechanisms, as shown in Figure 3.

1.1 interrupt class: in interrupt class, VDOS uses the stone interrupt control unit to dispatch and the priority that defines different task: the DSP interrupt control unit is designed to the relevant interrupt source of each application and has own unique interrupt vector address, in case interrupt source is sent an interruption, interrupt control unit produces an interruption and examines to DSP, and obtain correct interrupt vector address and give program bus, force DSP to jump to this specific address.All interrupt source is connected on the interrupt control unit with the chain sheet form.The priority of each interrupt source (by can concurrent interruption considering) is defined by its residing position in chained list, such as INT_VECTO limit priority is arranged, and INT_VECT14 is a lowest priority.Each interrupt source can be routed to the INTO of DSP nuclear separately, in INT1 or the INT2 interruption.VDOS processing DSP nuclear as follows interrupts and assignment DSP nuclear priority of interrupt: the INTO-limit priority; The INT1-lower priority; The INT2-lowest priority.

Table 3 has gathered all TD-SCDMA/3G/4G terminal D SP firmwares to interrupt and distributes priority: VDOS that minimum interrupt service routine is provided, and should call when using relevant interrupt service routine entering or withdraw from.Interrupt service routine guarantees to have only the higher interruption of priority to be enabled when carrying out low priority interrupt.

1.2 foreground level:, from the foreground task tabulation of organizing in the FIFO mode, carry out foreground level task in the foreground level.Each being scheduled of task has following 4 inlets (16 bit words): inlet #1: task address; Inlet #2: optional parameters (can be the input data address); Inlet #3: optional parameters (can be the dateout address); Inlet #4: optional parameters (can be operator scheme).

Foreground level operation is very useful for dispatching asynchronous task (such as searcher), and it provides the minimized ability of interrupt latency that makes.The task that all foreground levels are carried out can both be added in foreground and the background task tabulation 2.

1.3 backstage rank:, from the background task tabulation of organizing in the FIFO mode, carry out backstage level task in the backstage level.Each being scheduled of task has following 4 inlets (16 bit words): inlet #1: task address; Inlet #2: optional parameters (can be the input data address); Inlet #3: optional parameters (can be the dateout address); Inlet #4: optional parameters (can be operator scheme).

Most of backstages level task is the task that every frame is carried out, and requires a large amount of computing capabilitys, and all can only add in the background task tabulation in the task that the backstage level is carried out.

2.TD-SCDMA/3G/4G terminal D SP dual microprocessor control system: the data processing of IS2000 travelling carriage can be divided into RX path (Rx) and transmit path (Tx).On RX path, TD-SCDMA/3G/4G terminal D SP firmware handle is from the data of base station (forward direction (descending) Channel Processing).On transmit path, TD-SCDMA/3G/4G terminal D SP firmware handle is sent to the data of base station (oppositely (up) Channel Processing).

All DSP handle and adopt TD-SCDMA/3G/4G terminal D SP dual microprocessor control system to realize on forward direction (descending) and reverse (up) channel, and are divided into forward direction (descending) and reverse (up) state machine.All TD-SCDMA/3G/4G terminal D SP firmware state exchanges (for forward direction (descending) and reverse (up) channel) ask to finish according to CPU.The DSP firmware does not check whether the state exchange request is effective, and the conversion of state is done in its place one's entire reliance upon driving of CPU.

VDOS is not the direct subsystem relevant with signal processing with CPU-DSP port subsystem, but provides the business to other signal processing firmware subsystems.Therefore VDOS is in state of activation all the time with CPU-DSP port (professional the same with stone).

2.1 forward direction (descending) Channel Processing: when forward direction (descending) Channel Processing adopts state machine to finish, use following 5 main states (referring to Fig. 4): the opening initialization state; Forward direction (descending) pilot channel obtains state; Forward direction (descending) synchronizing channel state; Idle condition; Forward direction/downlink traffic channel state.

Forward direction (descending) channel status machine as shown in Figure 4.The state of forward direction (descending) channel status machine is the L1D variable, is stored in overall storing space.When travelling carriage will be linked into the TD-SCDMA/3G/4G terminal network, carry out forward direction (descending) channel status machine normal flow as shown in Figure 4.

2.1.1 opening initialization state: this is the initial condition of the forward and backward link of TD-SCDMA/3G/4G terminal D SP dual microprocessor control system.In this stage, TD-SCDMA/3G/4G terminal D SP firmware subsystem is initialized to default opening initialization state.The state that these stone module initializations is become to require with the firmware subsystem of stone module interface

2.1.2 forward direction (descending) pilot channel obtains state: at this state, following DSP firmware subsystem is activated: the demodulator firmware; Searcher firmware (SMD).

Before activating forward direction (descending) pilot search, CPU obtains request primitive to L1D by transmission, dual microprocessor control system is arranged to forward direction (descending) pilot channel obtains state.L1D is arranged to the value of the state that obtains with all global variables, and calls the demodulator firmware and obtain the initialization function and start and obtain state processing.Obtain state at forward direction (descending) pilot channel, the demodulator firmware only realizes being used for TD-SCDMA/3G/4G forward direction (descending) pilot search algorithm (Rx AGC, the algorithm of reliable operation I/QDC bias compensation, received signal Energy Estimation) does not carry out symbol and handles.

Receiving when confirming that the DSP dual microprocessor control system is transformed into forward direction (descending) pilot channel and obtains the primitive of state CPU initialization search, possible TD-SCDMA/3G/4G forward direction (descending) pilot signal of search in full feature sequence code space.Search each possible forward direction (descending) pilot tone and all be based on the Energy Estimation that forward direction (descending) pilot channel is handled, skew is not associated with TD-SCDMA/3G/4G base station characteristic sequence sign indicating number.

The DSP dual microprocessor control system remains on forward direction (descending) pilot channel always and obtains state before not finding satisfied forward direction (descending) pilot tone.In case forward direction (descending) pilot tone that CPU picked up signal intensity is good, it just be necessary, send among the DSP as pilot frequency deviation parameters such as (skews of base station characteristic sequence sign indicating number), and indication DSP dual microprocessor control system jumps to forward direction (descending) synchronizing channel state.

In other all TD-SCDMA/3G/4G terminal D SP firmware states, request is activated searcher firmware (SMD) according to CPU, and handle asynchronous (even in TD-SCDMA/3G/4G terminal D SP firmware state conversion process, the searcher firmware also can be activated) with the TD-SCDMA/3G/4G terminal data.The performance of SMD and function (forward direction (descending) pilot search, multipath reception assignment) depend on the current state of TD-SCDMA/3G/4G terminal D SP dual microprocessor control system.

2.1.3 forward direction (descending) synchronizing channel state: forward direction (descending) synchronizing channel state is used for receiving and handling forward direction (descending) synchronous channel information.At this state, activate following DSP firmware subsystem: physical layer control subsystem (LID); The demodulator firmware; Channel coding-decoder (channel decoder); Physical layer multiplex sublayer (demodulation multiplexer).Forward direction (descending) synchronizing channel firmware handle process as shown in Figure 5.

Before TD-SCDMA/3G/4G terminal D SP dual microprocessor control system jumps to forward direction (descending) synchronizing channel state, CPU sends a primitive comes a FFE stone of assignment to SMD multipath reception, make its operation in the base station characteristic sequence sign indicating number skew of obtaining, and forward direction (descending) synchronizing channel is decoded.

Next step, CPU sends a primitive makes TD-SCDMA/3G/4G terminal D SP dual microprocessor control system jump to forward direction (descending) synchronizing channel state to physical layer.In this, physical layer is arranged to forward direction (descending) synchronizing channel state with all global variables, and: (1) calls forward direction (descending) the synchronizing channel initialization function of demodulation firmware, starts the demodulation of forward direction (descending) synchronizing channel.(2) call forward direction (descending) the synchronizing channel function of initializing of channel decoder, the channel encoder parameter is arranged to forward direction (descending) synchronizing channel state.(2) return primitive to CPU, confirm that TD-SCDMA/3G/4G terminal D SP dual microprocessor control system jumps to forward direction (descending) synchronizing channel state.

Following sequence of events occurs at forward direction (descending) synchronizing channel state: (1) in case forward direction (descending) synchronizing channel is handled beginning, the demodulation firmware just begins to monitor that forward direction (descending) the synchronizing channel frame of FFE stone begins bit.In case this signal is activated, the demodulator firmware just carries out the processing of forward direction (descending) synchronizing channel to the symbol (interrupting based on 19.2kbps) of input, and they are focused in the annular SoftDataBufChA buffer area.(2) in case the demodulation firmware fills up the data of a synchronization frame, it just calls the physical layer control subsystem.(3) the physical layer control subsystem is checked the current state of forward direction (descending) channel status machine, and channel decoder is received formatted program task (pre-Viterbi task) is put in the foreground task tabulation.4. receive that the formatted program task is finished the piece deinterleaving of forward direction (descending) sync channel data frame and frame goes bit to repeat.And will go the Frame of bit repetition to be put in the format buffer area (RxFmtBuf) of channel decoder through piece deinterleaving and frame.When the processing of finishing entire frame, receive the formatted program task and just activate the convolution decoder function.5. the convolution decoder function writes the soft-decision coded data by Viterbi stone accelerator, reads the hard decision dateout, realizes folding coding.Whenever the Viterbi accelerator is write the hard decision buffer area, it just produces a Viterbi and interrupts sending to DSP.DSP reads hard decision data and next soft-decision data is write.Data in forward direction (descending) the synchronizing channel frame are continuous programming codes.Here it is, and why convolutional decoder can only initialization in the channel decoder function of initializing, and can not reset in forward direction (descending) synchronizing channel interframe.Because adopt Viterbi accelerator stone, forward direction (descending) sync channel data frame can't be ready in the end point of present frame, but the intermediate point that will arrive next frame just can be ready to.When the decoding of finishing the complete forward direction of a frame (descending) synchronizing channel frame, channel decoder just calls physical layer multiplex sublayer function and sends the data to CPU.At forward direction (descending) synchronizing channel treatment state, CPU can not send new forward direction (descending) pilot search message and give DSP, the unactivated reason of searcher firmware why that Here it is.Have only a RX path to be assigned and be used to obtain forward direction (descending) synchronizing channel.Therefore, at forward direction (descending) Channel Processing state, the demodulator firmware is not carried out (multipath) diversity and is merged.CPU receives the synchrodata frame from DSP, merges forward direction (descending) synchronous channel information (forward direction (descending) synchronizing channel frame).In case CPU decodes forward direction (descending) synchronous channel information, it just produces request primitive to L1D, main synchronously regularly stone module.When L1D receives request primitive, firmware stops to send forward direction (descending) synchronizing channel frame and gives CPU.Based on the skew of base station, and the characteristic sequence sign indicating number state and the frame counter that provide based on this primitive, L1D is provided with, loads main regularly stone module.In case main regularly stone module is set up, loads (downloading suitable forward direction (descending) pilot tone and characteristic sequence sign indicating number state), in this moment terminal and Network Synchronization.

2.1.4 idle condition: in this state terminal monitors paging channel or forward direction (descending) Common Control Channel.It is also received in the message of broadcast channel transmission.At this state, following DSP firmware subsystem is in state of activation: physical layer control (L1D); The demodulator firmware; Channel coding-decoder (channel decoder); Physical layer multiplex sublayer (demodulation multiplexer); The searcher firmware.In idle condition, according to the configuration of CPU to it, the Audio Processing firmware also can activate (such as tone generator or voice recognition tasks).

Before TD-SCDMA/3G/4G terminal D SP dual microprocessor control system jumped to idle condition, CPU sent multipath reception assignment primitive to SMD, and the characteristic sequence sign indicating number side-play amount that the FFE stone works in the base station is set, and with suitable channel code de-spread.The processing of two kinds of possible TD-SCDMA/3G/4G terminal idle pulleys is arranged: paging channel decoding and 2 concurrent decodings of channel---forward direction (descending) Common Control Channel (CCCH), broadcast channel (BCH).

2.1.4.1 paging channel is handled: paging channel is handled processing procedure as shown in Figure 6.After the multipath reception assignment was finished, CPU sent the paging channel request primitive to L1D, makes TD-SCDMA/3G/4G terminal D SP dual microprocessor control system jump to idle condition.At this constantly, L1D finishes: it is idle condition that overall forward direction (descending) state variable is set; The categorical variable that overall forward direction (descending) channel A is set is a paging channel; Request is provided with the speed of forward direction (descending) channel A according to CPU; The frame length of forward direction (descending) channel A is set; The encoding rate of forward direction (descending) channel A is set; Call the paging channel initialization function of demodulation firmware, start paging channel demodulation; Call the paging channel function of initializing of channel decoder; Return primitive to CPU, confirm that TD-SCDMA/3G/4G terminal D SP dual microprocessor control system jumps to idle condition, prepares to start the paging channel decoding.

Have following sequence of events in paging channel is handled: (1) demodulator firmware is carried out the paging channel processing (interrupting based on 19.2kbps) of incoming symbol and they is focused in the annular SoftDataBufChA buffer area.(2) in case the demodulation firmware fills up the data buffer area of a paging frame, it just calls the physical layer control subsystem.(3) the physical layer control subsystem is checked the current state of firmware forward direction (descending) the channel status machine of TD-SCDMA/3G/4G terminal, and channel category-A type, and channel decoder is received format paging channel task (pre-Viterbi task) be put in the foreground task tabulation.(4) receive that the formatted program task is finished the piece deinterleaving based on paging channel speed and frame goes bit to repeat.And will go the Frame of bit repetition to be put in the format buffer area (RxFmtBuf) of channel decoder through piece deinterleaving and frame.When the processing of finishing entire frame, receive the formatted program task and just activate the convolution decoder function.(5) the convolution decoder function writes the soft-decision coded data by Viterbi stone accelerator, reads the hard decision dateout, realizes folding coding.Whenever the Viterbi accelerator is write the hard decision buffer area, it just produces a Viterbi and interrupts sending to DSP.DSP reads hard decision data and next soft-decision data is write.Data in the paging channel frame are continuous programming codes.Here it is, and why convolutional decoder can only initialization in the channel decoder function of initializing, and can not reset in paging channel interframe.Why this point can realize, is because do not have other channels and paging channel to carry out demodulation simultaneously.Because adopt Viterbi accelerator stone, the paging channel Frame can't be ready in the end point of present frame, but the intermediate point that will arrive next frame just can be ready to.When the decoding of finishing the complete paging channel frame of a frame, channel decoder just calls physical layer multiplex sublayer function and sends the data to CPU.CPU analyzes from the message of paging channel and correspondingly provides indication for the DSP firmware.For example, it can send access exploration or monitor specific paging channel.

2.1.4.2 the public control of forward direction (descending), broadcasting is handled: idle condition firmware handle Common Control Channel/the broadcast channel process as shown in Figure 7.To CCCH, each channel of BCH all have one independently request primitive issue L1D, before sending any one channel request primitive, CPU should indicate SMD to carry out the multipath reception assignment by enabling corresponding channel and channel code being set.

When LID received forward direction (descending) the Common Control Channel request primitive of CPU, can carry out following operation: (1) was made as idle condition with overall forward direction (descending) state variable.(2) with overall forward direction (descending) channel A categorical variable be made as forward direction (descending) Common Control Channel.(3) speed of forward direction (descending) channel A is set according to CPU request.(4) frame length of forward direction (descending) channel A is set according to CPU request.(5) encoding rate of forward direction (descending) channel A is set according to CPU request.(6) call demodulation firmware forward direction (descending) Common Control Channel function of initializing.(7) call channel decoder forward direction (descending) Common Control Channel function of initializing.(8) return primitive to CPU, confirm that TD-SCDMA/3G/4G terminal D SP dual microprocessor control system has been in idle condition, and prepare the decoding of beginning forward direction (descending) control channel.

When LID receives the broadcast channel request primitive of CPU, can carry out following operation: (1) with overall forward direction (descending) channel B categorical variable be made as broadcast channel.(2) speed of forward direction (descending) channel B is set according to CPU request.(3) with the frame length of forward direction (descending) channel B.(4) encoding rate of forward direction (descending) channel B is set according to CPU request.(5) call demodulation firmware broadcast channel function of initializing.(6) call channel decoder broadcast channel function of initializing.(7) return primitive to CPU, confirm that TD-SCDMA/3G/4G terminal D SP dual microprocessor control system has been ready to start the broadcast channel decoding.

When 2 channels all are activated, following chain of events will take place: (1) to the channel of each activation, the demodulator firmware is carried out the paging channel of incoming symbol and is handled (interrupting based on 19.2kbps).And they are focused in the annular buffer area corresponding to the stone channel of its assignment (SoftDataBufChA, SoftDataBufChB).(2) in case the demodulator firmware is finished the collection to a frame soft symbol of the channel of some activation, it calls L1D.Because the frame length of different channels can be different, so (A B) needs independent process to each channel.(3) L1D checks the current state of firmware forward direction (descending) the channel status machine of TD-SCDMA/3G/4G terminal, and has finished the channel type that frame is prepared.With reception format forward direction (descending) the CCCH channel task of channel decoder, the reception format BCH channel task of channel decoder to channel B is put in the foreground task tabulation then channel A.Should dispatch Channel Processing earlier with less frame length.(4) receive formatted program task (pre-Viterbi task) based on channel type with parameter (data rate, encoding rate, frame length) is finished the piece deinterleaving and frame goes bit to repeat.And will go the Frame of bit repetition to be put in the format buffer area (RxFmtBuf) of channel decoder through piece deinterleaving and frame.When the processing of finishing entire frame, receive the formatted program task and just activate the convolution decoder function.(5) the convolution decoder function writes the soft-decision coded data by Viterbi stone accelerator, reads the hard decision dateout, realizes folding coding.Whenever the Viterbi accelerator is write the hard decision buffer area, it just produces a Viterbi and interrupts sending to DSP.DSP reads hard decision data and next soft-decision data is write.Unlike synchronous and paging channel, the convolutional encoding of these 2 channels is discontinuous, and that is exactly whenever to finish a forward direction (descending) CCCH why, the BCH decoding, and the Viterbi decoder all should be reinitialized.(6) in case finish the decoding of entire frame data, Viterbi interrupt requests (ISR) is called the L1D expanded function, and forward direction (descending) CCCH, the back Viterbi Processing tasks of BCH is put into the foreground task tabulation.This task is calculated CRC to each frame data and is compared with the CRC check tail bit that (BCH) receives, and removes CRC tail bit.Afterwards, back Viterbi Processing tasks calls physical layer multiplex sublayer function, and data are sent to CPU.

In idle condition, CPU continues to monitor whole TD-SCDMA/3G/4G forward direction (descending) pilot channels and send primitive to SMD.Based on the result who returns to CPU from SMD, CPU keeps to the tracking of forward direction (descending) pilot set (activating candidate etc.) and by the additional RX path of SMD multipath reception assignment primitive assignment.The demodulation firmware utilizes a plurality of RX path to finish the diversity combination.

2.1.4.3 slotted mode: idle condition L1D key-course is supported paging or forward direction (descending) Common Control Channel DSP firmware handle enabled/go the slotted mode that enables.Utilize the switch of request (slotted mode request primitive) the realization ON/OFF time slot of CPU.When CPU is in the OFF time slot, L1D stops idle condition being handled, and closes the Viterbi stone, and shielding FFE and modulator interrupt, and finish the residue task, sends confirm primitive to CPU and close DSP nuclear.When CPU is in the ON time slot, L1D enables the idle condition firmware operation, reinitializes demodulator and channel coding-decoder firmware, and continues aforementioned channels and handle.DSP nuclear is started by the slotted mode request primitive that cpu i/f interrupts exciting.TD-SCDMA/3G/4G terminal D SP firmware supports quick paging channel to handle.The purpose of this channel is the travelling carriage operation of introducing under the slotted mode, is implemented in paging channel or forward direction (descending) Common Control Channel time slot that the ON time slot woke and received assignment up, and is perhaps then opposite at the OFF time slot.Quick paging channel is handled and to be handled the energy that is consumed than the paging channel of assignment time slot or forward direction (descending) Common Control Channel and will lack a lot.It is to be finished under L1D control by the demodulation firmware that quick paging channel is handled.L1D receives the Quick Paging configuring request primitive that comprises the quick paging channel parameter that the base station provides in advance.Then, start quick paging channel demodulation with the Quick Paging request primitive.In the end point of Quick Paging time slot, L1D (by Quick Paging data acknowledgement primitive) is to CPU report quick paging channel decode results.If paging indicator and configuration change indicating device are configured to " OFF ", CPU sending time slots mode request primitive, indication DSP enters slotted mode once more.Otherwise DSP then should remain on wake-up states and paging or forward direction (descending) common signal channel are deciphered.

2.1.5 forward direction/downlink traffic channel state: in traffic channel state, travelling carriage receives traffic channel frame, comprise from sound, data and the signaling of base station.At this state, following DSP subsystem activates: physical layer control (L1D); The demodulator firmware; Channel coding-decoder (channel decoder); The physical layer multiplex sublayer; Audio coder ﹠ decoder (codec) (Voice decoder); Audio process (forward direction (descending) Audio Processing); The searcher firmware.

Before TD-SCDMA/3G/4G terminal D SP firmware forward direction (descending) channel status machine jumps to traffic channel state, CPU is according to up-to-date TD-SCDMA/3G/4G forward direction (descending) pilot channel distribution situation, send multipath reception assignment primitive and the operation of FFE stone is set, and the TD-SCDMA/3G/4G terminal channel of assignment is deciphered to the searcher firmware.Forward direction/downlink traffic channel firmware handle process as shown in Figure 8.

When receiving CPU traffic channel request primitive, L1D control TD-SCDMA/3G/4G terminal firmware forward direction (descending) channel status machine jumps to traffic channel state.The channel mask field of primitive is that DSP is provided at and begins to call forward direction (descending) FCH (or DTCH, Dedicated Traffic Channel), want the channel information of demodulation during forward direction (descending) DCCH, at this time point, L1D:(1) overall forward direction (descending) state variable being set is traffic channel state.(2) categorical variable that overall forward direction (descending) channel A is set according to the channel mask is primary channel/Dedicated Traffic Channel, and/or the categorical variable of forward direction (descending) channel B is a Dedicated Control Channel.(3), radio bearer/radio configuration of forward direction (descending) channel A and/or B is set, speed, frame length, default forward direction (descending) link Multiplex Option global variable, and some other relevant parameter according to the CPU request.(4) encoding rate of forward direction (descending) channel A and/or B is set.(5) call the traffic channel initialization function of demodulator firmware.(6) call channel decoder traffic channel initialization function.(7) global variable that the MAD demodulation multiplexer is set is a default setting.(8) send primitive to CPU, confirm that TD-SCDMA/3G/4G terminal D SP firmware forward direction (descending) channel status machine has jumped to service condition, and prepare to start primary channel/Dedicated Traffic Channel decoding.CPU sends the traffic channel configuration request primitive to L1D afterwards, configure dedicated channel and business option.This primitives DSP begins to handle with lower channel: forward direction (descending) FCH (DTCH), forward direction (descending) DCCH, forward direction (descending) SCH (forward complement channel/DSCH Downlink Shared Channel).L1D carries out following: (1) is primary channel/Dedicated Traffic Channel based on the categorical variable that the channel mask is provided with overall forward direction (descending) channel A, and/or the categorical variable of forward direction (descending) channel B is Dedicated Control Channel, and/or the categorical variable of forward direction (descending) channel C is a complement channel.(2) according to the bit rate variable overall forward direction (descending) channel A (B, radio bearer/radio configuration C), speed, frame length are set.(3) call MAD forward direction (descending) business option update functions.(4) if be connected, call the Voice decoder function of initializing so based on the voice service option of DSP.(5) send primitive and come into force to the new traffic channel configuration of CPU affirmation, and TD-SCDMA/3G/4G terminal D SP firmware Traffic Channel decoding function all set.

Occur following sequence of events in forward direction (descending) the Traffic Channel processing procedure successively: (1) demodulator firmware is to channel (forward direction (descending) FCH (DTCH) and forward direction (descending) the DCCH execution incoming symbol processing (interrupting based on 19.2kbps) of each activation, and with the symbol that demodulates focus on annular buffer area corresponding to the stone channel of assignment (SoftDataBufChA, SoftDataBufChB).The supplementary service channel is handled by stone, so do not need to use buffer area.(2) in case the demodulator firmware arrives the end point of frame, it calls L1D.(3) L1D checks the current state of firmware forward direction (descending) the channel status machine of TD-SCDMA/3G/4G terminal, and channel decoder is put into the foreground task tabulation to the reception format task (also being known as pre-Viterbi task) of Dedicated Control Channel DCCH.(4) pre-Viterbi task is finished the piece deinterleaving and is gone the bit punching.Activate the convolution decoder function then.(5) the convolution decoder function writes the soft-decision coded data by Viterbi stone accelerator, reads the hard decision dateout, realizes folding coding.Whenever the Viterbi accelerator is write the hard decision buffer area, it just produces a Viterbi and interrupts sending to DSP.DSP reads hard decision data and next soft-decision data is write.The convolutional encoding of Traffic Channel is discontinuous, and that is exactly whenever to finish a traffic channel data frame why, and the Viterbi decoder all should be reinitialized.(6) in case finish the decoding of entire frame data, Viterbi interrupt requests (ISR) is called the L1D expanded function, the back Viterbi of DCCH is handled and MAD demultiplexing task, and the pre-Viterbi task of forward direction (descending) FCH (or DTCH) is put into the foreground task tabulation.(7) the Viterbi task is compared to each frame data calculating CRC and with the CRC check tail bit that receives behind forward direction (descending) DCCH, and removes CRC tail bit.Afterwards, MAD demultiplexing task sends to CPU with data.(8) the pre-Viterbi task of forward direction (descending) FCH (DTCH) is finished the piece deinterleaving and is gone the bit punching.If allow the speed except that full rate, then the frame of for 1/2,1/4 and 1/8 speed goes bit to repeat.Next step is to activate the convolution decoder function.(9) in case finish the decoding of entire frame data, Viterbi interrupt requests (ISR) is called the L1D expanded function, the back Viterbi of forward direction (descending) FCH/DTCH is handled and MAD demultiplexing task is put into foreground task and tabulated.If audio-frequency function is used, Voice decoder and forward direction (descending) Audio Processing task also can be added in the tabulation so.If there is the SCH of convolution to be activated, L1D will dispatch the pre-Viterbi task of SCH on the foreground.(10) forward direction (descending) FCH (DTCH) back Viterbi task is carried out the correlation matrix that all frame rate that enable were calculated and carried out in the indication of frame quality.In case they are ready to, the speed ordo judiciorum will be activated.The speed of speed ordo judiciorum Function detection present frame, correct locator data pointer, and correct frame category is set.(11) based on the current business option configuration, MAD demodulation multiplexer task is that Voice decoder extracts original data stream and send whole Frame to produce voice data (linear PCM sampling) frame to CPU. (12) Voice decoder task.LID is by being sent to sound decorder with pointer, and data are placed in the voice output annular buffer area.For guaranteeing the reliability of firmware operation, the size of buffer area must be double (can be used to support the Audio Processing task so that a big buffer area to be provided) at least.(13) after tone decoding was finished, forward direction (descending) acoustic processing task was activated from the task list of foreground.This task is taken out the Voice decoder dateout, handles, and writes back to the output buffers district then.(14) audio frequency simulation front end interrupt service subroutine (VBAFE ISR) interrupts from forward direction (descending) audio frequency buffer area (ForwardAudioBuf) sense data based on 8kHz and writes in the VBAFE stone register.(15), comprise deinterleaving, go all symbol levels such as bit punching to handle in stone, to finish if low data rate SCH is activated.When frame data were finished dealing with, the stone deinterleaver produced an interruption and issues DSP.Deinterleaver ISR is provided with the SCH data and reads sign, and indication SCH pre-Viterbi task read data from stone and starts the convolution decoder function that adopts Viterbi stone accelerator to received frame buffer area (RxFrameBuf).After finishing whole SCH frame coding, Viterbi ISR calls the L1D excitation function, and its back Viterbi and MAD demodulation multiplexer task with complement channel is put into the foreground task tabulation.The CRC of the every frame of Viterbi task computation behind the SCH, and the CRC that calculates compared with the CRC tail bit that receives, and remove the CRC tail bit of every frame.Finish after these processing, MAD demodulation multiplexer task transfers data to CPU.(16) if high data rate SCH is activated, the stone function of expansion can be carried out Turbo/CRC decoding.Turbo/CRC decoding is to carry out after finishing symbol merging and alignment and piece deinterleaving.After frame decoding was finished, the Turbo/CRC decoder was sent out and is interrupted giving DSP.Turbo/CRC decoder ISR (interrupt service subroutine) is from the stone copies data, and the MAD demodulation multiplexer task of complement channel is joined in the foreground task tabulation.

At service condition, CPU sends new search message constantly and gives SMD, safeguards (the demodulator firmware should be able to provide the diversity of at least three RX path to merge) to keep desired diversity merging and forward direction (descending) pilot set.Every next new request arrives, and the SMD subsystem just is activated.CPU keeps the assignment of multipath reception based on current forward direction (descending) pilot distribution general status.The RX path of current activation depends on forward direction (descending) the pilot distribution general status of current input, and real-time change.

2.2 reverse (up) Channel Processing: oppositely (up) Channel Processing realizes (referring to Fig. 9) with a state machine and following three main states: the opening initialization state; System's access state; Reverse (up) traffic channel state.Oppositely the state of (up) channel status machine is a L1D variable, is stored in the global storage.The process that each terminal (MS/UE) is linked into the TD-SCDMA/3G/4G terminal network all relates to the normal flow that reverse (up) channel status machine is as shown in Figure 9 carried out.

2.2.1 opening initialization state: oppositely the opening initialization state in (up) channel status machine has description in 3.1.1.

2.2.2 system's access state: the access state in reverse (up) channel status machine, following DSP firmware subsystem is activated: physical layer control (L1D); The modulator firmware; Channel coding-decoder (channel encoder); Physical layer multiplex sublayer (multiplexer).Carry out following three kinds of different processing at TD-SCDMA/3G/4G terminal access state: the access channel transmission, (ACH); With oppositely (up) Common Control Channel transmission (CCCH).

2.2.2.1 access channel is handled: access channel firmware handle process as shown in figure 10.Before oppositely (up) Channel Processing state machine jumped to access state, CPU sent the access channel request primitive of the access channel message that comprises encapsulation to L1D.At access state, send whole channel massage immediately, rather than a frame one frame ground transmits.Afterwards, in the correct moment, CPU sends the access exploration request primitive to L1D, starts an access exploration.This primitive comprises initiates the needed full detail of access exploration---and RN (wireless network) postpones, Long Code Mask, power excursion, at this constantly, L1D:(1) reverse (up) state variable of the overall situation is set to access state.(2) categorical variable of reverse (up) channel A of the overall situation is set to access channel.(3) the oppositely speed of (up) channel A is set.(4) oppositely (up) channel A frame length is set.(5) the oppositely encoding rate of (up) channel A is set.(6) call modulator access channel function of initializing.

Following sequence of events appears in the access channel processing procedure successively: (1) modulator ISR monitors the end point of frame boundaries, when arriving the end of frame boundaries, calls the L1D incentive programme.(2) L1D checks the type of state and reverse (up) channel A of reverse (up) channel status machine of current TD-SCDMA/3G/4G terminal D SP firmware, and access channel encoder task is put into the background task tabulation.(3) channel encoder takes out Frame from access channel encapsulation buffer area, adds the tail bit, finishes convolutional encoding, and this Frame is carried out bit repeat and interweave.The data set that interweaves synthesizes symbol.(4) the channel encoder task is that the TxFrameBufA buffer area is filled by unit with the frame, by interrupting sending the data to modulator stone (every 4.8kHz interrupts producing a channel code symbol).(5) the each scheduling channel encoder of L1D can check that all remaining what access channel frames will handle.L1D scheduling channel encoder does not no longer stop the modulator stone after a frame time when having data to stay.No longer include oppositely (up) Channel Processing this time.

Based on the parameter that the base station provides, CPU starts a timer, is used to wait for the response of the access exploration of nearest transmission.If timer expiry is not received response, CPU sends a new request to L1D, to initiate a new access exploration.

Do not have mechanism to go to discern regularly and the number of times of access exploration in DSP, as long as receive the CPU request, DSP just initiates access exploration.CPU sends access exploration and stops request primitive to DSP, stops current access exploration transmission.This situation typical case appears at that the access exploration that has sent is confirmed by the base station or travelling carriage has lost paging channel.If DSP receives this primitive when important frame will send, these frames just have been dropped, and relevant variable all can be set as the value that finishes the access exploration transmission.

2.2.2.3 oppositely (up) Common Control Channel is handled: oppositely (up) Common Control Channel firmware handle process as shown in figure 11.When L1D receives oppositely (up) Common Control Channel request primitive from CPU: (1) overall situation oppositely (up) state variable is set to access state.(2) the oppositely categorical variable of (up) channel A of the overall situation is set.(3) request is provided with the oppositely speed of (up) channel A according to CPU.(4) request is provided with oppositely (up) channel A frame length according to CPU.(5) the oppositely encoding rate of (up) channel A is set.(6) call modulator (reverse/up) CCCH function of initializing.

Following sequence of events appears in the access channel processing procedure successively: (1) modulator ISR monitors the end point of frame boundaries, when arriving the end of frame boundaries, calls the L1D incentive programme.(2) L1D checks the type of state and reverse (up) channel A of reverse (up) channel status machine of current TD-SCDMA/3G/4G terminal D SP firmware, and MAD multiplexer and access channel encoder task are put into the background task tabulation.(3) the multiplexer task prepares to be input to the data of channel encoder, and channel encoder task computation CRC increases the tail bit, finishes convolutional encoding, symbol repetition, block interleaving.(4) modulator ISR interrupts with 4.8kbps, and the bit that is of convenient length is read in the district from the channel encoder output buffers, and writes the modulator stone.

2.2.3 reverse (up) traffic channel state: in reverse (up) traffic channel state, travelling carriage sends voice, data, and signaling is given the base station.In traffic channel state, following DSP firmware subsystem is activated: (1) physical layer control (L1D); (2) modulator firmware; (3) channel coding-decoder (channel encoder); (4) physical layer multiplex sublayer (multiplexer); (5) audio coder ﹠ decoder (codec) (speech coder); (6); (7) Audio Processing (oppositely (up) Audio Processing).

CPU sends traffic channel request primitive to L1D, makes reverse (up) channel status machine of TD-SCDMA/3G/4G terminal D SP firmware jump to traffic channel state.Here, the primitive that makes oppositely (up) or forward direction (descending) channel status machine jump to service condition does not have any difference---and traffic channel request primitive sends to two state machines and all causes state exchange.Oppositely (up) Traffic Channel firmware handle process as shown in figure 12.

CPU sends traffic channel request primitive to L1D,, make reverse (up) channel status machine of TD-SCDMA/3G/4G terminal D SP firmware jump to traffic channel state.Channel mask field in the primitive provides when beginning to call (oppositely/up) FCH (or DTCH, up Dedicated Traffic Channel) for DSP, (oppositely/up) DCCH (oppositely/up Dedicated Control Channel) time, with the information of which Channel Transmission.At this constantly, L1D:(1) reverse (up) state variable of the overall situation being set is traffic channel state.(2) according to the channel mask be provided with the overall situation oppositely the categorical variable of (up) channel A be that the categorical variable of primary channel/Dedicated Traffic Channel and/or channel B is a Dedicated Control Channel.(3) radio bearer/radio configuration of oppositely (up) channel A and/or B is set by the request of CPU, speed, frame length, default oppositely (up) link Multiplex Option global variable and other relevant parameter.(4) the respective coding rate of reverse (up) channel A and/or B is set.(5) in the initial condition of reverse (up) Channel Processing state machine, L1D can not dispatch the relevant firmware task of any oppositely (up) channel.It waits for reverse (up) of coming from CPU always thereby prefix sends request primitive can carry out oppositely (up) link processing.This incident only occurs in when receiving the good frame of forward direction (descending) link.At this moment, L1D: 1. call modulator firmware traffic channel initialization function.2. MAD multiplexer global variable is set is default value.If 3. audio frequency activates, call oppositely (up) Audio Processing initialize routine.

Oppositely in a single day (up) link is set up, and CPU sends the traffic channel configuration request primitive to L1D, and L1D is provided with dedicated channel and business option.This primitive can ask DSP to begin transmission (reverse/up) FCH (DTCH), (oppositely/up) DCCH, any channel in (reverse/up) SCH channels such as (reverse complemental channel/Uplink Shared Channels).Operation below L1D carries out: (1) is primary channel/Dedicated Traffic Channel according to the categorical variable that the channel mask is provided with reverse (up) channel A of the overall situation, and/or oppositely the categorical variable of (up) channel B is a Dedicated Control Channel, and/or oppositely the categorical variable of (up) channel C is a complement channel.(2) overall situation oppositely (up) channel A (B, C) radio bearer/radio configuration, speed, frame length, encoding rate are set.(3) call oppositely (up) business option update functions of MAD.(4) if connect, call the speech coding function of initializing based on the voice service option of DSP.

Following sequence of events appears in reverse (up) Traffic Channel processing procedure successively: the benchmark that (1) speech coding stone (VBAFE) interrupts with 8KHz, and to the speech data sampling and send to DSP.VBAFE ISR reads the input data from VBAFE stone register, and is written among reverse (up) speech buffer storage district ReverseAudioBuf.When whole Frame was well found, VBAFE ISR called the L1D incentive functions.(2) L1D checks the oppositely state of (up) channel status machine of current TD-SCDMA/3G/4G terminal D SP firmware, and places oppositely (up) speech processes and speech coder task in the background task tabulation.(3) oppositely (up) Audio Processing is taken out the linear PCM Frame, through handling accordingly, outputs to the speech coding task.(4) in case reverse (up) Audio Processing is finished, the speech coding task just starts, and current frame is extracted speech parameter, and coded data is put into encoded voice buffer area EncoderVoiceBuf, offers in MAD multiplexer task.In case the speech coding task is determined the speed of current encoded frame, it will notify the MAD (by routine call) and the latter to send FCH (DTCH) TxEmpty indication to CPU, inquiry and the multiplexing size of data of voice.(5) after frame begins, modulator ISR (with 4.8KHz speed) starts MAD multiplexer and the channel encoder task that the L1D scheduling is in the primary channel/Dedicated Traffic Channel of backstage level.L1D is provided with task in the background task tabulation by following order: SCH multiplexer, SCH channel encoder, DCCH multiplexer, DCCH channel encoder, FCH (DTCH) multiplexer, FCH (DTCH) channel encoder, MAD TxEmpty, modulator power control task.This order is to send reverse (up) service request primitive that comprises current frame data to the CPU time enough.(6) data are accepted from MAC in MAD multiplexer one frame one frame ground.MAD sends TxEmpty indication notice CPU, and DSP has been ready to receive new data, promptly new oppositely (up) service request primitive.The data multiplex that MAD multiplexer task provides the multiplex sublayer of moving among vocoded data and the CPU (MAC) together.At the business option based on CPU, oppositely (up) service request primitive comprises the next frame data of requirement MAD and channel encoder processing.In voice service option (can only transmit) at primary channel/Dedicated Traffic Channel based on DSP, need be multiplexing from the data of CPU with vocoded data.(7) the channel encoder task is carried out convolutional encoding, symbol repetition, block interleaving to each information frame.If use Turbo coding (only being used for two-forty supplementary service channel), whole chnnel coding is finished by stone---SCH channel encoder task only needs to write data into the stone register.(8) modulator power control task is calculated the code channel gain of all code channels that need use based on reverse (up) link gain table and present frame characteristic.At frame boundaries, modulator ISR is written to corresponding modulator stone register with the code channel gain of all code channels that need use.(9) the modulator ISR that works in 4.8KHz finishes the coded data transmission (when using the stone channel encoder, data are directly to send to the stone register, and do not relate to any firmware) between DSP firmware and the modulator stone.Simultaneously, modulator ISR also is responsible for finishing the power control of being determined by the gate mask.

Table 1:TD-SCDMA/3G/4G terminal D SP firmware IDT

Interrupt source	Interrupt control register/interrupt vector	The DSP interrupt number	Interrupt cycle
				Multipath reception front end (Finger Front End)	INT_VECTO	INTO	19.2kHz
The Audio Processing of audio frequency simulation front end (VBAFE Audio)	INT_VECT1	INTO	8.0kHz
				Transmit modulator (Tx Modulator)	INT_VECT2	INTO	4.8kHz
SSP (synchronous serial interface) receives	INT_VECT3	INTO	8.0kHz
				Searcher (Searcher)	INT_VECT4	INT1	Asynchronous
The Viterbi decoder	INT_VECT6	INT1	1408 DSP cycles after receiving the DSP write request (1408 DSP cycles after DSP write request)

DSP timer 0 (Timer O)	INT_VECT7	INT	Asynchronous (asynchronous)
				The Turbo/CRC decoder	INT_VECT8	INT1	50Hz
Deinterleaver (De-Interleaver)	INT_VECT9	INT1	50Hz
				House Keeping ADC	INT_VECT10	INT1	Asynchronous
DSP timer 1 (Timer 1)	INT_VECT11	INT1	Asynchronous
				Mailbox receives (Mailbox Receive)	INT_VECT12	INT2	Asynchronous (depending on the CPU request)
Mailbox sends (Mailbox Transmit)	INT_VECT13	INT2	Asynchronous (depending on the CPU request)

Table 2 TD-SCDMA/3G/4G terminal D SP firmware foreground task

Task name (Task Name)	The firmware subsystem	Handle type	Scheduler
				Pre-Viterbi handles (Pre-Viterbi Processing)	Channel coding-decoder	Forward direction/down channel: carry out soft symbol frame formatting, deinterleaving, the repetition of elimination bit	L1D
Back Viterbi handles (Post-Viterbi Processing)	Channel coding-decoder	Forward direction/down channel: calculate based on output of Viterbi decoder and CRC, finish speed and differentiate algorithm i	L1D
				Physical layer demodulation multiplexer (Demultiplexer)	MAD	Forward direction/down channel: to forward direction/downlink frame demultiplexing of receiving, voice data is issued inner voice codec, the Frame of route input is given CPU.	L1D
Voice decoder (Voice Decoder)	Voice codec Vocoder	Forward direction/down channel: the coded speech data decode of input is become the PCM speech stream	L1D
				Forward direction/downstream tones is handled (Forward Audio Processing)	Audio Processing	Handle the speech PCM sampling of forward/downlink	L1D
Forward direction/downlink business option upgrades (Forward Service Option Update)	LID	Parameter with new forward direction/downlink business option join dependency is set	L1D
				Search data is handled (Search Data Processing)	SMD	Search for the search window in each time interval the strongest pilot tone in long	Searcher interrupt service subroutine (Searcher ISR)
Main timing calibration (Master Time Correction)	SMD	Finish the master timer timing alignment	Searcher ISR

Table 3 TD-SCDMA/3G/4G terminal D SP firmware background task

Task name (Task Name)	The firmware subsystem	Handle type	Scheduler
				Voice encryption device	Voice codec Vocoder	Oppositely/and up channel: the PCM voice sample of input is encoded into the voice compression encoded data stream	L1D
Oppositely/up speech processing	Audio Processing	Handle the speech PCM sampling of return/uplink	L1D
				Physical layer multiplex device Multiplexer	Physical layer multiplex sublayer MAD	Oppositely/and up channel: the data of the data of the voice codec of inside and CPU input are finished multiplexing, and sent to channel encoder.	L1D
Channel encoder	Channel coding-decoder	Oppositely/and up channel: the convolutional encoding, bit of finishing data flow repeats and interweaves.
				The firmware state exchange	L1D	Carry out the conversion of TD-SCDMA/3G/4G terminal firmware state machine, comprise necessary initialization.	L1D
The control of modulator power	Modulator Modulator	Calculating is in the code channel gain of all code channels of usefulness.	L1D
				Oppositely/uplink service option renewal (Reverse Service Option Update)	L1D	Parameter with new reverse/uplink service option join dependency is set.	L1D

What need understand is: though the foregoing description is to the utility model detailed explanation of contrasting; but these explanations; just to simple declaration of the present utility model; rather than to restriction of the present utility model; any innovation and creation that do not exceed in the utility model connotation all fall in the protection range of the present utility model.

Claims (1)

1. DSP fixer system that is used for the TD-SCDMA/3G/4G terminal, it comprises DSP operating system (18), it is characterized in that: the signal output part one tunnel of demodulator (10) connects the signal input part that symbol aligned merges normalizer (3), one the tunnel connects the signal input part output of demodulator firmware (9), one the tunnel connects the signal input part of searcher firmware (14), the signal input output end of searcher firmware (14) connects the signal input output end of buffer (21), the signal input output end of buffer (21) connects the CPU-DSP interface, the signal output part of demodulator firmware (9) connects the signal input part of buffer (38), the signal output of buffer (38) connects the signal input part of channel decoder (8), the signal output part of channel decoder (8) connects the signal input part of buffer (13), the signal output part of buffer (13) connects the signal input part of decoder (15), the signal output part that connects decoder (15) connects the signal input part of buffer (12), the signal output part of buffer (12) connects the signal input part of speed determiner (7), the signal output part of speed determiner (7) connects the signal input part of physical layer demodulation multiplexer (6), the signal output part one tunnel of physical layer demodulation multiplexer (6) connects the signal input part of buffer (20), one the tunnel connects the signal input part of buffer (5), the signal output part of buffer (20) connects the CPU-DSP interface, the signal output part of buffer (5) connects the signal input part of Voice decoder (4), the signal output part of Voice decoder (4) connects the signal input part of forward link speech processor (11), the signal output part of forward link speech processor (11) connects the signal input part of buffer (16), the signal output part of buffer (16) connects the signal input part of audio base-band analog front-end device (17), the signal output part of audio base-band analog front-end device (17) connects the signal input part of buffer (22), the signal output part of buffer (22) connects the signal input part of reverse link speech processor (27), the signal output part of reverse link speech processor (27) connects the signal input part of speech coder (31), the signal output part of speech coder (31) connects the signal input part of buffer (32), the signal output part that connects buffer (32) connects the signal input part of physical layer multiplex device (33), the signal output part of physical layer multiplex device (33) connects the signal input part of buffer (34), the signal output part one tunnel of buffer (34) connects the signal input part of channel encoder (35), the signal output part of channel encoder (35) connects the signal input part of buffer (36), the signal output part of buffer (36) connects the signal input part of modulator firmware (37), the signal output part of modulator firmware (37) connects the signal input part of modulator (30), another road of signal output part of buffer (34) connects the signal input part of hardware channel encoder (29), the signal output part of hardware channel encoder (29) connects the signal input part of modulator (30), the signal output part of symbol aligned merging normalizer (3) connects the signal input part of deinterleaver (2), the signal output part of deinterleaver (2) connects the signal input part of decoder (1), the signal output part of decoder (1) connects the signal input part of physical layer demodulation multiplexer (6), the signal input of hardware service apparatus (19) and phy controller (23), output is connected with the two-way communication of CPU-DSP interface, the signal input output end of CPU (26) is connected with the signal input output end of hardware mailbox (25), the signal input output end of hardware mailbox (25) is connected with the two-way communication of CPU-DSP interface, the CPU-DSP interface is connected with CPU (28) signal of communication input, the signal input part of CPU (28) signal of communication output termination physical layer multiplex device (33), the signal input output end of phy controller (23) is connected with the two-way communication of CPU-DSP interface.

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