CN1971879A - High-voltage metal oxide semiconductor element - Google Patents
High-voltage metal oxide semiconductor element Download PDFInfo
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- CN1971879A CN1971879A CN 200510126732 CN200510126732A CN1971879A CN 1971879 A CN1971879 A CN 1971879A CN 200510126732 CN200510126732 CN 200510126732 CN 200510126732 A CN200510126732 A CN 200510126732A CN 1971879 A CN1971879 A CN 1971879A
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Abstract
This invention provides one high voltage metal oxidation semi-conductor parts structure, which comprises the following parts: one underlay; one first ion well set inside underlay; one first field oxidation layer to enclose one leakage area; one second oxidation layer to comprise one leakage area; one first voltage metal oxidation layer semiconductor groove area between first and second oxidation layers; one grating oxidation layer set in groove area; one grating electrode on the oxidation layer; one third field oxidation layer set on semiconductor underlay to enclose first field oxidation layer and second layer; the third field oxidation layer for one parts isolation area; one element isolation mixture area.
Description
Technical field
The present invention relates to a kind of high voltage device, relate in particular to a kind of high-voltage metal oxide semiconductor (metal-oxide-semiconductor, MOS) transistor unit with and preparation method thereof.
Background technology
As is known to the person skilled in the art, the application that high-voltage metal oxide semiconductor (MOS) element and low pressure metal oxide semiconductor element are integrated is simultaneously often arranged in the semiconductor element manufacturing.For example, use low pressure metal oxide semiconductor element to come the production control circuit, and use high-voltage metal oxide semiconductor element make EPROM (electrically programmableread-only-memory, EPROM) or the drive circuit of LCD etc.
Short-channel effect for fear of high voltage most, normally forming component isolation structure between grid and drain/source increases the distance of grid and drain/source, reach the purpose that reduces transverse electric field in the raceway groove, and utilize raceway groove blocking-up (channelstop) doped region that is formed on component ambient to be used as two adjacent interelement electrical isolation, so, even high voltage most still can normal operation under the operation of high operation voltage (as the 30-40 volt).
See also Fig. 1 to Fig. 9, what it illustrated is the existing schematic diagram of making a high-voltage metal oxide semiconductor element, wherein Fig. 8 and Fig. 9 are the floor map of high-voltage metal oxide semiconductor element, and the profile of Fig. 1 for being looked along tangent line I-I among Fig. 8, the profile of Fig. 3 for being looked along tangent line II-II among Fig. 9.
At first,, provide semi-conductive substrate 10, be formed with a p type wells 12 on it, and in p type wells 12, be pre-formed two N type wells 14 as Fig. 1 and shown in Figure 8.Then, on Semiconductor substrate 10 surfaces, form a pad oxide 16, then, on pad oxide 16, form mask pattern 20a and 20b, wherein mask pattern 20a defines the groove active zone territory of this high-voltage metal oxide semiconductor element, and mask pattern 20b defines the drain/source zone of this high-voltage metal oxide semiconductor element.Mask pattern 20a and 20b can be that dielectric materials such as silicon nitride constitute.
As shown in Figure 2, then form a photoresist layer 22 on Semiconductor substrate 10 surfaces, it comprises an opening 23, exposes the zone between mask pattern 20a and the mask pattern 20b.Then, utilize an ion implantation technology,,, inject Semiconductor substrate 10, form N type drift diffusion region (N drift region) 24 as phosphorus or arsenic etc. with N type dopant.Subsequently, again photoresist layer 22 is removed.
As Fig. 3 and shown in Figure 9, then on Semiconductor substrate 10 surfaces, form another photoresist layer 32, it comprises an opening 33, exposes the P type element separation doped region that will soon form in Semiconductor substrate 10.And as shown in Figure 9, opening 33 also inwardly is connected to the mask pattern 20a both sides in the groove active zone territory that defines this high-voltage metal oxide semiconductor element.Then, as the ion injecting mask, with P type dopant, for example boron etc. injects Semiconductor substrate 10 via opening 33, forms P type element separation doped region 36 with photoresist layer 32.Subsequently, again photoresist layer 32 is removed.Then, carry out a heat again and drive in (drive-in) technology, will before inject the dopant activation of Semiconductor substrate 10 with heat treatment method.
As shown in Figure 4, then carry out an oxidation (field oxide) technology, with mode of oxidizing, the zone that not masked pattern 20a and 20b cover on Semiconductor substrate 10 surfaces forms field oxide 42 and field oxide 44, wherein field oxide 42 is formed between mask pattern 20a and the 20b, and adjacent with N type drift diffusion region 24, and field oxide 44 then is formed on the mask pattern 20b outside, and it is on P type element separation doped region 36, and adjacent with P type element separation doped region 36.In the heat treatment process that forms field oxide 42 and field oxide 44, the P type element separation doped region 36 that had before injected Semiconductor substrate 10 can be affected, and the phenomenon of outside horizontal proliferation (lateral diffusion) is arranged.
Then, as shown in Figure 5, remove mask pattern 20a and 20b, and Semiconductor substrate 10 lip-deep pad oxides 16 are removed.Then, as shown in Figure 6, carry out thermal oxidation technology, the grid oxic horizon 56 of on Semiconductor substrate 10 surfaces that expose out, growing up again.Then, form a doped polycrystalline silicon grid 58 on the channel region between the N type drift diffusion region 24, it is formed on the grid oxic horizon 56.The step that forms doped polycrystalline silicon grid 58 comprises that (chemicalvapor deposition, CVD) technology forms a doped polysilicon layer on Semiconductor substrate 10, and then utilizes photoetching and etch process to define grid structure with chemical vapour deposition (CVD).
At last, as shown in Figure 7, form a photoresist layer 72 on Semiconductor substrate 10 surfaces, it comprises an opening 73, exposes the drain/source zone of part.Then, utilize an ion implantation technology,,, inject the N type well 14 of Semiconductor substrate 10, form N type heavy doping drain/source zone 74 as phosphorus or arsenic etc. with N type dopant.Subsequently, again photoresist layer 72 is removed.
The method of the existing high-voltage metal oxide semiconductor element of above-mentioned making has following shortcoming, still treats further improvement:
(1) in order to form P type element separation doped region 36, need the extra ion injection photomask of preparing one, be used on the element separation specially, so cost is higher.
(2) because the element separation of P type element separation doped region 36 is i.e. implanted semiconductor substrates 10 before the thermal oxidation technology of the heat treatment of field oxide 42 and 44 and grid oxic horizon 56, therefore, after implanting, still to bear the elevated temperature heat technology of back, cause P type element separation doped region 36 that the horizontal proliferation problem is arranged, make the doping content of element separation be not enough to adopt polysilicon field element (poly fielddevice), even do not allow to use ground floor metal field element (M1 field device), this makes circuit design limited many.In addition, the horizontal proliferation problem of P type element separation doped region 36 also makes the area of high voltage device be not easy further to dwindle.
Summary of the invention
Therefore, main purpose of the present invention is promptly in structure and its manufacture method of the high-voltage metal oxide semiconductor element that a kind of improvement is provided, to solve the problem of above-mentioned existing skill.
According to a preferred embodiment of the invention, the invention provides a kind of method of making high-voltage metal oxide semiconductor element, comprise the steps:
(1) provides semi-conductive substrate, be formed with first an ion well with one first conductivity on it;
(2) on this Semiconductor substrate, form a pad oxide;
(3) on this pad oxide, form a silicon nitride layer;
(4) etch away this silicon nitride layer of part, make this remaining silicon nitride layer constitute an active region mask, it covers a channel region, a drain region, one source pole zone and an element area of isolation of this high-voltage metal oxide semiconductor element;
(5) carry out an oxidation technology, on this Semiconductor substrate that is not covered, grow one first field oxide, one second field oxide and the 3rd field oxide by this active region mask;
(6) remove this active region mask and this pad oxide;
(7) grow a grid oxic horizon in this channel region;
(8) on this grid oxic horizon, form a grid;
(9) carry out one first ion implantation technology, in this drain region and this source region, form a drain/source doped region with one second conductivity simultaneously; And
(10) carry out one second ion implantation technology, in this element separation zone, form an element separation doped region with this first conductivity.
According to another preferred embodiment of the invention, the invention provides a kind of structure of high-voltage metal oxide semiconductor element, comprise semi-conductive substrate; One first ion well is located in this Semiconductor substrate, and this first ion well has one first conductivity; One first field oxide (field oxide layer), it is aboveground to be located at this first ion, and this first field oxide surrounds drain electrode (drain) zone of this high-voltage metal oxide semiconductor element; One drain doping region is located in this Semiconductor substrate in this drain region, and this drain doping region has one second conductivity; One second field oxide, it is aboveground to be located at this first ion, and this second field oxide surrounds one source pole (source) zone of this high-voltage metal oxide semiconductor element, is a channel region of this high-voltage metal oxide semiconductor element between this first field oxide and this second field oxide wherein; The one source pole doped region is located in this Semiconductor substrate in this source region, and this source doping region has this second conductivity; One grid oxic horizon is located on this channel region; One grid is located on this grid oxic horizon; One the 3rd field oxide is located on this Semiconductor substrate, surrounds this first field oxide and this second field oxide, and is an element area of isolation between the 3rd field oxide and this first field oxide, this second field oxide; And one element isolate doped region, be located in this Semiconductor substrate in this element separation zone.
In order to make those skilled in the art can further understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and explanation usefulness, is not to be used for the present invention is limited.
Description of drawings
What Fig. 1 to Fig. 7 illustrated is existing generalized section of making a high-voltage metal oxide semiconductor element;
Fig. 8 and Fig. 9 are the floor map of high-voltage metal oxide semiconductor element, and wherein Fig. 1 is the profile of being looked along tangent line I-I among Fig. 8, the profile of Fig. 3 for being looked along tangent line II-II among Fig. 9;
What Figure 10 to Figure 16 illustrated is the generalized section that the present invention makes a high-pressure N-type metal oxide semiconductor element;
Figure 17 is the floor map of high-voltage metal oxide semiconductor element of the present invention after defining active region with the silicon nitride mask pattern, and wherein Figure 10 is the profile that Figure 17 is looked along tangent line III-III;
Figure 18 is the side isometric view of high-voltage metal oxide semiconductor element of the present invention.
The main element symbol description
10 Semiconductor substrate, 12 p type wellses
14 N type wells, 16 pad oxides
The 20c mask pattern
22 photoresist layers, 23 opening
24 N types drift diffusion region, 32 photoresist layers
33 openings, 36 P type element separation doped regions
42 field oxides, 44 field oxides
46 field oxides
56 grid oxic horizons, 58 doped polycrystalline silicon grids
72 photoresist layers, 73 opening
74 N type heavy doping drain/source zones
82 photoresist layers, 83 opening
136 P type element separation doped regions
100 Semiconductor substrate, 112 P type ion wells
214 N types drift diffusion region 224a N type is layer impure well gradually
224b N type is layer impure well gradually
236 heavy doping element separation doped regions, 256 grid oxic horizons
258 grid 274a drain doping region
274b source doping region 310 first field oxides
320 second field oxides 330 the 3rd field oxide
374a drain region, 336 element separation zone
The 374b source region
Embodiment
See also Figure 10 to Figure 16, what it illustrated is the generalized section that the present invention makes a high-pressure N-type metal oxide semiconductor element, Figure 17 is the floor map of high-voltage metal oxide semiconductor element of the present invention after defining active region with the silicon nitride mask pattern, and Figure 10 is the profile of being looked along tangent line III-III among Figure 17.The present invention can be applicable to the making of high voltage p-type metal oxide semiconductor (HVPMOS) element, wherein only need get final product electrically doing suitable conversion.
At first, as shown in figure 10, provide semi-conductive substrate 10, be formed with a p type wells 12 on it, and in p type wells 12, be pre-formed two N type wells 14, respectively as the N type of high voltage device drain/source layer diffusion region (N grade well) gradually.Then, on Semiconductor substrate 10 surfaces, form a pad oxide 16.
Then, on pad oxide 16, form mask pattern 20a, 20b and 20c, wherein mask pattern 20a is connected with mask pattern 20c, wherein mask pattern 20a defines the groove active zone territory of this high-voltage metal oxide semiconductor element, mask pattern 20b defines the drain/source zone of this high-voltage metal oxide semiconductor element, and mask pattern 20c defines P type raceway groove blacked-out areas or the element separation doped region that will soon form in Semiconductor substrate 10.
According to a preferred embodiment of the invention, mask pattern 20a, 20b and 20c can be that dielectric materials such as silicon nitride constitute.
When the invention is characterized in silicon nitride definition active region, promptly utilize mask pattern 20c that P type raceway groove blacked-out areas or element separation doped region are covered in simultaneously, therefore, when carrying out oxidation technology, above P type raceway groove blacked-out areas or element separation doped region, do not have the formation of field oxide when follow-up.
As shown in figure 11, then form a photoresist layer 22 on Semiconductor substrate 10 surfaces, it comprises an opening 23, exposes the zone between mask pattern 20a and the mask pattern 20b.Then, utilize an ion implantation technology,,, inject Semiconductor substrate 10, form N type drift diffusion region (N drift region) 24 as phosphorus or arsenic etc. with N type dopant.Subsequently, again photoresist layer 22 is removed.Then, carry out a hot injection process again, will before inject the dopant activation of Semiconductor substrate 10 with heat treatment method.
As shown in figure 12, then carry out an oxidation technology, with mode of oxidizing, not masked pattern 20a on Semiconductor substrate 10 surfaces, the zone that 20b and 20c cover forms field oxide 42, field oxide 44 and field oxide 46, wherein field oxide 42 is formed between mask pattern 20a and the 20b, and it is adjacent with N type drift diffusion region 24, field oxide 44 is formed between mask pattern 20b and the 20c, field oxide 46 then is formed on the mask pattern 20c opposite side or the outside, and the follow-up P type element separation doped region that will form then is between field oxide 44 and field oxide 46.
Than Prior Art, the present invention did not carry out the ion implantation technology of element separation doped region before forming field oxide 42,44 and 46.
Then, as shown in figure 13, remove mask pattern 20a, 20b and 20c, and Semiconductor substrate 10 lip-deep pad oxides 16 are removed.Remove the practice of mask pattern 20a, 20b and 20c and normally utilize the wet etching mode to carry out, for example with hot phosphoric acid solution.The removal of pad oxide 16 then can utilize dilute hydrofluoric acid (DHF) solution to carry out.
As shown in figure 14, carry out thermal oxidation technology, the grid oxic horizon 56 of on Semiconductor substrate 10 surfaces that expose out, growing up again, its thickness is about between 300 to 900 dusts.Then, form a doped polycrystalline silicon grid 58 on the channel region between the N type drift diffusion region 24, it is formed on the grid oxic horizon 56.
The step that forms doped polycrystalline silicon grid 58 comprises that (chemical vapordeposition, CVD) technology forms a doped polysilicon layer on Semiconductor substrate 10, and then utilizes photoetching and etch process to define grid structure with chemical vapour deposition (CVD).
Then, as shown in figure 15, form a photoresist layer 72 on Semiconductor substrate 10 surfaces, it comprises an opening 73, exposes the drain/source zone of high pressure NMOS element.Then, utilize an ion implantation technology,,, inject the N type well 14 of Semiconductor substrate 10, form N type heavy doping drain/source zone 74 as phosphorus or arsenic etc. with N type dopant.Subsequently, again photoresist layer 72 is removed.
Then, as shown in figure 16, form a photoresist layer 82 on Semiconductor substrate 10 surfaces, it comprises an opening 83, expose the zone that previous mask pattern 20c is covered, and photoresist layer 82 defines the drain/source zone of high voltage PMOS element (not shown) simultaneously.Then, utilize an ion implantation technology,,, inject Semiconductor substrate 10, form P type element separation doped region 136 via opening 83 as boron etc. with P type dopant.
Another principal character of the present invention is to be used for to carry out the photoresist layer 82 of the ion implantation technology of P type element separation doped region 136, the ion that also is suitable for the drain/source zone that is used as high voltage PMOS element (not shown) simultaneously injects, therefore, the doping content of P type element separation doped region 136 of the present invention is identical with the doping content in the drain/source zone of high voltage PMOS element (not shown), is about 1E15-2E15 atoms/cm
3About, the comparable Prior Art of its doping content (is about 1E14 atoms/cm
3) want high.
See also Figure 18, what it illustrated is the side isometric view of high-voltage metal oxide semiconductor element of the present invention.As shown in figure 18, high-voltage metal oxide semiconductor element structure provided by the invention comprises semi-conductive substrate 100, is formed with a P type ion well 112 on it; One first field oxide (fieldoxide layer) 310 is located on this P type ion well 112, and first field oxide 310 surrounds drain electrode (drain) regional 374a of this high-voltage metal oxide semiconductor element; One N type heavy doping drain doping region 274a is located in the Semiconductor substrate 100 in the 374a of drain region; One N type is layer impure well 224a gradually, surrounds drain doping region 274a; One second field oxide 320, be located on the first ion well 112, and second field oxide 320 surrounds the regional 374b of one source pole (source) of this high-voltage metal oxide semiconductor element, is a channel region of this high-voltage metal oxide semiconductor element between first field oxide 310 and second field oxide 320 wherein; One N type heavy doping source electrode doped region 274b is located in the 374b of source region; One N type is layer impure well 224b gradually, surrounds source doping region 274b; One grid oxic horizon 256 is located on this channel region; One grid 258 is located on the grid oxic horizon 256; One the 3rd field oxide 330 is located on the Semiconductor substrate 100, surrounds first field oxide 310 and second field oxide 320, and is an element area of isolation 336 between the 3rd field oxide 330 and first field oxide 310, second field oxide 320; And a P type heavy doping element separation doped region 236, be located in the element separation zone 336.In addition, gradually also be provided with N type drift diffusion region 214 between the layer impure well at this channel region and N type.
In sum, the maximum characteristics of the present invention are to define the active region of high voltage device when (comprising channel region and drain/source zone), earlier element separation doped region to be formed in the subsequent step is covered simultaneously, and when forming field oxide, high voltage device active region and element separation doped region that these linings cover can't generate field oxide.In addition, it is that oxidation technology on the scene is just carried out afterwards that the ion that forms the element separation doped region injects, and therefore can avoid the doped region horizontal proliferation in the implanted semiconductor substrate.
Moreover, the present invention utilizes the photomask and the photoresist layer in the drain/source zone of definition high voltage PMOS element, define the element separation doped region of high pressure NMOS element simultaneously, not only can save photomask and cost, and make the concentration of element separation doped region improve, and can allow and use polysilicon field element (poly field device) and ground floor metal field element (M1 fielddevice) on the circuit design, have more elasticity.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (16)
1. method of making high-voltage metal oxide semiconductor element comprises:
Semi-conductive substrate is provided, is formed with one first ion well on it, and this first ion well has one first conductivity;
On this Semiconductor substrate, form a pad oxide;
On this pad oxide, form a silicon nitride layer;
Etch away this silicon nitride layer of part, make this remaining silicon nitride layer constitute an active region mask, it covers a channel region, a drain region, one source pole zone and an element area of isolation of this high-voltage metal oxide semiconductor element;
Carry out an oxidation technology, on this Semiconductor substrate that is not covered, grow one first field oxide, one second field oxide and the 3rd field oxide by this active region mask, wherein this first field oxide surrounds this drain region, and this second field oxide surrounds this source region;
Remove this active region mask;
Remove this pad oxide;
Grow a grid oxic horizon in this channel region;
On this grid oxic horizon, form a grid;
Carry out one first ion implantation technology, in this drain region and this source region, form a drain/source doped region with one second conductivity simultaneously; And
Carry out one second ion implantation technology, in this element separation zone, form an element separation doped region with this first conductivity.
2. the method for making high-voltage metal oxide semiconductor element as claimed in claim 1, wherein this channel region is connected with this element separation zone.
3. the method for making high-voltage metal oxide semiconductor element as claimed in claim 1 is this channel region between this first field oxide and this second field oxide wherein.
4. the method for making high-voltage metal oxide semiconductor element as claimed in claim 1 is this element separation zone between the 3rd field oxide and this first field oxide, this second field oxide wherein.
5. the method for making high-voltage metal oxide semiconductor element as claimed in claim 1, wherein this first conductivity is the P type, this second conductivity is the N type.
6. the method for making high-voltage metal oxide semiconductor element as claimed in claim 1, wherein this first conductivity is the N type, this second conductivity is the P type.
7. the method for making high-voltage metal oxide semiconductor element as claimed in claim 1, wherein this grid is a polysilicon gate.
8. the method for making high-voltage metal oxide semiconductor element as claimed in claim 1, wherein the thickness of this grid oxic horizon is about 300 dust to the 900 Izod right sides.
9. high-voltage metal oxide semiconductor element structure comprises:
Semi-conductive substrate;
One first ion well is located in this Semiconductor substrate, and this first ion well has one first conductivity;
One first field oxide, it is aboveground to be located at this first ion, and this first field oxide surrounds a drain region of this high-voltage metal oxide semiconductor element;
One drain doping region is located in this Semiconductor substrate in this drain region, and this drain doping region has one second conductivity;
One second field oxide, it is aboveground to be located at this first ion, and this second field oxide surrounds the one source pole zone of this high-voltage metal oxide semiconductor element, is a channel region of this high-voltage metal oxide semiconductor element between this first field oxide and this second field oxide wherein;
The one source pole doped region is located in this Semiconductor substrate in this source region, and this source doping region has this second conductivity;
One grid oxic horizon is located on this channel region;
One grid is located on this grid oxic horizon;
One the 3rd field oxide is located on this Semiconductor substrate, surrounds this first field oxide and this second field oxide, and is an element area of isolation between the 3rd field oxide and this first field oxide, this second field oxide; And
One element is isolated doped region, is located in this Semiconductor substrate in this element separation zone.
10. high-voltage metal oxide semiconductor element structure as claimed in claim 9, wherein this high-voltage metal oxide semiconductor element structure also comprises gradually layer impure well of a drain electrode, is located in this Semiconductor substrate, and surrounds this drain doping region.
11. high-voltage metal oxide semiconductor element structure as claimed in claim 9, wherein this high-voltage metal oxide semiconductor element structure also comprises gradually layer impure well of one source pole, is located in this Semiconductor substrate, and surrounds this source doping region.
12. high-voltage metal oxide semiconductor element structure as claimed in claim 9, wherein the doping content of this source doping region and this drain doping region all is about 1E15-2E15atoms/cm
3About.
13. high-voltage metal oxide semiconductor element structure as claimed in claim 9, wherein this first conductivity is the P type, and this second conductivity is the N type.
14. high-voltage metal oxide semiconductor element structure as claimed in claim 9, wherein this first conductivity is the N type, and this second conductivity is the P type.
15. high-voltage metal oxide semiconductor element structure as claimed in claim 9, wherein this grid is a polysilicon gate.
16. high-voltage metal oxide semiconductor element structure as claimed in claim 9, wherein the thickness of this grid oxic horizon is about 300 dust to the 900 Izod right sides.
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| CN104810271A (en) * | 2014-01-26 | 2015-07-29 | 北大方正集团有限公司 | Formation method of field oxide layer |
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| JPH1154630A (en) * | 1997-08-07 | 1999-02-26 | Sony Corp | Semiconductor and fabrication thereof |
| JP2002026139A (en) * | 2000-06-30 | 2002-01-25 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
| TWI238517B (en) * | 2004-07-28 | 2005-08-21 | United Microelectronics Corp | Method for fabricating integrated circuits having both high voltage and low voltage devices |
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| CN104810271A (en) * | 2014-01-26 | 2015-07-29 | 北大方正集团有限公司 | Formation method of field oxide layer |
| CN104810271B (en) * | 2014-01-26 | 2017-09-15 | 北大方正集团有限公司 | The forming method of field oxide |
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