CN1968061A - Re-timing apparatus and method - Google Patents
Re-timing apparatus and method Download PDFInfo
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- CN1968061A CN1968061A CN 200610140440 CN200610140440A CN1968061A CN 1968061 A CN1968061 A CN 1968061A CN 200610140440 CN200610140440 CN 200610140440 CN 200610140440 A CN200610140440 A CN 200610140440A CN 1968061 A CN1968061 A CN 1968061A
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Abstract
The invention relates to a retimed device and method, wherein said device comprises buffer module and selecting controlling module; the selecting controlling module comprises block one-to-two module and clock selecting module. And the method comprises that: A, system selects retime buffer module in cascade buffer modules, selects other buffer modules as non-retime buffer module; b, said retime buffer module writes the data decoded from the input E1 signal of retime buffer module into said retime buffer module, then reads out the data from said module, to realize retime function. The invention can expand the buffer capacity of retime buffer via connecting the channels of several present E1 chip, without rereading or covering data caused by lacked buffer.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of Apparatus and method for of timing again.
Background technology
Timing technology is a kind of emerging clock technology again, the E1 signal (transmission rate by the ITU-T of International Telecommunication Association regulation is the signal of 2048kbit/s) that is used for SDH (SDH (Synchronous Digital Hierarchy)) transmission equipment output branch road carries out clock optimization, its basic principle as shown in Figure 1:
At first receive the E1 signal of transmission branch road output, the data decode in the signal come out, extract simultaneously in the signal clock as more regularly buffer write clock, the data write buffer that decodes.Utilize the data of the clock sense buffer of system then, be encoded into the E1 signal and export to terminal equipment again.Whole process has kept original E1 data content, but the clock that E1 comprised is optimized.The data terminal equipment of subordinate can extract good clock from the E1 of timing device output again, as timing base.
Because in the buffering area of existing E1 chip (receiving and send the device chip of E1 signal), 1 road E1 buffering area altogether has only 512 bytes.Like this, if realize again regularly by 1 road E1, maximum buffer can only reach 512 bytes, when writing clock frequency and reading clock frequency not simultaneously, if write faster than reading, then writing clock can catch up with and read clock, at this moment old data can take place does not also take out, the phenomenon that new data deposit in again if write slowlyer than reading, is then read clock and can be caught up with and write clock, at this moment new data can take place does not also write, read the mistake that clock reads through old data again, like this, be capped or read again with regard to causing the data in the buffering area.
The manufacturer that has now adopts the new special-purpose E1 chip of oneself exploitation, make its data buffer zone increase to 1024 bytes, effectively reduced reading again or the covering phenomenon of buffer data, but this method requires the special E1 chip of redesign, the realization cost is higher, and the competitiveness of product in market is lower.
Summary of the invention
In view of above-mentioned existing in prior technology problem, the purpose of this invention is to provide a kind of Apparatus and method for of timing again, realize again the regularly expansion of buffer pool size by the mode that the existing E1 chip of multichannel is carried out cascade, solved in the process of timing again, because the data buffer zone deficiency causes data by the problem of reading again or covering.
The objective of the invention is to be achieved through the following technical solutions:
The invention provides a kind of buffer device of timing again, comprising: buffer module and selection control module,
Described buffer module cascade, road E1 passage in the corresponding E1 chip of each buffer module;
Select control module: be connected with buffer module respectively, and select timing buffer module again in buffer module, the buffer module of selecting other cascade is as the non-buffer module of timing again;
The clock that the described buffer module of timing again will be extracted from the described buffer module of timing again input E1 writes the described buffer module of timing again as writing clock with data, and clock is read in the conduct of using system clock then, and data are read the described buffer module of timing again.
State and select control module specifically to comprise:
Clock alternative module: the selective system clock as more regularly buffer module read clock, and select from the described non-clock that regularly extracts the buffer module input E1 signal again as described non-more regularly buffer module read clock;
Clock selection module: be connected with buffer module by clock alternative module, control clock alternative module is read clock to each buffer module selection, when the described buffer module of timing is again write full or is read sky, triggering the described timing again of change buffer module is the non-buffer module of timing again, selects regularly buffer module again in a plurality of buffer modules again.
Described non-the writing clock and read clock and all use of buffer module regularly again from the described non-clock that regularly extracts the buffer module input E1 again.
The present invention also comprises a kind of method of timing again, and described method comprises:
Regularly buffer module is selected by A, system again in the buffer module of cascade, the buffer module of selecting other cascade is as the non-buffer module of timing again;
The clock that B, the described buffer module of timing again will be extracted from the described buffer module of timing again input E1 writes the described buffer module of timing again as writing clock with data, and clock is read in the conduct of using system clock then, and data are read the described buffer module of timing again.
Described steps A specifically comprises:
The state of current buffer module is judged by A1, system, if described buffer module is not write full or do not read sky, then selects described current buffer module as buffer module regularly again, and the buffer module of other cascade is as non-time block again, otherwise, execution in step A2;
The state of the buffer module of A2, system's judgement and described current buffer module cascade, if the buffer module of described cascade is not write full or is not read sky, the buffer module of then selecting described cascade is as the current buffer module of timing again, otherwise repeat this step, all write full or all read sky up to all buffer modules, system reports warning.
Before carrying out described steps A 1, also comprise:
During initialization, first buffer module conduct timing buffer module is again selected by system, and other is the non-buffer module of timing again.The clock that clock selection module extracts from input E1 is as the clock of writing of first buffer module, and the selective system clock is as the clock of reading of first buffer module; Simultaneously for the buffer module of other cascade, select the clock that from the buffer module input E1 signal of each cascade, extracts writing clock and reading clock as the buffer module of each cascade.
Described steps A 1 specifically comprises:
The state of current buffer module is judged by system, if described buffer module is not write full or is not read sky, then select described current buffer module conduct timing buffer module again, the buffer module of other cascade is as non-time block again, clock selection module select the clock that extracts from current buffer module input E1 as more regularly buffer module write clock, the selective system clock as more regularly buffer module read clock, and select to import clock the writing clock and reading clock of extracting the E1 signal as the non-buffer module of timing again from the buffer module of cascade, otherwise, execution in step A2.
Described steps A 2 specifically comprises:
The state of the buffer module of system's judgement and described current buffer module cascade, if the buffer module of described cascade is not write full or is not read sky, the buffer module of then selecting described cascade is as buffer module regularly again, changes current buffer module as non-buffer module regularly again; Clock selection module select the clock that extracts from the buffer module input E1 of cascade as more regularly buffer module write clock, the selective system clock as more regularly buffering area read clock; Select simultaneously from the non-clock that regularly extracts the buffer module E1 signal again as non-the writing clock and read clock of buffer module regularly again, otherwise repeat this step, all write full or all read sky up to all buffer modules, system reports warning.
Described step B also comprises: clock the writing clock and reading clock as the described non-buffer module of timing again that will extract from the described non-buffer module of timing again input E1.
As seen from the above technical solution provided by the invention, among the present invention, under the prerequisite that does not change existing E1 chip functions, carry out cascade by passage with multichannel E1 chip, to more regularly the capacity of buffering area expand, solved in the process of timing again, because the data buffer zone deficiency causes data by the problem of reading again or covering.
Description of drawings
Fig. 1 is the principle schematic of timing technology more of the prior art;
Fig. 2 is the hardware connection diagram of the embodiment of the invention;
Fig. 3 is the flow chart of the control method of the embodiment of the invention.
Embodiment
Core concept of the present invention provides a kind of increase method and the device of timing buffer pool size again, the mode that passage by multichannel E1 chip carries out cascade realizes the regularly expansion of buffer pool size again, reach the purpose of avoiding data to read again or cover, effectively overcome the existing in prior technology problem.
Be described in further detail to 3 pairs of method and apparatus of the present invention of accompanying drawing below in conjunction with accompanying drawing 2.
Here, will form two buffer module levels and be linked as example with two-way E1 passage cascade, Apparatus and method for of the present invention is elaborated, wherein, the buffering area of the buffer module of two-way E1 passage is respectively buffer A and buffer B.
At first, equipment of the present invention is further elaborated.
As shown in Figure 2, by buffer A and buffer B is respectively the buffering area of two-way E1, the buffer that its grade is linked to be is a circular buffer, and buffer A and buffer B write pointer translational speed be with to write clock frequency corresponding, and the read pointer translational speed is with to read clock frequency corresponding.When writing clock when reading clock, buffer takies expansion; When writing clock when reading clock, taking of buffer will reduce.It all is the clock that extracts passage input E1 that 2 tunnel E1 writes clock, reads clock or the system clock of clock by clock selecting control module control selector channel input E1.
In order to represent the buffering area user mode of buffer A and buffer B, be provided with A sign and B sign here.The state of A sign is empty, and expression buffer A is not write full, is not read sky yet; A sign state is A1, and expression buffer A is write full; A sign state is A0, and expression buffer A is read sky.The state of same B sign is empty, and expression buffer B is not write full, is not read sky yet; B sign state is B1, and expression buffer B is write full; B sign state is B0, and expression buffer B is read sky.
As shown in Figure 3, when system start-up, the buffer of initialization 2 road E1.Extract the write clock of the clock of the first via (buffer A) input E1 as buffer A, clock selecting control module selective system clock is the clock of reading of buffer A, and buffer A is as the data buffer zone of timing again like this.Extract the write clock of the clock of the second tunnel (buffer B) input E1 as buffer B, it is the clock of reading of buffer B that the clock selecting control module is selected the clock of described the second tunnel (buffer B) input E1, like this, buffer B does not serve as timing data buffering area again.System intialization buffer A and two buffers of bufferB is masked as sky then.System uses buffer A to carry out timing function more earlier like this, and the buffer B of the second road E1 does not carry out regularly again, just transparent data and clock.Set the clock sign that A sign and B sign are respectively buffer A and buffer B, at this moment, A sign and B sign all are empty.
When the frequency of the clock frequency of input E1 signal and system clock not simultaneously, buffer A to write, read clock frequency also just different, specifically, can be divided into two kinds of situations:
First kind of situation, if write clock greater than reading clock, taking of buffer A will constantly enlarge.Like this, when the clock to the E1 signal was optimized, the state of buffer A at first will be judged by system: when taking of buffer A equals 512, illustrate that buffer A is filled with by data, system will put A and be masked as A1.System's state of interpretation B sign again if B is masked as B1, illustrates that buffer B also is filled with by data then, and at this moment, buffer A and buffer B are filled with, and system does not have buffer resource and can use report and alarm.If the B sign is not B1, be that B is masked as B0 or for empty, illustrates that taking of buffer B also do not reach 512, that is to say upwards to take up room in addition, i.e. write data inside, the clock selecting control module is selected the clock that clock extracts for first via E1 input of reading of buffer A.Like this, the clock that the reading and writing clock of first via E1 all extracts for buffer A input E1, buffer A is as the non-buffer module of timing again, and buffer A takies and remains unchanged, and has protected the data of buffer A can not occur covering.Simultaneously, it is system clock that the clock selecting control module is selected the clock of reading of buffer B, and the second road E1 begins to enable timing function again, and buffer B serves as regularly buffer module again.
Second kind of situation, if write clock less than reading clock, taking of buffer A will constantly be dwindled.Like this, when the clock to the E1 signal is optimized, at first will judge the state of buffer A: system is confirming that taking of buffer A is not equal at 512 o'clock, system will judge also whether taking of buffer A equals 1, if when taking of buffer A equals 1, the data that buffer A is described are run through, and system will put A and be masked as A0.System's state of interpretation B sign again if B is masked as B0, illustrates that the data of buffer B are run through then, and at this moment, buffer A and buffer B are read sky, and system does not have buffer resource and can use report and alarm; If the B sign is not B0, be that B is masked as B1 or for empty, illustrates that taking of buffer B also do not narrow down to 1, that is to say to take up room downwards in addition, promptly can be from the inside read data, the clock selecting control module is selected the clock that clock extracts for first via E1 input of reading of buffer A.Like this, the clock that the reading and writing clock of bufferA all extracts for buffer A input E1, buffer A is as the non-buffer module of timing again, and taking of buffer A remains unchanged, and protected the data of buffer A can not occur reading again.Simultaneously, it is system clock that the clock selecting control module is selected the clock of reading of buffer B, and the second road E1 begins to enable timing function again, and buffer B serves as regularly buffer module again.
After this, system changes the state of judging buffer B into; The state of judging buffer A with the front is the same, is divided into two kinds of situations.
When taking of buffer B equals 512, illustrate that buffer B is filled with by data, system will put B and be masked as B1.System's state of interpretation A sign again if A is masked as A1, illustrates that buffer A also is filled with by data then, and at this moment, buffer A and buffer B are filled with, and system does not have buffer resource and can use report and alarm; If the A sign is not A1, be that A is masked as A0 or for empty, illustrates that taking of buffer A also do not reach 512, that is to say upwards to take up room in addition, i.e. write data inside, the clock selecting control module is selected the clock that clock extracts for buffer B input E1 of reading of buffer B.Like this, the reading and writing clock of the second road E1 all is the clock that input E1 extracts, and buffer B takies and remains unchanged, and has protected the data of buffer B can not occur covering.Simultaneously, it is system clock that the clock selecting control module is selected the clock of reading of buffer A, and first via E1 begins to enable timing function again, and buffer A serves as timing data buffering area again, and system changes the state of judging buffer A into, and deterministic process is described with preamble.
When taking of buffer B equals 1, illustrate that buffer B has read sky, system will put B and be masked as B0.System's state of interpretation A sign again if A is masked as A0, illustrates that buffer A is also read sky then, and at this moment, buffer A and buffer B are read sky, and system does not have buffer resource and can use report and alarm; If the A sign is not A0, promptly A is masked as A1 or for empty, illustrates that taking of buffer A also do not narrow down to 1, that is to say to take up room downwards in addition, and the clock selecting control module is selected the clock that clock extracts for buffer B input E1 of reading of buffer B.Like this, the reading and writing clock of the second road E1 all is the clock that input E1 extracts, and buffer B takies and remains unchanged, and has protected the data of buffer B can not occur reading again.Simultaneously, it is system clock that the clock selecting control module is selected the clock of reading of buffer A, and first via E1 begins to enable timing function again, and buffer A serves as timing data buffering area again, and system changes the state of judging buffer A into, and deterministic process is described with preamble.
Here, only with two buffer, be that buffer A and buffer B carry out level and be linked as example and describe the present invention, but those skilled in the art will be appreciated that, the present invention is not limited to two buffer cascades, promptly, the present invention is equally applicable to the situation of a plurality of buffer cascades, such as, if three buffer are arranged, be buffer A, buffer B and buffer C carry out cascade, if buffer A has write full (reading sky), a buffer who is not write full (reading sky) will select in system from buffer B and buffer C, as buffering area regularly again, such as having selected buffer B, when buffer B is write full (reading sky), system selects a buffer who is not write full (reading sky) as buffering area regularly more again from buffer C and buffer A, is all write full (reading sky) up to all buffer, and system is report and alarm.Detailed process is identical with the situation of described two buffer of preamble, here just repeats no more.
In sum, the present invention is the circular buffer that is linked to be by a plurality of buffer levels, current conduct more regularly the buffer of buffering area write full or when reading sky, system selects being expired by not writing of other or reads empty buffer conduct timing buffering area again, all write completely or read sky up to all buffer, so just expanded the memory space of timing buffer again, covering or the accentuating phenomenon of having avoided data have been arranged.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (9)
1, a kind of buffer device of timing again is characterized in that, comprising: buffer module and selection control module,
Described buffer module cascade, road E1 passage in the corresponding E1 chip of each buffer module;
Select control module: be connected with buffer module respectively, and select timing buffer module again in buffer module, the buffer module of selecting other cascade is as the non-buffer module of timing again;
The clock that the described buffer module of timing again will be extracted from the described buffer module of timing again input E1 writes the described buffer module of timing again as writing clock with data, and clock is read in the conduct of using system clock then, and data are read the described buffer module of timing again.
2, a kind of buffer device of timing more according to claim 1 is characterized in that described selection control module specifically comprises:
Clock alternative module: the selective system clock as more regularly buffer module read clock, and select from the described non-clock that regularly extracts the buffer module input E1 signal again as described non-more regularly buffer module read clock;
Clock selection module: be connected with buffer module by clock alternative module, control clock alternative module is read clock to each buffer module selection, when the described buffer module of timing is again write full or is read sky, triggering the described timing again of change buffer module is the non-buffer module of timing again, selects regularly buffer module again in a plurality of buffer modules again.
3, a kind of buffer device regularly more according to claim 1 and 2 is characterized in that, described non-the writing clock and read clock and all use from the described non-clock that regularly extracts the buffer module input E1 again of buffer module regularly again.
4, a kind of method of timing again is characterized in that, comprising:
Regularly buffer module is selected by A, system again in the buffer module of cascade, the buffer module of selecting other cascade is as the non-buffer module of timing again;
The clock that B, the described buffer module of timing again will be extracted from the described buffer module of timing again input E1 writes the described buffer module of timing again as writing clock with data, and clock is read in the conduct of using system clock then, and data are read the described buffer module of timing again.
5, a kind of method of timing more according to claim 4 is characterized in that described steps A specifically comprises:
The state of current buffer module is judged by A1, system, if described buffer module is not write full or do not read sky, then selects described current buffer module as buffer module regularly again, and the buffer module of other cascade is as non-time block again, otherwise, execution in step A2;
The state of the buffer module of A2, system's judgement and described current buffer module cascade, if the buffer module of described cascade is not write full or is not read sky, the buffer module of then selecting described cascade is as the current buffer module of timing again, otherwise repeat this step, all write full or all read sky up to all buffer modules, system reports warning.
6, a kind of method of timing more according to claim 5 is characterized in that, also comprises before carrying out described steps A 1:
During initialization, first buffer module conduct timing buffer module is again selected by system, and other is the non-buffer module of timing again.The clock that clock selection module extracts from input E1 is as the clock of writing of first buffer module, and the selective system clock is as the clock of reading of first buffer module; Simultaneously for the buffer module of other cascade, select the clock that from the buffer module input E1 signal of each cascade, extracts writing clock and reading clock as the buffer module of each cascade.
7, a kind of method of timing more according to claim 5 is characterized in that described steps A 1 specifically comprises:
The state of current buffer module is judged by system, if described buffer module is not write full or is not read sky, then select described current buffer module conduct timing buffer module again, the buffer module of other cascade is as non-time block again, clock selection module select the clock that extracts from current buffer module input E1 as more regularly buffer module write clock, the selective system clock as more regularly buffer module read clock, and select to import clock the writing clock and reading clock of extracting the E1 signal as the non-buffer module of timing again from the buffer module of cascade, otherwise, execution in step A2.
8, a kind of method of timing more according to claim 5 is characterized in that described steps A 2 specifically comprises:
The state of the buffer module of system's judgement and described current buffer module cascade, if the buffer module of described cascade is not write full or is not read sky, the buffer module of then selecting described cascade is as buffer module regularly again, changes current buffer module as non-buffer module regularly again; Clock selection module select the clock that extracts from the buffer module input E1 of cascade as more regularly buffer module write clock, the selective system clock as more regularly buffering area read clock; Select simultaneously from the non-clock that regularly extracts the buffer module E1 signal again as non-the writing clock and read clock of buffer module regularly again, otherwise repeat this step, all write full or all read sky up to all buffer modules, system reports warning.
9, a kind of method of timing more according to claim 4 is characterized in that described step B also comprises: clock the writing clock and reading clock as the described non-buffer module of timing again that will extract from the described non-buffer module of timing again input E1.
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| CN 200610140440 CN1968061A (en) | 2006-10-08 | 2006-10-08 | Re-timing apparatus and method |
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| CN 200610140440 CN1968061A (en) | 2006-10-08 | 2006-10-08 | Re-timing apparatus and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101674479B (en) * | 2008-09-11 | 2013-07-03 | 索尼株式会社 | Information processing apparatus and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101674479B (en) * | 2008-09-11 | 2013-07-03 | 索尼株式会社 | Information processing apparatus and method |
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Open date: 20070523 |