CN1317842C - Super large-scale cross connection device and method used for synchronous digital transmission system - Google Patents
Super large-scale cross connection device and method used for synchronous digital transmission system Download PDFInfo
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- CN1317842C CN1317842C CNB031398987A CN03139898A CN1317842C CN 1317842 C CN1317842 C CN 1317842C CN B031398987 A CNB031398987 A CN B031398987A CN 03139898 A CN03139898 A CN 03139898A CN 1317842 C CN1317842 C CN 1317842C
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Abstract
The present invention relates to a very large scale cross connection device and a method thereof for a synchronous digital transmission system. The device comprises an input data conversion module, an output data conversion module, a microcomputer interface module and a switching and connecting module, wherein the input data conversion module is used for downloading data from a DIN bus line and demultiplexing, a programmable unit of the input data conversion module can insert programmable delay into SIN and DOUT bus lines according to needs, and the programmable delay is allocated to a corresponding data memory; the output data conversion module selects output data in each time slot and transmits the output data onto the DOUT bus line for multiplexing, and the programmable unit of the output data conversion module can insert the programmable delay into the SIN and DOUT bus lines according to needs; the microcomputer interface module is used for realizing the configuration of switching rules of an external CPU to a chip register and a connection memory; the switching and connecting module is used for realizing the cross connection of data. The present invention is characterized in that the input data conversion module comprises an alignment module used for realizing byte alignment, frame boundary alignment and the alignment of 64 paths of frames. The present invention has the advantages that the use quantity of DM of the cross connection device is reduced; the capacity of each DM is reduced; the cross connection scale for completing 64 paths of STM-4/STS-12 signals is reduced; fabrication is easy.
Description
Technical field
The present invention relates to the Digital Transmission field, specifically the particularly ultra-large cross connection device in the synchronous digital transmission system relates to time-division, the space division cross jockey of the Synchronous Digital Hierarchy of multichannel, two-forty.
Background technology
So-called digital crossover jockey, be meant and pass through cross-connect matrix, according to the cross connection pattern of cross connection pattern of depositing in advance or dynamic calculation, the time slot of channel signal of input to be rearranged, the signal that makes it to become speed such as new is exported from output channel.Continuous increase along with the Digital Transmission scale, at present, the access scale of this digital crossover jockey has reached 64 passages, access rate has reached 622.08Mbps (corresponding to the STM-4 speed of SDH, the STS-12 speed of SONET), the minimum particle that intersects is STM-0 (SDH) or STS-1 (SONET), requires digital crossover to connect simultaneously and still will keep clog-free interconnection.
At Chinese patent application " the ultra-large cross connection device in the synchronous digital transmission equipment " (number of patent application: 00114059.0), proposed a kind ofly to finish that to insert port number be 16, access rate is the clog-free cross-coupled cross connection device of 155.52Mbps.Comprise: the input data mux block, realize that from DIN bus data download, demultiplexing wherein programmable unit can insert programmable delay to SIN and DOUT bus as required, and distributes to corresponding data storage; The dateout conversion block, it is multiplexing to select dateout to deliver on the DOUT bus at each time slot, and programmable unit wherein can insert programmable delay to SIN and DOUT bus as required; The microcomputer interface piece is realized the configuration of external CPU to chip register and connection memory transactions rule; Switching Module is realized the interconnection of data.In this cross connection device, the number that needs data storage (DM) altogether is 8 * 8=64, and wherein each DM utilizes one 1080 * 8 dual port RAM to realize, needs 64 RAM to realize the DM function altogether.For the cross-connecting signals that guarantees all passages can both in time write, read DM, requirement utilizes the clock of 38.88Mhz that the data of 19.44Mbps are sampled, and utilize the clock of 38.88Mhz that data are write among the RAM, the clock of reading of RAM also is 38.88Mhz.
For the access scale is 64 passages, access rate is 622.08Mbps, minimum cross time-slot is the cross connection device of STM-0 or STS-1, if still adopt the thought of above-mentioned patent, then the number of needed DM is 32 * 32=1024, and each DM need utilize one 4320 * 8 dual port RAM to realize.In addition, need sample with the clock of 155.52Mhz for the data of 77.76Mbps, and be written among the RAM of DM.So the frequency of the clock that DM is read and write is 77.76 * 2=155.52Mhz.That is to say, only be to make up DM, be 1024 with regard to the number that needs dual port RAM, and the read-write frequency of RAM all reaches the high speed of 155.52Mhz.A scale like this realizes it being unpractical on single chip, and its cost also is very expensive.
Summary of the invention
The objective of the invention is to propose a kind of ultra-large cross connection device that is used for synchronous digital transmission system, reduce the usage quantity of DM in the cross connection device, reduce the capacity of each DM, dwindle in order to finish the cross-coupled scale of 64 road STM-4/STS-12 signals, make it to be easy to make.
The invention discloses a kind of follow-on cross connection device, be used for synchronous digital transmission system and realize that the access scale is the interconnection of the STM-4/STS-12 signal of 64 passages.In this device, input module, output module, CM module, DM module, cross-connect module have been comprised.The definition of these modules is consistent with the definition of patent " the ultra-large cross connection device in the synchronous digital transmission equipment ".But in order to adapt to the characteristics of STM-4/STS-12 frame, input module has increased byte-aligned, the frame boundaries alignment and the function alignment of 64 road STM-4/STS-12 frames.
The cross connection device that the present invention proposes is based on the exchange principle of " order writes control and reads ", and cross-connect module all utilizes combinational logic and register to finish, and on the structure, has adopted distributed cross-coupled structure.That is to say, originally the interconnection of 64 passages is divided into 2 identical 32 passage interconnections independent of each other again of structure earlier, and then, finish the selection of 2 32 road cross-coupled output signals, thereby finish the interconnection of whole 64 road STM-4/STS-12 by a selector.In 32 road cross-connect modules, use the cross-coupled method of single-bit to finish of the interconnection of 32 tunnel input channels to 64 tunnel output channels.
Specifically, the invention discloses a kind of ultra-large cross connection device that is used for synchronous digital transmission system, comprise: the input data conversion module, realization is from DIN bus data download, demultiplexing, wherein programmable unit can insert programmable delay to SIN and DOUT bus as required, and distributes to corresponding data storage; Output data converting module, it is multiplexing to select dateout to deliver on the DOUT bus at each time slot, and wherein programmable unit can insert programmable delay to SIN and DOUT bus as required; The microcomputer interface piece is realized the configuration of external CPU to chip register and connection memory transactions rule; The exchange link block realizes the interconnection of data; Also comprise alignment module in the described input data mux block, be used to realize byte-aligned, frame boundaries alignment and the alignment of 64 road frames.
Described cross-connect module all utilizes combinational logic and register to finish, and on the structure, has adopted distributed cross-coupled structure.
Described distributed interconnection is that the interconnection of 64 passages is divided into 2 identical 32 passage interconnections independent of each other again of structure earlier, and then by a selector, finish the selection of 2 32 road cross-coupled output signals, thereby finish the interconnection of whole 64 paths.
Described in 32 road cross-connect modules, use the cross-coupled method of single-bit to finish of the interconnection of 32 tunnel input channels to 64 tunnel output channels.
In the described cross-coupled interconnection line, intersect the direction of transfer of address wire with to intersect the direction of data flow opposite.
The minimum repetitive of a described interconnection storage time slots.
Described alignment module is extracted channel clock from the clock and data recovery module, make all parallel data streams be synchronized with system clock, alignment module is also carried out byte-aligned and frame boundaries registration process, finishes the conversion of serial data to the parallel data of 8 bit bit wides by " string and conversion " module simultaneously.
Described parallel data is input to respectively in 64 DM modules, in conjunction with the principle of cross-connect module according to " sequential writing on and controlled reading ", finishes the interconnection of 64 circuit-switched data stream; Pass through the overhead processing of output data converting module afterwards, finish the conversion of parallel data, export by chip by LVDS to serial data stream by " and string conversion " module to data flow.
In the present invention, the number of the DM of use is 64, and the memory capacity of each DM is 24 * 8 bits.Compare with using the resulting result of patent " the ultra-large cross connection device in the synchronous digital transmission equipment ", the quantity of DM drops to 64 from 1024, and the byte number of each DM drops to 24 by 4320.Thereby make the scale of cross connection device dwindle greatly.
Description of drawings
Fig. 1 is a simplification calcspar of the present invention, comprising an embodiment: the interconnection of 64 road STM-4/STS-12;
Fig. 2 is the content organization chart of DM among Fig. 1;
Fig. 3 is a cross-connect module schematic diagram among Fig. 1;
Fig. 4 is the realization block diagram of Fig. 3;
Fig. 5 is that 32 tunnel interconnection submodules are realized block diagram among Fig. 4.
Embodiment
To be example with the embodiment of 64 road STM-4/STS-12 interconnection chips of the present invention below, introduce specific implementation of the present invention.
As shown in Figure 1,64 tunnel speed are the serial data stream RX1 of the STM-4/STS-12 of 622Mbps, RX2 ..., RX64 is input in the chip by the LVDS port, carry out the extraction and the bit aligned of channel clock handles through clock and data recovery module (CDR), finish the conversion of serial data by " string and conversion " module simultaneously, generate D1[7:0 to the parallel data of 8 bit bit wides], D2[7:0], ..., D64[7:0].Input module is finished the byte-aligned and the frame boundaries alignment of parallel data, and makes all STM-4/STS-12 parallel data streams be synchronized with system clock, and such 64 road STM-4/STS-12 can carry out correct interconnection according to the STM-0/STS-1 time slot.Be input to respectively 64 DM modules from the parallel data of input module output,, finished the interconnection of 64 road STM-4/STS-12 in conjunction with the principle of cross-connect module according to " sequential writing on and controlled reading ".Pass through the overhead processing of output module to STM-4/STS-12 afterwards, (" overhead processing " is the processing of refering in particular to the section overhead byte here, comprises the regeneration of frame head byte, extracts or insert specific overhead byte, the regeneration of parity byte.) finish the conversion of parallel data by " and string conversion " module to 622.08Mbps serial STM-4/STS-12 data flow, export by chip by LVDS.
Fig. 2 has shown the interior tissue mode of DM module.Because the frame of a STM-4 is to be combined according to interleaving multiplexing mode by 12 STM-0 time slots, from the angle of time slot, this compound mode is fixed, and is to repeat in the cycle with 12 bytes.So, finish the interconnection of all 768 the STM-0 time slots among 64 road STM-4, we do not need to store the data of a whole frame, carry out interconnection again, we only need 12 bytes of minimum repetitive----of these time slots of storage, these 12 bytes are carried out interconnection, periodically repeat the interconnection that such interconnection action can be finished all bytes in the whole frame then.With improve before compare, the capacity of each DM module narrows down to 24 bytes greatly by 4320 bytes.These 24 bytes are divided into two zone: PAGE0 and PAGE1 again.Such arrangement can guarantee cross-coupled continuity.When the PAGE0 order write parallel data stream, 12 time slots storing among the PAGE1 were exported simultaneously, finish the interconnection of 12 time slot bytes in 12 system clock cycles (12.86ns).Then, after PAGE0 write completely, PAGE1 was switched to the pattern of writing, and order writes parallel data stream, and 12 time slots storing among the PAGE0 are exported simultaneously, finish the interconnection of 12 time slot bytes in 12 system clock cycles.The interconnection of bytes all in the STM-4 frame is finally finished in the operation that goes round and begins again like this.
Fig. 3 has provided the schematic diagram of cross-connect module.CM module output interconnection address figure, its structure and DM are similar, and the capacity of each CM is 24 * 10bits, is divided into two pages, every page of 12 * 10bits.The corresponding CM of each input channel has 64 CM like this.(m n) represents each time slot of input channel, and m represents the input channel sequence number, and span 1-64, n represent the sequence of time slots number of a passage, span (1-12) with CM for we.At any time, carry that one page of interconnection address to be referred to as active page to cross-connect module, another page or leaf is referred to as non-active page.Microcomputer interface can carry out read and write access to non-active page.Address stored is represented the position of output time solt among the CM, is made up of 10bits, wherein low 4 bit representation timeslot numbers, high 6 bit representation channel numbers.For example, CM (1,1)=89 ' d, expression is cross connected to the 1st time slot in the 1 tunnel input channel the 9th time slot of the 5 tunnel output channel.The interconnection address of exporting from CM is divided into two parts, and time slot intersection address (4bits) is delivered to the DMx module and finished interconnection for the first time, and the DMx module is combined by DM module and time slot Cross module.Passage intersection address (6bits) is delivered to the Mux64 module and is finished interconnection for the second time, thereby finishes whole interconnection.
Fig. 4 has provided the implementation method of Fig. 3.Owing to disposablely finish 64 tunnel interconnections and relatively be difficult to design, so that we are divided into 64 tunnel interconnection on two structures is duplicate, but 32 tunnel interconnection submodules independent of each other.Each 32 tunnel interconnection submodule can independently be finished the clog-free formula interconnection based on STM-0/STS-1 of 32 road STM-4/STS-12.Preceding 32 channel parallel datas are input to and finish the interconnection of preceding 32 circuit-switched data to all output channels in the TSI_SUB_1 submodule, and 32 circuit-switched data were to the interconnection of all output channels after back 32 channel parallel datas were input to and finish in the TSI_SUB_2 submodule.Then, the dateout of TSI_SUB_1 and TSI_SUB_2 submodule enters into the MUX2 module and finishes selection, finally finishes the interconnection of all 64 tunnel input STM-4/STS-12 frames to all 64 tunnel output STM-4/STS-12 frames.
Fig. 5 has provided the realization block diagram of one 32 tunnel interconnection submodule.Delivering to 32 tunnel 8 bit parallel data of 32 tunnel interconnection submodules sorts out according to bit earlier, bit 0 signal of also just saying all 32 channel parallel datas is classified as the 1st group, bit 1 signal of all 32 channel parallel datas is classified as the 2nd group, ..., bit 7 signals of all 32 channel parallel datas are classified as the 8th group.Each group signal is sent into by DM_bit, and TS_x_bit finishes the single-bit interconnection of input data in the single-bit cross-connection unit that CH_x_bit forms.At the output port of 32 tunnel interconnection submodules, these bit signal groups are reassembled into parallel data output.The DM_bit functions of modules is the same with the DM module, is used for storing the single-bit input traffic.The TS_x_bit module is finished the time slot interconnection of a bit of bit to 64 output channel of 32 input channels.The CH_x_bit module is finished the passage interconnection of a bit of bit to 64 output channel of 32 input channels.Consider and reduce the intersection between the holding wire and effectively utilize area of chip that single-bit is cross-coupled to put in order as shown in Figure 5.Equally, in order effectively to utilize area of chip, increase the completion rate of interconnection line, intersect the direction of transfer of address wire with to intersect the direction of data flow opposite.For the delay of the holding wire that reduces long Distance Transmission, need to give the former end of these holding wires to insert big driving buffer.
More than having described principle of the present invention uses and embodiment.Though the present invention is based on the improvement of patent " the ultra-large cross connection device in the synchronous digital transmission equipment " to 64 * 64 road STM-4/STS-12 cross connection devices, but according to above analysis, be not difficult to find, as long as change slightly, the present invention can also use and more massive interconnection, as 80 * 80 road STM-4/STS-12 time slot cross chips, 96 * 96 road STM-4/STS-12 time slot cross chips.
Claims (5)
1. ultra-large cross connection device that is used for synchronous digital transmission system, comprise: the input data conversion module, realization is from DIN bus data download, demultiplexing, and wherein programmable unit can insert programmable delay to SIN and DOUT bus as required, and distributes to corresponding data storage; Output data converting module, it is multiplexing to select dateout to deliver on the DOUT bus at each time slot, and wherein programmable unit can insert programmable delay to SIN and DOUT bus as required; The microcomputer interface piece is realized the configuration of external CPU to chip register and connection memory transactions rule; Cross-connect module is realized the interconnection of data; It is characterized in that, also comprise alignment module in the described input data conversion module, be used to realize byte-aligned; frame boundaries alignment and the alignment of 64 road frames; described cross-connect module all utilizes combinational logic and register to finish; adopted distributed cross-coupled structure; distributed interconnection is that the interconnection of 64 paths is divided into 2 identical 32 paths interconnections independent of each other again of structure earlier; and then pass through a selector; finish the selection of 2 32 road cross-coupled output signals; thus the interconnection of whole 64 paths finished; and in described 32 tunnel interconnections, the cross-coupled method of use single-bit is finished the interconnection of 32 tunnel input channels to 64 tunnel output channels.
2. the ultra-large cross connection device that is used for synchronous digital transmission system as claimed in claim 1 is characterized in that, in the described cross-coupled interconnection line, intersects the direction of transfer of address wire with to intersect the direction of data flow opposite.
3. the ultra-large cross connection device that is used for synchronous digital transmission system as claimed in claim 2 is characterized in that, the minimum repetitive of a described interconnection storage time slots.
4. the ultra-large cross connection device that is used for synchronous digital transmission system as claimed in claim 1, it is characterized in that, described alignment module is extracted channel clock from the clock and data recovery module, make all parallel data streams be synchronized with system clock, alignment module is also carried out byte-aligned and frame boundaries registration process, finishes the conversion of serial data to the parallel data of 8 bit bit wides by " string and conversion " module simultaneously.
5. the ultra-large cross connection device that is used for synchronous digital transmission system as claimed in claim 4, it is characterized in that, described parallel data is input to respectively in 64 data memory modules, in conjunction with the principle of cross-connect module, finish the interconnection of 64 circuit-switched data stream according to " sequential writing on and controlled reading "; Pass through the overhead processing of output data converting module afterwards, finish the conversion of parallel data, export by chip by LVDS to serial data stream by " and string conversion " module to data flow.
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100339349C (en) * | 2004-09-22 | 2007-09-26 | 内蒙古自治区畜牧科学院 | Preparation method of long chain fatty acid calcium salt |
| CN100433591C (en) * | 2004-09-30 | 2008-11-12 | 烽火通信科技股份有限公司 | Bus delay correcting method for 40G SDH system |
| CN101145873B (en) * | 2007-03-21 | 2012-09-05 | 中兴通讯股份有限公司 | A method and system for improving crossed capacity of SDH service |
| CN101145876B (en) * | 2007-07-25 | 2011-05-25 | 中兴通讯股份有限公司 | Time slot configuration method and time slot configuration device |
| CN101394335B (en) * | 2007-09-20 | 2011-01-19 | 中兴通讯股份有限公司 | Synchronous digital cross connecting self-routing method and system |
| CN101483504B (en) * | 2009-02-10 | 2012-05-23 | 华为技术有限公司 | Implementation method and apparatus for space division, time division cross-interaction |
| CN101605082A (en) * | 2009-07-21 | 2009-12-16 | 中兴通讯股份有限公司 | Realize the device and method that multi-channel overhead bus intersects |
| CN105630825B (en) * | 2014-11-04 | 2021-04-06 | 中兴通讯股份有限公司 | Data conversion method and device |
| CN105812062B (en) * | 2016-03-04 | 2018-11-30 | 烽火通信科技股份有限公司 | Optical transfer network MLD method for interface adaptation and system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1248878A (en) * | 1998-09-22 | 2000-03-29 | 深圳市华为技术有限公司 | Synchronous digital sequence space division cross connection equipment |
| CN1297296A (en) * | 2000-02-01 | 2001-05-30 | 深圳市中兴通讯股份有限公司 | Very-large-scale cross connector in synchronous digital transmission device |
| WO2002054821A2 (en) * | 2000-12-29 | 2002-07-11 | Marconi Communications Limited | Digital cross-connect |
-
2003
- 2003-07-17 CN CNB031398987A patent/CN1317842C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1248878A (en) * | 1998-09-22 | 2000-03-29 | 深圳市华为技术有限公司 | Synchronous digital sequence space division cross connection equipment |
| CN1297296A (en) * | 2000-02-01 | 2001-05-30 | 深圳市中兴通讯股份有限公司 | Very-large-scale cross connector in synchronous digital transmission device |
| WO2002054821A2 (en) * | 2000-12-29 | 2002-07-11 | Marconi Communications Limited | Digital cross-connect |
Non-Patent Citations (4)
| Title |
|---|
| WGS1608-超大规模交叉连接芯片设计 田耘，光通信研究，第2期 2000 * |
| WGS1608-超大规模交叉连接芯片设计 田耘，光通信研究，第2期 2000;数字同步网 洪志敏，电信快报，第3期 2000;同步光纤通信系统中的十个基本问题 林达权，黄良碧，崔玉萍，叶忠美，现代电子技术，第10期 1999 * |
| 同步光纤通信系统中的十个基本问题 林达权，黄良碧，崔玉萍，叶忠美，现代电子技术，第10期 1999 * |
| 数字同步网 洪志敏，电信快报，第3期 2000 * |
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