CN1248878A - Synchronous digital sequence space division cross connection equipment - Google Patents
Synchronous digital sequence space division cross connection equipment Download PDFInfo
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- CN1248878A CN1248878A CN 98118987 CN98118987A CN1248878A CN 1248878 A CN1248878 A CN 1248878A CN 98118987 CN98118987 CN 98118987 CN 98118987 A CN98118987 A CN 98118987A CN 1248878 A CN1248878 A CN 1248878A
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Abstract
The present invention relates to a SDH space-division cross connection equipment structure, i. e. adopts a cross control unit integrally formed chip structure with two working modes of cross kernel unit and control. The described kernel unit includes 64 cross matrixes, and the described control unit includes multiplex control register for configurating cross matrix control data, main RAM and stand-by RAM respectively for working and stand-by, command register for selecting working mode and first change-over switch (MUX1) for switching main and stand-by RAM and second change-over switch for switching two working modes (register/RAM). Said invention flexibly implements 4/4 or 4/1 cross connection equipment, and provides a switching mechanism without error code, and its operation is convenient.
Description
The present invention relates to the digital information transmission technical in the telecommunication, more specifically relating to the function of exchange is the network equipment of feature.
Digital cross connect equipment (DXC) is an important transmission equipment in Synchronous Digital Hierarchy (SDH) network, and it can realize effective management of synchronous transmission net, network protection reliably and automation distribution and network monitoring.DXC can transmit the professional and business that is connected between unlike signal of different stage SDH, and CCITT (CCITT) has only defined function to the suggestion of SDH, but the physics realization structure of this equipment of concrete regulation not.
The TST cross connecting structure is can realize clog-free connection and than other structures (for example STS etc.) cost effective device more, because its cross-coupled scale can be determined by required exchange capacity under every kind of situation.
The present invention is the space division cross connection equipment in a kind of TST cross connecting structure.
Digital crossover connects intersects the speed of data and rank by it and can be divided into kind such as 4/4 and 4/1.Purpose of the present invention realizes finishing 4/4 exactly, can finish the space division cross connection equipment of 4/1 cross connect function again.
For reaching this purpose, the solution that the present invention takes is: Synchronous Digital Hierarchy (SDH) space division cross connection equipment comprises that one contains the intersection kernel unit of cross matrix and the control unit that intersects; Intersect control unit to intersect kernel unit output control signal (CCSR, CCSRa), to realize 4/4 or 4/1 two kind of interconnection;
Described intersection control unit comprises multiplexing control register, the standby random access memory ram of advocating peace, switching controls register, the first multicircuit switch MUX1, command register and the second multicircuit switch MUX2; Main random access memory ram, standby random access memory ram and switching controls register link to each other with first multicircuit switch; Multiplexing control register, command register and first multicircuit switch link to each other with second multicircuit switch.The first multicircuit switch MUX1 changes the control data that receives main RAM or standby RAM under the signal controlling of switching controls register; The second multicircuit switch MUX2 changes ground and receives the output of the first multicircuit switch MUX1 or the output of described multiplexing control register under the command signal COM_REG of command register control, and the control signal CCS of output control intersection kernel unit.
Described intersection control unit also comprises a d type flip flop on output signal (SR) path that is connected the switching controls register, it is the control end of the Q termination first multicircuit switch MUX1 of d type flip flop, and the D of trigger, CE, C end respectively with the switching controls register, the switching controls position (GEN) of command register, and frame-synchronizing impulse input (SFP) is continuous, switches to realize no error code.
Because the present invention adopts the corresponding two cover cross matrix control units of each cross-connection unit, wherein one the cover be used for current exchange another set of give over to switch refresh, Cross Connect equipment was controlled and inserted in the switching of two inner rooms by synchronizing signal signal content has nothing to do, thereby have relative independentability, simplified the implementation process of handover operation greatly.Because what adopt is 4/1 cross modal, the SDH signal that enters Cross Connect equipment is that frame alignment and branch road are aimed at, and its frame head position is by intersecting the unified control of control unit, produce the switching synchronizing signal by frame alignment control signal, the frame head that assurance switches in every road SDH signal carries out, thereby has realized the zero defect switching.In addition, the present invention has adopted intersection kernel unit and the design of intersection control unit one, can realize 4/4 interconnection of different cross modals: 64*64 and 4/1 interconnection of 16*16 by the working method position in the command register in the configuration intersection control unit.
Now be described with reference to the accompanying drawings embodiments of the invention:
Fig. 1 is the circuit connection diagram of space division cross connection equipment embodiment of the present invention;
Fig. 2 is the composition schematic diagram of intersection kernel unit shown in Figure 1;
Fig. 3 is the circuit connection diagram of intersection control unit shown in Figure 1;
Fig. 4 illustrates the situation when intersection control unit shown in Figure 3 is in the register working method;
Fig. 5 is the schematic diagram of each register cell content in the explanation intersection control unit, wherein
Fig. 5 a represents each location contents of multiplexing control register;
Fig. 5 b represents each location contents of command register;
Fig. 5 c represents the location contents of switching controls register;
Fig. 6 is that intersection control unit shown in Figure 3 is in the schematic diagram under the RAM working method;
Fig. 7 is profile and each pin schematic diagram of the space division cross connection equipment sheet of the embodiment of the invention.
Fig. 8 and Fig. 9 are respectively explanation the present invention and realize control principle and the signal sequence schematic diagram that zero defect switches;
At first referring to Fig. 7, the figure shows profile and each pin of one embodiment of the invention, wherein the implication of each pin mark is as follows:
UHW0～UHW63 is the upstream data input pin
DHW0～DHW63 is the downlink data output pin
/ RST-reset signal
SFP-frame-synchronizing impulse input
The CK38-38M clock
The CK19-19M clock
TST mode: 0: normal mode of operation, 1: test pattern
/ RD-μ P interface read signal end
/ WR-μ P interface write signal end
/ ACS-chip selection signal
Da-μ P interface data
Ad-μ P interface IP address
Above-mentioned last five ends are formed MPU (Microprocessor Unit) interface end 601.
The internal structure that Fig. 1 then illustrates this embodiment comprises the intersection kernel unit 11 and control unit 12 two large divisions of intersecting, and these two parts are by holding wire CCS0[5:0]～CCS63[5:0] connect.
Fig. 2 shows intersection kernel unit 11 and includes 64 cross matrixes (100～163).The signal UHW that the kernel unit 11 of intersecting receives from upstream data input pin UHW0～UHW63, its cross matrix 100～163 carries out interconnection under the control (below will describe in detail) of the signal CCS0～CCS63 of intersection control unit 12, and output downlink data signal DHW is to downlink data output pin DHW0～DHW63.
Fig. 3 shows the structure of intersection control unit 12 and forms.Scheme as seen thus, this control unit comprises multiplexing control register 22, and its each memory cell mark SEL5～SEL0 represents control signal CCS[5:0 respectively shown in Fig. 5 a].In order to realize the switching under the register working method, multiplexing control register 22 is connected with multiplexing control temporary register 21 by a d type flip flop 27, the D of this trigger 27 (D0, D1 ..., D5), CE, C each the end link to each other with multiplexing control temporary register 21, GEN and SFP signal respectively, its Q (Q0, Q1 ..., Q5) end links multiplex controller 22.D type flip flop 27, multiplexing control temporary register 21 and multiplexing register 22 have 64 groups, each group is exported control datas by second multicircuit switch 32 to intersection kernel unit 11, the interconnection of control intersection kernel unit 11 interior cross matrixes, thereby 4/4 cross connect function of realization 64*64.
According to Fig. 3, the control unit 12 that intersects comprises that also main RAM25 links to each other with first multicircuit switch 31 with standby RAM26, under the control of switching controls register 23, first multicircuit switch 31 is transferred to intersection kernel unit 11 with the control data signal of main RAM25 or standby RAM26 through second multicircuit switch 32.Main RAM25 and standby RAM26 have 16 groups, the switching controls register is 16, shown in Fig. 5 c, the operating state of every one group of master RAM25 of control and standby RAM26, when being 0 (or 1), certain position represents the main RAM25 work of its control, be the standby RAM26 work that its control is represented in 1 (or 0), thereby realize 4/1 cross connect function of 16*16.
According to Fig. 3, the intersection control unit 12 of this embodiment also comprises the command register 24 that is used for mask register or RAM working method, and this command register 24 is an eight bit register, and its memory cell assignment implication is shown in Fig. 5 b, in this example:
GEN is that permission is switched in 0 expression; GEN is that 1 expression switching is forbidden.
REN is that read register REG/RAM content is forbidden in 1 expression; Be that 0 expression allows to read the REG/RAM content;
OEN is that 1 expression output is ternary, 0 expression dateout;
REG/RAM:0 represents register REG mode, 1 expression RAM mode;
Below again in conjunction with Fig. 4 and Fig. 6 to the embodiment of the invention 4/4,4/1 two kind of cross-coupled switching and operation principle be elaborated.
Order COM_REG when command register 24, be set to " selecting the register working method ", promptly its most last unit R EG/RAM is 0 o'clock, intersection control unit 12, promptly structure is finished 4/4 cross connect function of 64*64 as shown in Figure 4, and output intersects control signal CCSR to intersecting kernel unit 11.
More particularly, under the register working method, the control unit 12 that intersects selects the data of multiplexing control register 22 as crossing control data, article 64, input signal cable UHW (63:0) enters intersection kernel unit 11, cross matrix annexation by crossing control data control intersection kernel unit 11 is connected to downlink data signal line DHW (63:0) with holding wire UHW (63:0).This moment, each road upstream data UHW signal was done as a whole the intersection, thereby realized 4/4 interconnection of 64*64.
On the other hand when command register is set to " selecting the RAM working method ", be that REG/RAM byte assignment is 1 o'clock, then as shown in Figure 6, the control unit 12 that intersects is under the RAM working method, by RAM25, data in 26 are as the interconnection relation between crossing control data control cross matrix 100～163 (Fig. 2) is from UHW to DHW, and be by row in SDH frame structure to intersect to each road UHW data this moment, thereby realize 4/1 interconnection.
More particularly, at this moment, signal UHW (63:0) is divided into 16 groups (1 group of 4bit) when intersecting.UHW (4n), UHW (4n+1), UHW (4n+2), UHW (4n+3) [n=0,1,2 ... 15] be one group.DHW (63～0) also is divided into 16 groups by the same manner is corresponding, every group has active/standby two RAM25,26, its main and standby relation control is finished by the switching register 23 shown in Fig. 5 C, this signal comprises 8 high-order H bytes (8～15) and 8 low level L bytes (0～7), and its each 1bit0/1 controls 1 group.Be 0 o'clock, represent main RAM work; Be 1 o'clock, expression is equipped with RAM work.Every group of UHW signal to the annexation of DHW signal by the Data Control in the corresponding RAM, data in the RAM are to organize by the row of SDH STM-1 frame signal, thereby every group of UHW also undertake by row to the annexation of DHW, thereby realize 4/1 interconnection of 16*16 (one group of 4bit).
Below in conjunction with Fig. 8 and Fig. 9 the realization that no error code switches is described.
As shown in Figure 8, the SDH signal is to have frame structure A1, A2 ... data, no error code switches the integrality that will guarantee to switch this frame structure of front and back exactly, that is to say to guarantee to realize switching as shown in Figure 8 that the present invention utilizes the rising edge of the frame-synchronizing impulse SFP of outside input to indicate frame head position Hd's at Hd place, frame head position.In other words, as long as switching when aliging with the frame head of SDH signal, the rising edge of assurance synchronization pulse SFP just can realize not having the error code switching.
Fig. 9 is the control principle figure that realizes that no error code switches under the RAM control mode of the present invention, how it and Fig. 6 schematic diagram difference only have been a d type flip flop 71, the D of this trigger, CE, each end of C link to each other with switching controls register, GEN and SFP signal respectively, and its Q terminates to MUX1.Under the RAM working method, realization be 4/1 interconnection, the signal frame head that enter into cross matrix this moment aligns, frame head Hd aligns with SFP signal rising edge as shown in Figure 8.So, the present invention carries out following handoff procedure: before carrying out switching, the control data that will switch to cross-connect matrix earlier writes standby RAM26, a switching permission position GEN who puts command register 24 simultaneously is 1, promptly switch and be under an embargo, change the content (Fig. 5 C) of switching controls register 23 this moment on request, and then put that switch to allow a position GEN be 0, promptly allow to switch, as shown in Figure 8, before carrying out switching point Hd, GEN has finished from forbidding switching → allowing the said process that switches, in conjunction with Fig. 9 as can be known, this moment d type flip flop 71 and be equipped with RAM and all performed to switch and prepare, so arrive when frame-synchronizing impulse one, its rising edge just triggers the Q end of d type flip flop and exports switch-over control signal SR, the conversion of control MUX1 and MUX2 switches to cross-connect matrix with those corresponding crossing control data CCSRa that write standby RAM26 that the switching controls register has been changed.Thereby realized no error code switching by the frame head position of SFP signal indication.
Claims (9)
1, a kind of synchronous digital sequence space division cross connection equipment is characterized in that: comprise that one contains the intersection kernel unit (11) of cross matrix (100～163) and the control unit (12) that intersects; Intersect and link to each other with holding wire between kernel unit (11) and the intersection control unit (12);
Described intersection control unit (12) comprises multiplexing control register (22), the standby random access memory (25,26) of advocating peace, switching controls register (23), first multicircuit switch (31), command register (24) and second multicircuit switch (32); Main random access memory (25), standby random access memory (26) and switching controls register (23) link to each other with first multicircuit switch (31); Multiplexing control register (22), command register (24) and first multicircuit switch (31) link to each other with second multicircuit switch (32).
2, synchronous digital sequence space division cross connection equipment as claimed in claim 1 is characterized in that: the kernel unit (11) of intersecting contains 64 cross matrixes (100～163).
3, synchronous digital sequence space division cross connection equipment as claimed in claim 1 is characterized in that: multiplexing control register (22) is six bit registers.
4, synchronous digital sequence space division cross connection equipment as claimed in claim 1 is characterized in that: command register (24) is an eight bit register.
5, as claim 1 or 3 described synchronous digital sequence space division cross connection equipments, it is characterized in that: also comprise the multiplexing control temporary register (21) that links to each other with multiplexing control register (22) by d type flip flop (27).
6, synchronous digital sequence space division cross connection equipment as claimed in claim 5 is characterized in that: d type flip flop (27), multiplexing control temporary register (21) and multiplexing control register (22) have 64 groups.
7, synchronous digital sequence space division cross connection equipment as claimed in claim 1 is characterized in that: main random access memory (25) and standby random access memory (26) have 16 groups.
8, synchronous digital sequence space division cross connection equipment as claimed in claim 7 is characterized in that: the switching controls register is 16 bit registers.
9, as claim 1,4 or 8 described synchronous digital sequence space division cross connection equipments, it is characterized in that: the control unit (12) that intersects also comprises a d type flip flop (71) that is connected on switching controls register (23) the output signal SR path, it is the control end of Q termination first multicircuit switch of described d type flip flop (71), and D, the CE of trigger (71), C end respectively with the switching controls position GEN of switching controls register (23), command register (24), and frame-synchronizing impulse input SFP links to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 98118987 CN1093727C (en) | 1998-09-22 | 1998-09-22 | synchronous digital sequence space division cross connection equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 98118987 CN1093727C (en) | 1998-09-22 | 1998-09-22 | synchronous digital sequence space division cross connection equipment |
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| CN1248878A true CN1248878A (en) | 2000-03-29 |
| CN1093727C CN1093727C (en) | 2002-10-30 |
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| CN 98118987 Expired - Fee Related CN1093727C (en) | 1998-09-22 | 1998-09-22 | synchronous digital sequence space division cross connection equipment |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005032205A1 (en) * | 2003-09-27 | 2005-04-07 | Huawei Technologies Co., Ltd. | A method and apparatus for realizing switching synchronously of clos cross connection matrix |
| CN1301599C (en) * | 2002-06-04 | 2007-02-21 | 中兴通讯股份有限公司 | Method for positioning up branch signal multi-frame and pointer |
| CN1317842C (en) * | 2003-07-17 | 2007-05-23 | 深圳市中兴通讯股份有限公司 | Super large-scale cross connection device and method used for synchronous digital transmission system |
| CN100440772C (en) * | 2004-03-19 | 2008-12-03 | 华为技术有限公司 | A method for implementing SDH low order time division full cross |
| CN1620186B (en) * | 2003-11-17 | 2010-09-22 | 阿尔卡特公司 | Method and apparatus for carrying out connection and related input/output processing functions |
| CN101014200B (en) * | 2007-01-29 | 2010-10-27 | 华为技术有限公司 | Switch method and switch apparatus for time division multiplexing signal |
| CN103138839A (en) * | 2013-02-22 | 2013-06-05 | 烽火通信科技股份有限公司 | Hardware implementation system compatible with multi-rate fiber channel services |
| CN101789840B (en) * | 2010-01-19 | 2013-06-05 | 华为技术有限公司 | Pan-T crossing device and pan-T crossing method |
| CN101453667B (en) * | 2000-12-29 | 2015-02-11 | 爱立信股份有限公司 | Digital cross-connect |
-
1998
- 1998-09-22 CN CN 98118987 patent/CN1093727C/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101453667B (en) * | 2000-12-29 | 2015-02-11 | 爱立信股份有限公司 | Digital cross-connect |
| CN1301599C (en) * | 2002-06-04 | 2007-02-21 | 中兴通讯股份有限公司 | Method for positioning up branch signal multi-frame and pointer |
| CN1317842C (en) * | 2003-07-17 | 2007-05-23 | 深圳市中兴通讯股份有限公司 | Super large-scale cross connection device and method used for synchronous digital transmission system |
| WO2005032205A1 (en) * | 2003-09-27 | 2005-04-07 | Huawei Technologies Co., Ltd. | A method and apparatus for realizing switching synchronously of clos cross connection matrix |
| CN100452886C (en) * | 2003-09-27 | 2009-01-14 | 华为技术有限公司 | Method and device of realizing synchronous switchover of CLDS crosslink matrix |
| CN1620186B (en) * | 2003-11-17 | 2010-09-22 | 阿尔卡特公司 | Method and apparatus for carrying out connection and related input/output processing functions |
| CN100440772C (en) * | 2004-03-19 | 2008-12-03 | 华为技术有限公司 | A method for implementing SDH low order time division full cross |
| CN101014200B (en) * | 2007-01-29 | 2010-10-27 | 华为技术有限公司 | Switch method and switch apparatus for time division multiplexing signal |
| CN101789840B (en) * | 2010-01-19 | 2013-06-05 | 华为技术有限公司 | Pan-T crossing device and pan-T crossing method |
| US8588255B2 (en) | 2010-01-19 | 2013-11-19 | Huawei Technologies Co., Ltd. | Full-T cross apparatus and method |
| CN103138839A (en) * | 2013-02-22 | 2013-06-05 | 烽火通信科技股份有限公司 | Hardware implementation system compatible with multi-rate fiber channel services |
| CN103138839B (en) * | 2013-02-22 | 2015-05-13 | 烽火通信科技股份有限公司 | Hardware implementation system compatible with multi-rate fiber channel services |
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| CN1093727C (en) | 2002-10-30 |
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