CN100433591C

CN100433591C - Bus delay correcting method for 40G SDH system

Info

Publication number: CN100433591C
Application number: CNB2004100802920A
Authority: CN
Inventors: 江柳; 胡晓君; 吕建新
Original assignee: Fiberhome Telecommunication Technologies Co Ltd
Current assignee: Fiberhome Telecommunication Technologies Co Ltd
Priority date: 2004-09-30
Filing date: 2004-09-30
Publication date: 2008-11-12
Anticipated expiration: 2024-09-30
Also published as: CN1588832A

Abstract

The present invention relates to a delayed self-adaptive correction method between high speed parallel bus groups in a 40GSDH system, particularly to a method applied to carrying out time delay and correction to signals of each group of SFI-4 interfaces in a chip of a framer of a 40G system. Due to the fact that the first-in first-out (FIFO) process of an SFI-4 signal buffer in an STM256 processing chip is controlled by the method, the present invention realizes that the maximum wiring difference of signal wires of a printed circuit board (PCB) between SFI-4 groups can reach more than 10 clock periods, and the requirement of the clock period of 0.1 in an SFI-4 interface specification is broken through. The limitation of PCB wiring is greatly lowered, and thereby, the design difficulty of PCB is lowered.

Description

The bus delay correcting method that is used for 40G SDH system

Technical field

The present invention relates to the self-adapting correction method of delaying time between the high speed parallel bus group in a kind of 40G SDH system, specifically be applied in the 40G system framer chip each group SFI-4 interface signal be carried out the method for delay correcting.

Background technology

In present High Speed System, normally parallel bus speed improves between chip and the chip by improving, the data throughout between backboard and the backboard.But the increase of bus number and transmission rate has also increased printed circuit board (PCB) (PCB) wiring difficulty and has produced the signal time delay problem.Specifically, owing to inevitably have time delay between each holding wire of parallel data/address bus, make signal eye diagram dwindle, clock signal owing to parallel bus independently transmits with respect to data-signal simultaneously, and clock signal itself may since time delay cause asynchronous with data, thereby reduced data-signal foundation and the maintenance nargin.The distortion of noise or clock signal has further aggravated this situation.Usually control by the strictness of PCB layout traditionally and suppress above-mentioned harmful effect.

High speed parallel bus standard commonly used in the SONET/SDH of 10G speed system is SFI-4.Data wire and a pair of clock cable that the parallel interface of every group of SFI-4 is 622Mb/s by 16 pairs of speed are formed, and are the transmission rate of 9953.28Mb/s so that total speed to be provided.For the interface of SFI-4, the maximum tolerance degree of its time delay was 0.1 clock cycle.

In present 40G (also being expressed as STM256) SDH used, because the restriction of chip technology, its physical circuit chip remained by realizing based on the high speed parallel bus of SFI-4 interface.In the demultiplexing process, earlier the 40G light signal is carried out opto-electronic conversion, form the parallel data of 64 road SFI-4 speed again by demultiplexing, handle then, as overhead extraction and professional the extraction.And in multiplex process, normally the parallel data of 64 road SFI-4 speed that transmit of receiving system is inserted by expense, forms the Frame of STM256 (40G) behind the service integration, then by going here and there and changing and form light signal, in optical communication net, transmit through electricity/light conversion.

At present, the common method that overcomes the shake of similar SFI-4 high-speed parallel data-interface is to realize by the length of arrangement wire that strict PCB goes up holding wire.This method is generally used in 10G (STM64) system realizes.But this method also is not suitable for the design of 40G (STM256) signal system, because, adopt this method, when design 10G (STM64) system, only need to guarantee 16 circuit-switched data lines length of arrangement wire unanimity on PCB in the SFI-4 interface.And, then must guarantee 64 circuit-switched data line PCB layout length unanimities in the STM256 system.Because chip height is intensive on the PCB of 40G system, can be very narrow for the space of adjusting holding wire length, for guaranteeing 64 road holding wire length unanimities, can only increase the PCB layout number of plies, but increase and wires design difficulty that this has brought pcb board thickness again make practical application become and hardly may.

Summary of the invention

The purpose of this invention is to provide the bus delay correcting method that is used for the 40G system, by designing the self-adapting correction method of delaying time between the high speed parallel bus group in a kind of 40G SDH system, correct the time-delay between the parallel data line group, thereby make 64 road SFI-4 signals in the inner phase place unanimity that realizes of the STM256 of 40G process chip, and reduce requirement thus, thereby make the realization of STM256 system become possibility to PCB layout.And the reduction owing to PCB layout is required makes the functional reliability of single circuit board be enhanced.

The know-why of at first explaining the present invention and being utilized.Signal processing for multiplexing direction is, in the STM256 process chip, 64 road STM4 signals are divided into 16 the tunnel one groups, and it is one road STM64 signal that 16 road STM4 signals in every group at first are multiplexed into, then multiplexing once more one road STM256 signal that becomes of 4 road STM64 signals.Above-mentioned STM4 signal is when entering the STM256 process chip, the data of every road STM4 signal at first are buffered in separately the buffer, the buffer of 16 road signals is unified control data cache-time in buffer by CPU on the same group, and this cache-time calculated with the buffer clock cycle.Data by 16 road buffers output on the same group are multiplexed into the Frame into STM64, and the header signal time of this Frame is depended on the output time of 16 road buffers on the same group.Like this, can just adjust the buffer memory degree of depth of buffer on the same group, just can control the header signal time of STM64 frame by regulating the metadata cache time of 16 road buffers on the same group.Four road STM64 Frame header signals alignment back quilt is multiplexing formation STM256 Frame once more, sends the optical-electrical converter circuit to through 4 groups of SFI-4 interfaces then.Specific implementation is: by the control of the microprocessor execution that is connected with the STM256 process chip by the control bus interface to the process chip internal buffer buffer memory degree of depth, carry out the monitoring of each being organized STM64 Frame header signal by field programmable gate array (FPGA), described FPGA is drawn and offered to STM256 process chip STM64 Frame header signal separately, produce the delay difference index signal of each group according to each framing head signal by FPGA, when each organizes the phase mutually synchronization, each organizes the delay difference index signal is 1, if exist a certain group asynchronous, then this group delay difference index signal is 0.CPU carries out relevant Control Software, is 0 o'clock in the delay difference index signal of finding a certain group, adjusts the buffer memory degree of depth of this group, till this group synchronously.

Signal processing for the demultiplexing direction is: from one road STM256 data-signal of optical-electrical converter part, at first be sent to the STM256 process chip through 4 groups of SFI-4 interfaces, in these processor chips, must at first align between the data-signal of every group of SFI-4 interface, the STM256 Frame be can be merged into then, expense and data extract carried out.If respectively organize not alignment between the signal, then can't extract any one group frame head index signal.The present invention utilizes and whether can extract first group of frame head index signal in the STM64 signal in the demultiplexing process and respectively organize the sign whether demultiplexed signal aligns as judging.Still carry out to extract in first group of STM64 signal the frame head index signal to produce the function of delay difference index signal by the FPGA circuit.

The related circuit of whole delay correcting method comprises STM256 frame process chip, FPGA, CPU and related peripheral circuit, and each chip all comprises separately initialization and Control Software.

Delay correcting method specifically comprises the steps: between 40G SDH system high-speed parallel bus group of the present invention

In multiplexing direction:

64 road STM4 signals are divided into 4 groups, and every group is 16 road STM4 signals;

By the STM256 process chip every group 16 road STM4 signal multiplexing formed a STM64 Frame;

By the STM256 process chip header signal of 4 STM64 Frames is exported to multiplexing direction delay difference indicating circuit, and indicate as a reference, produce the delay difference index signal that all the other respectively organize Frame with the frame head of first group of STM64 signal;

CPU detects delay difference index signal of each group, when finding a certain group synchronously the time, and the buffer memory degree of depth that the CPU regulating and controlling should the group buffer, until this group synchronously;

In the demultiplexing direction:

Extract the header signal of first group of STM64 signal,, be judged as then that respectively to organize signal synchronous if can extract;

If fail to extract the header signal of first group of STM64 signal, then be judged as respectively to organize and fail between the signal synchronously, then CPU controls all the other buffers of respectively organizing signal and adjusts the buffer memory degree of depth, till the header signal that extracts first group of STM64 signal.

In said method of the present invention, in multiplexing direction, utilize the overhead extraction clock generating of the frame head index signal respectively organize Frame and first group of Frame respectively to organize the delay difference index signal of Frame, if do not have delay difference between a certain group and first group, then the delay difference index signal of this group is 1, if have delay difference between a certain group and first group, the corresponding delay difference index signal of this group is 0, and CPU is with the foundation of this delay difference index signal as this group buffer buffer memory degree of depth of adjustment.

In said method of the present invention, in multiplexing direction, CPU is that buffer memory depth minus 1 or buffer memory depth minus 2 or the buffer memory degree of depth add 1, just can finish for maximum 9 times the adjustment of delay difference between the group of multiplexing direction to the buffer memory depth adjustment mode of each group buffer.

In said method of the present invention,, as the delay difference index signal,, then adjust the buffer memory degree of depth of its excess-three group if there is delay difference with the frame head index signal that whether can extract first group of STM64 signal in the demultiplexing direction.

In said method of the present invention, in the demultiplexing direction, the buffer memory depth adjustment mode of every group of buffer is to regulate the buffer memory degree of depth between ± 2, like this buffer memory degree of depth of its excess-three group buffer can add 2 for being adjusted to, add 1, constant, subtract 1, subtract 2 totally five kinds of states, regulate maximum 125 times of three groups of buffers, just can realize that the demultiplexing direction respectively organizes data-frame sync.

The outstanding advantage of the self-adapting correction method of delaying time between the high speed parallel bus group in the 40G SDH system is, owing to pass through to SFI-4 signal buffer first-in first-out (FIFO) process control in the STM256 process chip, realize that the PCB layout difference between the SFI-4 group can reach 10 more than the clock cycle, broken through the requirement of 0.1 clock cycle in the SFI-4 interface specification, greatly reduce the restriction of PCB layout, thereby reduced the PCB design difficulty.Make the pcb board of 40G (STM256) signal almost can design with reference to the design specification of the PCB version of 10G (STM64) signal.And because this technology of employing, the system that makes reduces the susceptibility of phase difference between the SFI-4 group, has improved the reliability of system greatly.

Another outstanding advantage of the self-adapting correction method of delaying time between the high speed parallel bus group in the 40G SDH system is its adaptivity.Since the discovery of the delay variation between group between high speed signal with and adjust and can finish by microprocessor fully, realize the complete adaptivity of correction of time-delay between the SFI-4 group, do not need manual intervention, greatly reduce the difficulty of producing debugging, strengthened its availability.

Description of drawings

Fig. 1 is the realization circuit block diagram of time-delayed adaptive correcting method between 40G SDH system high speed parallel bus group;

Fig. 2 is the flow chart of the self-adapting correction of delaying time between the SFI-4 interface group of multiplexing (MUX) direction;

Fig. 3 is the digital circuit realization block diagram that multiplexing (MUX) direction produces delay difference index signal between the SFI-4 interface group;

Fig. 4 be the self-adapting correction of delaying time between the SFI-4 interface group of demultiplexing (DEMUX) direction flow chart.

Embodiment

The present invention utilizes the multiplexing rule of SDH, and 64 pairs of SFI-4 buses are divided into 4 groups, and 16 pairs every group, promptly every group is equivalent to a 10G SDH signal.Utilize frame alligning information in every group of SFI-4 interface signal to come delay variation between 4 groups of SFI-4 data/address buss of indirect detection then, read this difference by microprocessor by microcomputer interface then, self adaptation is adjusted in the STM256 process chip degree of depth control to the FIFO of the reception buffer of every group of SFI-4 signal, to reduce this phase difference, till not having difference between 4 framing framing signals.Between multiplexing direction is to each group, whether exist the judgment mode of phase difference specifically to be, judge the frame head indication by judging in the expense index signal that extracts in every group of SFI-4 high-speed data from the low hopping edge that uprises, time order and function by frame head indication between comparative group judges whether phase difference between the existence group, if this species diversity is an overhead processing in the clock cycle, be judged as not time-delay between group, otherwise for time delay between group is arranged.When there is phase difference in method of the present invention between each group, realize that by the microprocessor that the STM256 process chip is outer every group of SFI-4 data of adaptive adjustment enter the FIFO degree of depth of STM256 process chip, and then make the frame head alignment before carrying out the STM256 signal processing of 4 groups of SFI-4 signals.The adjustment process that CPU carries out is, if CPU finds the delay difference index signal of FPGA generation and for there being delay difference, then adjusts the FIFO degree of depth of buffer in the STM256 process chip, and then has or not time delay indication between group among the judgement FPGA, if any, then continue to adjust the FIFO degree of depth.

Elaborate embodiments of the present invention below in conjunction with accompanying drawing.Fig. 1 is the realization circuit block diagram of the self-adapting correction method of delaying time between 40G SDH system high speed parallel bus group.No matter be multiplexing direction (MUX) or demultiplexing direction (DEMUX), every group of SFI-4 will extract its frame alignment signal by STM256 frame process chip, and give that the time delay detection circuit produces time delay index signal between group between group among the FPGA.This signal will be indicated between the SFI-4 group to have big phase difference indirectly as feedback signal, thereby instructs CPU to adjust the FIFO time-delay of 4 groups of SFI-4 parallel data lines in chip, realizes that high-speed data goes to tremble between adaptive SFI-4 group.

Different at multiplexing direction (MUX) and demultiplexing direction (DEMUX), below set forth the implementation procedure of all directions technical scheme separately.Fig. 2 is the flow chart of the self-adapting correction of delaying time between the SFI-4 interface group of multiplexing (MUX) direction.In the signal multiplexing direction, locate the frame head index signal of each group SFI-4 signal as phase difference between multiplexing direction test set and the MUX FPGA that produces the delay difference index signal.In practical operation, with the frame head index signal of first group of SFI-4 signal as a reference, relatively other respectively organizes the frame head index signal of SFI-4 and its difference respectively then.If variant, then adjust the buffer FIFO degree of depth that delay difference group SFI-4 interface should be arranged mutually, up to eliminating corresponding difference.In enforcement of the present invention, we limit the adjustment of the FIFO degree of depth and select there are 3 kinds, for subtracting 1, subtract 2 and add 1.Because in multiplexing direction, 4 groups of SFI-4 of input are independent mutually, and the FIFO degree of depth adjustment of one group of SFI-4 is not influenced other group, thus at most (3+3+3)=9 time adjust SFI-4 that action just can realize multiplexing direction organize between high-speed data go to tremble.

Fig. 3 is that the digital circuit of phase difference indication realized block diagram between the SFI-4 of multiplexing (MUX) direction organized, and this circuit is specifically realized by the FPGA circuit.Among Fig. 3, be labeled as the frame head index signal of 4 groups of SFI-4 interfaces of SFI_FR1 to SFI_FR4, it jumps to high level indication SDH frame head from low level.SFI_SOH_CLK is the overhead extraction clock of first group of SFI-4 interface.4 framing index signals jump to high level from low level at first will trigger this circuit, and phase difference signal is at this moment exported by REG0 to REG4 port.If 4 groups of SFI-4 interface differences are less than a clock cycle, then REG0 to REG4 is 1, if wherein some group exists delay difference, then the corresponding REG port of this group is output as 0.

Fig. 4 be the self-adapting correction of delaying time between the self adaptation SFI-4 interface group of demultiplexing (DEMUX) direction flow chart.In the demultiplexing direction,, be correlated with between these 4 groups of SFI-4 are mutual though give STM256 frame process chip after demultiplexing into 4 groups of SFI-4.When having only time delay between these 4 groups of SFI-4 interfaces to adjust to unanimity, just can obtain normal frame head index signal.Therefore, the present invention adopts the frame head index signal of first group of SFI-4 to indicate as difference.If the frame head index signal of first group of SFI-4 does not jump to the cycle variation of high level from low level, to represent to have phase difference between 4 groups of SFI-4 interfaces, this delay difference signal makes CPU control the FIFO degree of depth of SFI-4 interface.The variation of the FIFO degree of depth at N between-the N.Because the FIFO degree of depth adjustment of every group of SFI-4 interface all can have influence on the location of frame head, so with first group be under the base case, the possible state of every group of adjustment is N in its excess-three group, N-1,1,0 ,-1,-N+1 ,-N is 2N+1 kind state altogether, and it is (2N+1) that three groups of maximum altogether FIFO adjust number of times ³The numerical value of N gets 2 generally speaking, and such three groups of buffers are adjusted maximum 125 times of the FIFO degree of depth, just can realize that 4 groups of high-speed datas between the SFI-4 interface go to tremble.

Above-mentioned specific embodiment of the present invention does not constitute qualification to protection range of the present invention just to further specifying the present invention.Protection range of the present invention is limited by appended claims.

Claims

1. one kind is used for delay correcting method between 40G SDH system high-speed parallel bus group, and this method comprises the steps:

In multiplexing direction:

By the STM256 process chip header signal of 4 STM64 Frames is exported to multiplexing direction delay difference indicating circuit, and as a reference with the indication of the frame head of first group of STM64 signal, produce the delay difference index signal that all the other respectively organize Frame, particularly, utilize the overhead extraction clock generating of the frame head index signal respectively organize Frame and first group of Frame respectively to organize the delay difference index signal of Frame, if do not have delay difference between a certain group and first group, then the delay difference index signal of this group is 1, if have delay difference between a certain group and first group, the corresponding delay difference index signal of this group is 0, and CPU is with the foundation of this delay difference index signal as this group buffer buffer memory degree of depth of adjustment;

In the demultiplexing direction:

2. method according to claim 1, it is characterized in that: in multiplexing direction, CPU is that buffer memory depth minus 1 or buffer memory depth minus 2 or the buffer memory degree of depth add 1, just can finish for maximum 9 times the adjustment of delay difference between the group of multiplexing direction to the buffer memory depth adjustment mode of each group buffer.

3. method according to claim 1 is characterized in that: in the demultiplexing direction, as the delay difference index signal, if there is delay difference, then adjust the buffer memory degree of depth of its excess-three group with the frame head index signal that whether can extract first group of STM64 signal.

4. method according to claim 3, it is characterized in that: in the demultiplexing direction, the buffer memory depth adjustment mode of every group of buffer is to regulate the buffer memory degree of depth between ± 2, like this buffer memory degree of depth of its excess-three group buffer can add 2 for being adjusted to, add 1, constant, subtract 1, subtract 2 totally five kinds of states, regulate maximum 125 times of three groups of buffers, just can realize that the demultiplexing direction respectively organizes data-frame sync.