CN1909429B - Device for delaying phototiming digital transmission net channel payload data - Google Patents
Device for delaying phototiming digital transmission net channel payload data Download PDFInfo
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- CN1909429B CN1909429B CN2005100886615A CN200510088661A CN1909429B CN 1909429 B CN1909429 B CN 1909429B CN 2005100886615 A CN2005100886615 A CN 2005100886615A CN 200510088661 A CN200510088661 A CN 200510088661A CN 1909429 B CN1909429 B CN 1909429B
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Abstract
The invention relates to a method for delaying the load data of light synchronous digit transmission network channel, wherein it comprises: a channel de-multiplex module; a channel storage module with synchronous FIFO module, write point control module and read point control module, while the channel storage module is used to store and read the channel load and load instruct of delay channel based on the delay distribution information; a channel multiplex module for multiplexing the non-delay part and the delay channel, based on SDH frame structure multiplex projection theory, to generate new STM-1, STM-4, STM-16, or STM-64 frame of delay channel. The invention supplies needed channel delay data for designing transmission device, to improve the design property of transmission device.
Description
Technical field
The present invention relates to the device of a kind of delay Optical synchronization digital transmission network (SDH) passage payload data, relate in particular to the technology that the Virtual Concatenation compensation of delay is handled and communication channel delay is handled in a kind of communication field SDH transmission system.
Background technology
The time-delay of prior art is meant the time-delay of digital data transmission, and just signal is transferred to a place from a place always needs certain hour.Causing that time-delay mainly contains the reason of three aspects, mainly comprising time-delay that transmission system causes, time-delay that network digital equipment causes and the time-delay that causes such as the introducing of SDH equipment.Because the time-delay of photosignal in medium is propagated all can be relevant with the refractive index of transmission medium, the existence of medium refractive index all can make transmission signals produce certain time-delay, and this time-delay is exactly the time-delay that transmission system causes.When apparatus for network node was introduced in the transmission system, equipment such as the buffer that the network equipment may have, TSIU time slot interchange unit all can produce signal lag.Some special transmission equipments are introduced transmission network, may reduce time-delay, also may increase time-delay, in the SDH system, adopt the pointer adjustment technology to carry out phase alignment and frequency correction, the total time-delay of equipment is reduced, but pointer is handled, fixedly fill in processing, shine upon and is gone to shine upon the time-delay that processing etc. all can increase whole system.
Time-delay has different influences to different business, and for speech business, it is excessive to delay time, and can cause speech intelligibility to reduce and generation voice latency phenomenon; For data service, then can cause the reduction of efficiency of transmission.The SDH system can carry voice traffic and data service, so the existence of time-delay all can produce certain influence to the business of SDH transmission system.When voice-bearer and data service, passage payloads such as the AU4 of SDH system, AU3, TU3, TU2, TU12 or TU11 are in the mapping processing and go to shine upon the time-delay that may produce in the processing procedure in various degree, and this can reduce the performance of transmission equipment.
In the SDH transmission system, the general method that adopts of transmission for the business information of passages such as capacity overgauge AU4, AU3, FU3, FU2, IU12 or TU11 is a Virtual Concatenation, Virtual Concatenation is by a plurality of virtual container set altogether, make these virtual containers can be used as a bigger or suitable virtual container of Capacity Ratio and use, utilize Virtual Concatenation technology transmitting data service and effectively utilize bandwidth preferably through combination.Because constituting the transmission path of the passage process of virtual cascade group may be different, cause different passages may have different time-delays, in addition, the data that the sequencing of the increase and decrease of the passage of formation virtual cascade group causes sending are not necessarily carried out according to the channel slot number order, but in transmission system, data transmit according to the channel slot sequence arrangement, the then necessary corresponding adjustment virtual cascade group channel slot order of Virtual Concatenation process chip and equipment, according to original rule alignment, the alignment preface of laying equal stress on, thereby the influence of avoiding delaying time and bringing.
Because time-delay to the influence of transmission equipment, must be considered the influence that different delayed time is caused the respective chip function when therefore exploitation has the SDH transmission chip that shines upon functions such as conciliating mapping, Virtual Concatenation.Conciliate in mapping, the Virtual Concatenation relevant device design process in the SDH mapping, then need to produce the time-delay generation device of the various time-delays of different passage payloads, so that the designer can utilize this time-delay mechanism to change design with corrective at any time, mapping is conciliate in the mapping that makes equipment under the different delayed time condition, the Virtual Concatenation function all is normal so that satisfy, and improves the design performance of equipment.
It is open also to find no the technology contents that closes the transmission delay generation device in the prior art.
Summary of the invention
The object of the present invention is to provide a kind of device of delaying phototiming digital transmission net channel payload data, it is a kind of delay passage payload data device that provides for the chip design of SDH transmission system, the time-delay that produces various different passages can be provided, produce the different delayed time of the passage payloads such as AU4, AU3, TU3, TU2, TU12 and TU11 of STM-1, STM-4, STM-16 and STM-64, utilize this method can revise the design of transmission equipment, improve the device design performance at aspects such as Virtual Concatenation and mapping functions.
Technical scheme of the present invention comprises:
A kind of device of delaying phototiming digital transmission net channel payload data, wherein, described device comprises:
One passage demultiplexing module, comprise the data time delay module that is linked in sequence successively, Higher Order Path Overhead byte locating module and time-delay passage payload extraction module, described passage demultiplexing module is used to extract the payload of time-delay passage of STM-1, STM-4, STM-16 or STM-64 and the payload indication of payload indication and time-delay part;
One passage memory module comprises synchronous FIFO module, write pointer control module and read pointer control module, and described passage memory module is used for storing and reading according to the time-delay configuration information passage payload and the payload indication of described time-delay passage;
One channel multiplexing module, being used for described not time-delay part carries out multiplexing with the time-delay passage according to the multiplexing mapping principle of SDH frame structure, generation has new STM-1, STM-4, STM-16 or the STM-64 frame of a time-delay passage, the payload of the payload of time-delay passage wherein for reading from described synchronous FIFO module, the payload of described time-delay passage are designated as the payload indication of reading from described synchronous FIFO module.
Described device, wherein, described data time delay module is used to locate the indication of Higher Order Path Overhead byte and satisfies the sequential requirement, with multiplexing indication time-delay triple time of described payload, payload indication and frame head.
Described device, wherein, described Higher Order Path Overhead byte locating module is used for orienting the indication of Higher Order Path Overhead byte according to indication of the payload after time-delay triple time and the multiplexing indication of frame head.
Described device, wherein, described time-delay passage payload extraction module utilizes described Higher Order Path Overhead byte indication, time-delay configuration information and the multiplexing mapping principle of SDH frame structure, obtain the delay time payload and the payload indication of passage, and the payload and the payload indication of delaying time and partly comprising expense pointer, the section overhead of the passage of delaying time and the passage of not delaying time.
Described device, wherein, described synchronous FIFO module is used for storing and reading according to the time-delay configuration information passage payload and the payload indication of described time-delay passage, and selects the parameter of described synchronous FIFO module according to the time-delay configuration information.
Described device, wherein, described write pointer control module is represented delay time with the time-delay byte number, the unit of time-delay byte is byte, various passage bytes of payload sum, single frames total amount of byte and multi-frame total amount of byte; The payload and the payload indication of described time-delay passage are written in the synchronous FIFO module of first in first out the payload of the part of will not delaying time simultaneously and payload indication time-delay two bats; When the payload of time-delay passage is indicated when effective, write the payload and the payload indication of time-delay passage to described synchronous FIFO module, and write and do not stop.
Described device, wherein, when described read pointer control module is used for write address when described synchronous FIFO module and equals to delay time the time-delay byte of passage, the payload and the payload indication of reading the time-delay passage from described synchronous FIFO module.
Described device, wherein, the pass of described time-delay byte number and described time-delay is: time delays 125 microseconds 2430 bytes that just equal to delay time.
The device of a kind of delaying phototiming digital transmission net channel payload data provided by the present invention, compared with prior art, for transmission equipment design provides required communication channel delay data, thereby the performance according to the treatment channel delay data is constantly adjusted device design, has improved the design performance of transmission equipment in function aspects such as treatment channel time-delay and Virtual Concatenation compensation of delay.
Description of drawings
Fig. 1 is the realization schematic diagram of the device of a kind of delaying phototiming digital transmission net channel payload data of the present invention;
Fig. 2 is the passage demultiplexing schematic diagram of apparatus of the present invention;
Fig. 3 is the passage storage principle figure of apparatus of the present invention.
Embodiment
Below in conjunction with accompanying drawing, will carry out comparatively detailed explanation to each preferred embodiment of the present invention.
The device of delaying phototiming digital transmission net channel payload data of the present invention, its core concept is: after STM-1, STM-4, STM-16 and STM-64 etc. are carried out the passage demultiplexing, store into and carry out the passage storage in the fifo fifo isolating the indication of the payload of the passage of will delaying time and payload, when the write address of FIFO equals to delay time byte when being delay time, from FIFO, read the payload of time-delay passage
With the payload indication, carry out channel multiplexing with other passages of not delaying time then and form new STM-1, STM-4, STM-16 and STM-64 etc.
The device of a kind of delaying phototiming digital transmission net channel payload data of the present invention, it realizes schematic diagram as shown in Figure 1, its composition comprises:
One, passage demultiplexing module; It realizes schematic diagram as shown in Figure 2, comprise data time delay module, Higher Order Path Overhead byte J1 locating module and time-delay passage payload extraction module, described passage demultiplexing module mainly can be the payload of the time-delay passage that extracts STM-1, STM-4, STM-16 and STM-64 etc. and the payload indication of payload indication and time-delay part.And wherein,
Described data time delay module is in order to locate the J1 indication and to satisfy the sequential requirement, with payload ID, payload indication IPL and the multiplexing indication of the frame head IC1J1 time-delay triple time of STM-1.
Payload indication IPL and the multiplexing indication of frame head IC1J1 after described J1 locating module is clapped according to time-delay one orient the j1 byte indication.
Described time-delay passage payload extraction module utilizes J1 indication, time-delay configuration information and the multiplexing mapping principle of SDH frame structure, obtain the delay time payload and the payload indication of passage, and the payload and the payload indication of delaying time and partly comprising expense pointer, the section overhead of the passage of delaying time and the passage of not delaying time.
Two, passage memory module, it realizes schematic diagram as shown in Figure 3, comprises synchronous FIFO module, write pointer control module and read pointer control module.Passage memory module major function is the passage payload and the payload indication of storing and reading the passage of will delaying time according to the time-delay configuration information.
Passage payload and payload indication that the passage of will delaying time was stored and read to described synchronous FIFO module according to the time-delay configuration information, the parameter of FIFO is selected according to the time-delay configuration information.
Described write pointer control module is represented delay time with the time-delay byte number, and physical relationship is, 125 microseconds of delaying time, and 2430 bytes just equal to have delayed time; Timer is byte, various passage bytes of payload sum, single frames total amount of byte and multi-frame total amount of byte etc.; The payload and the payload indication of the passage of will delaying time are written in the synchronization fifo of first in first out the payload of the part of will not delaying time simultaneously and payload indication time-delay two bats; When the payload of time-delay passage is indicated when effective, FIFO begins to write the payload and the payload indication of time-delay passage, and FIFO does not write and can stop.
When described read pointer control module equaled to delay time the time-delay byte of passage when the write address of FIFO, FIFO began to read the payload and the payload indication of time-delay passage.
Three, channel multiplexing module; Not time-delay part and time-delay passage carry out multiplexing according to the multiplexing mapping principle of SDH frame structure, generation has the frames such as new STM-1, STM-4, STM-16 and STM-64 of a time-delay passage, in frames such as new STM-1, STM-4, STM-16 and STM-64, the payload of payload for reading from FIFO of time-delay passage, the payload of time-delay passage are designated as the payload indication of reading from FIFO.
The technical scheme of the invention described above all is applicable to the generation of time-delay passage of the passages such as TU11, TU12, TU2, TU3, AU3 and AU4 of STM-1 frame and STM-4, STM-16 and STM-64 etc.
Apparatus of the present invention have realized the time-delay to the various different times of AU4, AU3, TU3, TU2, TU12 or the TU11 passage payload of frames such as the STM-1 of SDH system, STM-4, STM-16 or STM-64, make and in the transmission equipment design, can utilize this device to produce various communication channel delay, constantly improve and revise the specific design of transmission equipment, thereby improved the design performance of functions such as transmission equipment mapping and Virtual Concatenation processing.
But should be understood that the above-mentioned description at specific embodiment of the present invention is comparatively concrete, can not therefore be interpreted as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (8)
1. the device of a delaying phototiming digital transmission net channel payload data is characterized in that, described device comprises:
One passage demultiplexing module, comprise the data time delay module that is linked in sequence successively, Higher Order Path Overhead byte locating module and time-delay passage payload extraction module, described passage demultiplexing module is used to extract the payload of time-delay passage of STM-1, STM-4, STM-16 or STM-64 and the payload indication of payload indication and time-delay part;
One passage memory module comprises synchronous FIFO module, write pointer control module and read pointer control module, and described passage memory module is used for storing and reading according to the time-delay configuration information passage payload and the payload indication of described time-delay passage;
One channel multiplexing module, being used for described not time-delay part carries out multiplexing with the time-delay passage according to the multiplexing mapping principle of SDH frame structure, generation has new STM-1, STM-4, STM-16 or the STM-64 frame of a time-delay passage, the payload of the payload of time-delay passage wherein for reading from described synchronous FIFO module, the payload of described time-delay passage are designated as the payload indication of reading from described synchronous FIFO module.
2. device according to claim 1 is characterized in that, described data time delay module is used to locate the indication of Higher Order Path Overhead byte and satisfies the sequential requirement, with multiplexing indication time-delay triple time of described payload, payload indication and frame head.
3. device according to claim 2 is characterized in that, described Higher Order Path Overhead byte locating module is used for orienting the indication of Higher Order Path Overhead byte according to indication of the payload after time-delay triple time and the multiplexing indication of frame head.
4. device according to claim 3, it is characterized in that, described time-delay passage payload extraction module utilizes described Higher Order Path Overhead byte indication, time-delay configuration information and the multiplexing mapping principle of SDH frame structure, obtain the delay time payload and the payload indication of passage, and the payload and the payload indication of delaying time and partly comprising expense pointer, the section overhead of the passage of delaying time and the passage of not delaying time.
5. device according to claim 1, it is characterized in that, described synchronous FIFO module is used for storing and reading according to the time-delay configuration information passage payload and the payload indication of described time-delay passage, and selects the parameter of described synchronous FIFO module according to the time-delay configuration information.
6. device according to claim 5 is characterized in that, described write pointer control module is represented delay time with the time-delay byte number, and the unit of time-delay byte is byte, various passage bytes of payload sum, single frames total amount of byte and multi-frame total amount of byte; The payload and the payload indication of described time-delay passage are written in the synchronous FIFO module of first in first out the payload of the part of will not delaying time simultaneously and payload indication time-delay two bats; When the payload of time-delay passage is indicated when effective, write the payload and the payload indication of time-delay passage to described synchronous FIFO module, and write and do not stop.
7. device according to claim 6 is characterized in that, when described read pointer control module is used for write address when described synchronous FIFO module and equals to delay time the time-delay byte of passage, and the payload and the payload indication of reading the time-delay passage from described synchronous FIFO module.
8. device according to claim 6 is characterized in that, the pass of described time-delay byte number and described time-delay is: time delays 125 microseconds 2430 bytes that just equal to delay time.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2005100886615A CN1909429B (en) | 2005-08-01 | 2005-08-01 | Device for delaying phototiming digital transmission net channel payload data |
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| CN2005100886615A CN1909429B (en) | 2005-08-01 | 2005-08-01 | Device for delaying phototiming digital transmission net channel payload data |
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| CN1909429A CN1909429A (en) | 2007-02-07 |
| CN1909429B true CN1909429B (en) | 2010-06-23 |
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| CN1909430B (en) * | 2005-08-01 | 2010-12-29 | 中兴通讯股份有限公司 | Method for delaying phototiming digital transmission net channel payload data |
| CN102098589A (en) * | 2009-12-14 | 2011-06-15 | 中兴通讯股份有限公司 | Multiplexing method and device for optical channel data units |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1453964A (en) * | 2002-04-24 | 2003-11-05 | Eci电信公司 | Processing of business quantity in synchro communication network |
| CN1619327A (en) * | 2003-11-18 | 2005-05-25 | 华为技术有限公司 | System of virtual cascade time delay alignment characteristic used for testing chip and its method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1453964A (en) * | 2002-04-24 | 2003-11-05 | Eci电信公司 | Processing of business quantity in synchro communication network |
| CN1619327A (en) * | 2003-11-18 | 2005-05-25 | 华为技术有限公司 | System of virtual cascade time delay alignment characteristic used for testing chip and its method |
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| CN1909429A (en) | 2007-02-07 |
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Application publication date: 20070207 Assignee: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Assignor: ZTE Corporation Contract record no.: 2015440020319 Denomination of invention: Device for delaying phototiming digital transmission net channel payload data Granted publication date: 20100623 License type: Common License Record date: 20151123 |
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Granted publication date: 20100623 Termination date: 20190801 |