CN105812062B - Optical transfer network MLD method for interface adaptation and system - Google Patents
Optical transfer network MLD method for interface adaptation and system Download PDFInfo
- Publication number
- CN105812062B CN105812062B CN201610124011.XA CN201610124011A CN105812062B CN 105812062 B CN105812062 B CN 105812062B CN 201610124011 A CN201610124011 A CN 201610124011A CN 105812062 B CN105812062 B CN 105812062B
- Authority
- CN
- China
- Prior art keywords
- channel
- state
- logical channel
- data
- fifo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
- H04B10/2589—Bidirectional transmission
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
The invention discloses a kind of optical transfer network MLD method for interface adaptation and system, which includes bit_demux module, and physical channel bit is demultiplexed into logical channel；Ll_align module, the detection for completing the frame alignment byte of logical channel obtains FP, and exports the channel data after framing and alarm indication signal, and framing is completed by the framing state machine of standard；Llm_recovery module, completes the recovery and sequence of logical channel number (LCN), and recovery process is restored state machine by standard and carried out；Deskew_pro module is made of deskew_ctrl submodule and correction FIFO submodule, and the delay registration process of logical channel is completed according to FP；Ll_mux module completes the data frame recombination in logical channel after alignment of data.The present invention solves the problems, such as the multi-channel data delay deviation occurred in the transmission of 100G MLD interface according to the FP and logical channel number (LCN) for extracting and recovering, the read operation of control channel correction FIFO.
Description
Technical field
The present invention relates to technical field of optical network communication, and in particular to optical transfer network MLD method for interface adaptation and system.
Background technique
As the implementation of " broadband China light net city " plan and mobile Internet, Internet of Things and cloud computing etc. are new
The strength of type bandwidth applications drives, and there is an urgent need to transmit network with higher capacity.Cloud service, household broadband and wireless backhaul
The explosive growth of brought packet stream amount pushing a new round for operator to invest, and supports 100G with dilatation optical transport network
Network transmission.
Multichannel distribution (MLD) is the core mechanism that 100G technology is realized, MLD is based on inverse multiplexing technology, by high speed
Signal is distributed into several low speed signals in transmitting terminal and carries out multi-channel parallel transmission, and each channel has the school of itself
Fiducial mark is known.The distribution that multichannel is carried out to high-speed data-flow, reduces the rate in each channel, to reduce interface-clock-frequency
Requirement and implementation complexity.
Fig. 1 is 100G OTU4 frame MLD mode；It is divided into as shown in Figure 1,100G OTU4 frame data are based on 16 byte modes
1020 groups, then in loop distribution to 20 logical channels (logical lanes, LL).Every OTU4 frame boundaries, channel point
With being rotated；Distribution for OTU4 to 20 logical channel, the 3rd OA2 byte on OTU4 frame are defined as logical channel
It marks (LLM), LLM value is successively incremented by from 0 to 239 with continuous OTU4 frame adds 1；Logical channel number (LCN) is by 20 (LLM of LLM modulus
Mod 20) operation obtains.
Currently, 100G OTN is directed to different physical channel quantity, bit multiplexing is carried out to logical channel.20 tunnel logics are logical
Road passes through 2:1 bit multiplexer is multiplexed into 10 tunnel physical channels (OTL4.10), or passes through 5:1 bit multiplexer is multiplexed into 4 road objects
It manages channel (OTL4.4), 100G OTN Transmission system constitutes two kinds of multichannel physics optical interfaces of 4 × 28G and 10 × 11G, in photosphere
Using wave division multiplex mode, multiple physical light paths are transmitted in an optical fiber, the rate of single optical channel is reduced from 100G
To 28G and 11G, customer side optical interface is substantially increased to the tolerance of chromatic dispersion and polarization mode dispersion (PMD), this variation is
Network application provides more flexibilities, and reduces network cost.But bring following problems：
MLD processing mode also brings multi-channel data delay correction while reducing high-speed data processing difficulty
Problem.Each physical channel parallel data is after different wavelength and line transmission process, between channel inevitably
Appearance misplaces and is delayed, and leads between logical channel that there are delay deviations, and initial data can not be reverted in data receiver.
In view of this, being badly in need of providing a kind of elimination interchannel delay inequality, realizes multi-channel data alignment, realize channel data
Recombination reverts to the system and method for initial data.
Summary of the invention
The technical problem to be solved by the present invention is to data during different wavelength and line transmission, exist dislocation and
Delay leads to the problem of can not reverting to initial data in data receiver there are delay deviation between logical channel.
In order to solve the above-mentioned technical problem, it is connect the technical scheme adopted by the invention is that providing a kind of optical transfer network MLD
Mouth adaption system, including：
Bit_demux module：For physical channel bit to be demultiplexed into logical channel；
Ll_align module：For completing the detection of the frame alignment byte of logical channel, FP mark is obtained, and export framing
Channel data and alarm indication signal afterwards, framing are completed by the framing state machine of standard；
Llm_recovery module：For completing the recovery and sequence of logical channel number (LCN), and recovery process is restored by standard
State machine carries out；
Deskew_pro module：For identifying the delay registration process for completing logical channel according to the FP, by deskew_
Ctrl submodule and FIFO submodule composition, wherein FIFO submodule complete logical channel delay correction adjustment and depth by most
Big correction parameter determines, and the read-write operation of deskew_ctrl submodule error correct fifo module；
Ll_mux module:For completing the recombination of the data frame in logical channel after alignment of data.
In the above scheme, the bit polling mode includes but is not limited to：
For OTL4.10 data-interface, every 2 bits by 1 physical channel data distribution to 2 logical channels, logic
The rate in channel is the half of original physical channel；
For OTL4.4 data-interface, every 5 bits by 1 physical channel data distribution to 5 logical channels, logic is logical
The rate in road is 1/5th of original physical channel；
After the completion of bit demultiplexing, raw 20 logical channels of common property, each logical channel is the 16320- of standard
Byte OTU frame structure, and there is fixed OA1OA2 frame alignment byte and LLM byte.
In the above scheme, the framing state machine defines 3 alarm status:OOF, IF and LOF, wherein：
In the OOF state, every 16320-byte section periodically 2 × OA1 of search and 2 × OA2 framing pattern, such as at M
It is determined after the 16320-byte period and has found framing pattern, search process enters the IF state；
In the IF state, it is carried out continuously the detection of OA1OA2OA2 framing sub-pattern in scheduled frame start position, such as in M
Without discovery framing pattern in a continuous 16320-byte period, search process returns to the OOF state；
If the OOF state continues 3ms, the LOF state will be entered；When the IF state uninterruptedly continues 3ms, removing
The LOF alarm.
In the above scheme, the logical channel number (LCN) is obtained by 20 operation of LLM modulus, and recovery process presses standard state machine
It carries out.
In the above scheme, the recovery state machine defines 3 alarm status：OOR, IR and LOR, wherein：
It is identical by continuous multiple " LLM MOD 20 " values in the 16320-byte period, such as obtained, then receive this and is identified as
Logical channel number (LCN), into the IR state；
In the IR state, when " the LLM MOD 20 " value each received in continuous multiple 16320-byte periods with connect
When the ident value received is not identical, into the OOR state, and retain the last one received index value as logical channel number (LCN)；
When the OOR state continues 3ms, into the LOR state；When the IR state continues 3ms, LOR state is exited.
The present invention also provides a kind of optical transfer network MLD method for interface adaptation, include the following steps：
Physical channel bit is demultiplexed to logical channel；
FP mark is generated in each logical channel inner search OA1OA2 framing byte-pattern according to framing detecting state machine
Know and export the channel data after framing, and exports corresponding alarm status；
Each logical channel has path marking LLM byte, obtains logical channel number (LCN) by 20 operation of LLM modulus, restores
Process is carried out by standard state machine, and exports corresponding alarm status；
It will lead between logical channel that there are delay deviations during MLD transmission data, delay benefit must be carried out in receiving end
It repays, eliminates interchannel delay inequality, logical channel frame alignment identifies the mark as interchannel delay inequality, then by patrolling after sequence
It collects in channel number and the corresponding correction FIFO of data write-in, then the Different Logic channel frame alignment by being read in the FIFO that rectifies a deviation
Home position controls the read operation of each lane deskew FIFO, completes the registration process of data delay difference between logical channel；In addition, patrolling
The correction size for collecting channel depends on the depth of correction FIFO；
Logical channel successively interleaves repeating query by 16byte and recombinates out original OTU4 data frame and corresponding OTU4 frame alignment
Signal.
In the above-mentioned methods, the process of framing includes the following contents：
In the OOF state, every 16320-byte section periodically 2 × OA1 of search and 2 × OA2 framing pattern, such as at M
It is determined after the 16320-byte period and has found framing pattern, search process enters the IF state；
In the IF state, it is carried out continuously the detection of OA1OA2OA2 framing sub-pattern in scheduled frame start position, such as in M
Without discovery framing pattern in a continuous 16320-byte period, search process returns to the OOF state；
If the OOF state continues 3ms, the LOF state will be entered；When the IF state uninterruptedly continues 3ms, removing
The LOF alarm.
In the above-mentioned methods, logical channel number (LCN) restores following content：
It is identical by continuous multiple " LLM MOD 20 " values in the 16320-byte period, such as obtained, then receive this and is identified as
Logical channel number (LCN), into the IR state；
In the IR state, when " the LLM MOD 20 " value each received in continuous multiple 16320-byte periods with connect
When the ident value received is not identical, into the OOR state, and retain the last one received index value as logical channel number (LCN)；
When the OOR state continues 3ms, into the LOR state；When the IR state continues 3ms, LOR state is exited.
In the above-mentioned methods, the logical channel delay registration process includes the following steps:
When LOF or LOR state occurs in any logical channel, then all logical channels will be in reset state；When all
Be sequentially written in FP mark and data to correction FIFO when logical channel is in IF and IR state, the read-write operation of FIFO continue into
Row；By FP mark 19 OTU4 frame periods of delay in the channel 0 read in the FIFO that rectifies a deviation, the FP mark in channel 1 delay 18
The OTU4 frame period, and so on, the FP mark in channel 19 does not need to be delayed；FP after delay is indicated with FP_DLY, at delay
After reason, interchannel FP only exists transmission delay deviation；Communication channel delay deviation maximum correction value was required no more than the channel frame period
Half, otherwise delay inequality will be unable to compensate；
In the reading side of correction FIFO, FP_DLY signal after real-time sampling delay, when detect correction FIFO some is logical
When the FP_DLY=1 in road, the reading in the channel is made to can request that rdreq sets 0, controls channel pause and read data, and continue to examine
Survey the channel reached thereafter；
The rdreq in all correction channels FIFO is subjected to line or operation, obtains rdreq_or control signal；By all corrections
The channel FIFO FP_DLY carries out line and operation, obtains fp_dly_and control signal；When detecting rdreq_or is 0, by institute
There is the rdreq signal in the correction channel FIFO while setting 1, the normal read operations in all correction channels FIFO of recovery；
It is subsequent after detecting fp_dly_and=1, then be delayed correction processing complete；
If any channel correction FIFO occurs writing spill-over alarm out, then be delayed processing failure of rectifying a deviation.
The present invention is entangled according to logical channel frame alignment (FP) mark and logical channel number (LCN), control channel extracting and recover
The read operation of inclined FIFO solves the problems, such as the multi-channel data delay deviation occurred in the transmission of 100G MLD interface, and communication channel delay
Correction range by rectify a deviation FIFO depth flexible modulation.
This circuit realizes small scale, and scalability is strong, fully meets the adaptation demand of 100G and super 100G OTN line interface；
In addition the logical channel delay alignment techniques in this method can equally be well applied between 100GE, INTERLAKEN and piece interconnect contour
Fast MLD coffret delay process.
Detailed description of the invention
Fig. 1 is existing OTU4 frame MLD schematic diagram；
Fig. 2 is MLD interface adaption system block diagram provided by the invention；
Fig. 3 is logical channel deskew timing diagram；
Fig. 4 is the flow chart of MLD method for interface adaptation.
Specific embodiment
It is attached with specification combined with specific embodiments below the present invention provides a kind of optical transfer network MLD interface adaption system
Figure is described in detail the present invention.
As shown in Fig. 2, MLD interface adaption system block diagram provided by the invention, including bit_demux module 10, ll_
Align module 20, llm_recovery module 30, deskew_pro module 40 and ll_mux module 50；Wherein：
Bit_demux module 10：Lead to for physical channel data bit to be demultiplexed into logic according to bit polling mode
On road；For OTL4.10 data-interface, every 2 bits by 1 physical channel data distribution to 2 logical channels, logical channel
Rate be original physical channel half；For OTL4.4 data-interface, every 5 bits by 1 physical channel data
5 logical channels are distributed to, the rate of logical channel is 1/5th of original physical channel；
After the completion of bit demultiplexing, raw 20 logical channels of common property, each logical channel is the 16320-byte of standard
(4080 × 4) OTU frame structure, and there is fixed OA1OA2 frame alignment byte and LLM byte.
Ll_align module 20：For completing the detection of the frame alignment byte of 20 tunnel logical channels, channel frame alignment is obtained
(FP) it identifies, and exports the channel data after framing and alarm indication signal, framing is completed by the framing state machine of standard, framing
State machine defines 3 alarm status:OOF (out of frame), IF (framing) and LOF (frame loss).
IF (framing) includes the following contents：
In OOF state, every 16320-byte section periodically searches for 2 × OA1 and 2 × OA2 framing pattern, if some
Determination has found framing pattern after the 16320-byte period, and search process enters IF state；
In IF state, OA1OA2OA2 (3/4/5 byte of logical channel frame first trip) is carried out continuously in scheduled frame start position
Framing sub-pattern detection, if search process returns to without discovery framing sub-pattern in M continuous 16320-byte periods
OOF state；
If OOF state continues 3ms, LOF state will be entered；When IF state uninterruptedly continues 3ms, removing LOF alarm.
If IF state duration is less than 3ms, original OOF state duration is not removed, is needed and later OOF shape
The state duration adds up, and is likely to occur between OOF and IF to avoid framing state and carries out the phenomenon that shaking for a long time.
Llm_recovery module 30：For completing the recovery and sequence of logical channel number (LCN).Logical channel number (LCN) is asked by LLM
Mould 20 (LLM mod 20) operation obtains, for guarantee logical channel number (LCN) stability, recovery process by standard restore state machine into
Row restores state machine and defines 3 alarm status:Restore step-out (OOR), restore correct (IR) and restore to lose (LOR).
Recovery process following content：
By continuous 5 16320-byte periods, if obtained " LLM MOD 20 " value is identical, receive ident value work
For logical channel index value, into IR processing status；
In IR state, when " the LLM MOD 20 " value each received in continuous 5 16320-byte periods with it is accepted
When ident value is not identical, into OOR state, and retain the last one received ident value as logical channel number (LCN)；
When OOR state continues 3ms, into LOR state.When IR state continues 3ms, LOR state is exited.
In order to complete logical channel number (LCN) uniqueness detection and channel number rearrangement, to each channel number recovered into
20 bits of encoded of row.The actual index value of the logical channel is reflected in the position bit in encoded signal uniquely for " 1 ".Such as channel number 3
It is encoded to " 00000000000000001000 ".
20 logical channel index values after coding are arranged, shown in table 1 20 × 20 rectangular channel column are formed
Table.To respectively column carry out the statistics of bit 1 in table, if statistical value is 1, show that the logical channel number (LCN) value of input is unique, otherwise
There are two or above input logic channel there is identical channel number value.There is the position of bit 1 according to each column in table 1, from
Corresponding channel data and FP frame alignment are selected to be sent in the channel of script in 20 logical channels of input.Such as output channel
Encoded information be " 00000000000000001000 ", then select the data in the 3rd input logic channel and FP framing to arrive this
In output channel.
Table 1：Logical channel sorted lists
Deskew_pro module 40：It is identified according to FP and completes logical channel delay registration process；
Deskew_ctrl submodule 410 is equipped in deskew_pro module 40, for controlling 20 tunnels correction FIFO submodule
420 read-write operation.
The delay registration process of logical channel includes the following steps：
A41, it is alerted when effective LOF or LOR occurs in logical channel, FIFO submodule 420 is rectified a deviation on 20 tunnels will be in reset
State, all logical channels of 20 tunnels correction FIFO submodule 420 are read and write enabled nothing by deskew_ctrl submodule 410 at this time
It imitates (for low level), and a small deviation is arranged in the read/write address of 20 tunnels correction FIFO submodule 420 (for example value is
2), prevent 20 tunnels correction FIFO submodule 420 after working normally from read/write address conflict occur；When all logical channels be in IF and
When IR state, all logical channels read-write of 20 tunnels correction FIFO submodule 420 is enabled to have by deskew_ctrl submodule 410
It imitates (for high level), read/write address adds 1 to be incremented by, and is in normal working condition.
A42, according to the logical channel number (LCN) after sequence, the FP mark and data of 20 tunnel logical channels are respectively written into corresponding
It rectifies a deviation in FIFO submodule 420 on 20 tunnels.
A43, deskew_pro module carry out the logical channel FP mark read in FIFO submodule 420 of rectifying a deviation at delay
Reason is eliminated interchannel and is inherently differed；Channel 0FP is delayed 19 OTU4 frame periods, channel 1FP is delayed 18 OTU4 frame periods,
And so on, channel 19FP does not need delay process.FP_ when initial, since that there are circuit delay is poor for interchannel, after delay
The position DLY be it is random, carry out line and operation (&fp_dly as shown in fp_dly [x] waveform in Fig. 3, while to fp_dly), obtain
The fp_dly_and signal identified to alignment control.After detecting fp_dly_and=1, show the channel read from FIFO
Data have been aligned, and the delay deviation of interchannel has been eliminated, and correction process is completed.It can be seen that working as fp_ from the waveform of Fig. 3
When dly_and=1, the fp_dly signal on 20 tunnels is alignment.
A44, real-time sampling is carried out to the FP_DLY signal in the channel after delay, as the FP_DLY=for detecting some channel
When 1, the reading in the channel is made to can request that rdreq [x] sets ' 0 ', controls channel pause and read data, and read address value is protected
It holds.Line or operation (| rdreq) is carried out to the 20bit rdreq of generation control signal simultaneously, obtains rdreq_or signal；Work as inspection
When measuring rdreq_or=0, show it has been found that the maximum logical channel of delay, deskew_ctrl submodule 410 will own at this time
The rdreq reading in channel makes to can request that while setting ' 1 ', restores the normal read operations in all channels；Such as rdreq [x] in Fig. 3 and
Shown in rereq_or waveform.
A45, in delay correction treatment process, go out if the channel of any correction FIFO submodule occurs writing spill-over
(overflow) it alerts, shows that the delay value in the channel has exceeded the maximum correction value of FIFO setting, then the correction processing that is delayed is lost
It loses.
Ll_mux module 50:For completing the recombination of the OTU4 data frame in logical channel after alignment of data.Logical channel
Repeating query successively, which is interleave, by 16byte recombinates out original OTU4 data frame and corresponding OTU4 frame alignment signal.
OTU4 frame regrouping process：On the basis of logical channel 0FP framing signal, by displacement, every 8 clock cycle are to defeated
The logical channel data that enter latch primary, constitute 16bytes data width, then using 8 clock cycle by 20 × 16=
320bytes byte is successively converted to the OTU4 output signal that data width is 40bytes (320bit).
The working principle of present system is as follows：
When input terminal has data input, bit_demux module 10 passes through OTL4.10 data according to bit polling mode
Physical channel data bit is distributed in 20 tunnel logical channels by interface, and then ll_align module 20 was by every 16320-byte weeks
Phase property searches for 2 × OA1 and 2 × OA2 framing pattern, carries out the detection of frame alignment byte, if some 16320-byte period it
Determination has found framing pattern afterwards, and search process enters IF state, and is carried out continuously OA1OA2OA2 in scheduled frame start position
The detection of (3/4/5 byte of logical channel frame first trip) framing sub-pattern, if finding framing sub-pattern in the 16320-byte period,
The framing mark FP signal of logical channel is then generated, and the channel data after framing transports to llm_recovery module 30；If
Without discovery framing pattern in M continuous 16320-byte periods, search process returns to OOF state, when OOF state continues
3ms will enter LOF state, and ll_align module 20 will continue every 16320-byte periodically search framing pattern at this time,
If LOF alarm will remove it was found that framing pattern and IF state uninterruptedly continue 3ms.
Llm_recovery module 30 receives the channel data of the input of ll_align module 20, by continuous 5
The 16320-byte period receives the logical channel index value if obtained " LLM MOD 20 " value is identical, handles shape into IR
State；If " the LLM MOD 20 " value each received and accepted ident value be not identical, into OOR state, and retain last
One received index value is as logical identifier value；When OOR state continues 3ms, into LOR state, for the port number of input
According to llm_recovery module 30 will constantly carry out " LLM MOD 20 " operation, if obtained " LLM MOD 20 " value phase
Together, and IR state continues 3ms, exits LOR state.
When effective LOF or LOR alarm occurs in logical channel, correction FIFO submodule 420 in 20 tunnels will be in reset state,
When all logical channels are in IF and IR state, the read-write of 20 tunnels correction FIFO submodule 420 enabled effectively (is high electricity
It is flat), read/write address adds 1 to be incremented by, and leads to 20 tunnel logics according to the logical channel number (LCN) after sequence in normal working condition
The FP frame alignment mark and data in road are respectively written into corresponding 20 tunnel correction FIFO submodule 420, and deskew_pro module
40 will carry out corresponding delay process to logical channel FP positioning signal, and obtain the FP_DLY positioning signal after sampling time delay,
Deskew_ctrl submodule 410 controls the read-write operation of 20 tunnels correction FIFO submodule 420 simultaneously；When detecting some FIFO
When the FP_DLY=1 in channel, deskew_ctrl submodule 410 makes the reading of channel FIFO to can request that rdreq [x] sets ' 0 ',
As fp_dly_and=1, illustrate that the FP_DLY signal on 20 tunnels has been aligned, at this point, rdreq_or=0, deskew_ctrl submodule
Block 410 makes the rdreq reading of all channel FIFO can request that while set ' 1 ', restores the normal read operations of all FIFO, is being delayed
During correction, such as any channel FIFO occurs writing spill-over (overflow) alarm out, then procedure failure of rectifying a deviation.
The number that data in the channel of 20 tunnels correction fifo module 50 are successively pressed 0-19 by last ll_mux module 50 is suitable
Sequence and 16byte interleave repeating query and recombinate out original OTU4 data frame and corresponding OTU4 frame alignment signal.
The present invention is entangled according to logical channel frame alignment (FP) mark and logical channel number (LCN), control channel extracting and recover
The read operation of inclined FIFO solves the problems, such as the multi-channel data delay deviation occurred in the transmission of 100G MLD interface, and communication channel delay
Correction range by rectify a deviation FIFO depth flexible modulation.
The circuit of the method realizes small scale, and scalability is strong, fully meets the suitable of 100G and super 100G OTN line interface
With demand；In addition the logical channel delay alignment techniques in this method can equally be well applied between 100GE, INTERLAKEN and piece mutually
The high speeds MLD coffret delay process such as company.
As shown in figure 4, including the following steps the present invention also provides a kind of optical transfer network MLD method for interface adaptation：
S1：Physical channel bit demultiplexing：Physical channel is demultiplexing as 20 tunnel logical channels.Each channel OTL4.10
Data are distributed in 2 tunnel logical channels by bit poll or each OTL4.4 channel data by bit poll is distributed to 5 tunnels
In logical channel.
S2：Logical channel frame alignment (FP) is extracted：According to framing detecting state machine, in each logical channel inner search
OA1OA2 framing byte-pattern generates FP signal and exports the channel data after framing, and exports corresponding alarm status.
S3：Logical channel number (LCN) restores and sequence, and each logical channel has path marking (LLM) byte, passes through LLM modulus
20 (LLM mod 20) operations obtain logical channel number (LCN).
Logical channel number (LCN) is some integer between 0 to 19, and for the stability for guaranteeing logical channel number (LCN), recovery process is provided
The protection mechanism of forward and backward, and export corresponding alarm status；Uniqueness is carried out to the logical channel number (LCN) recovered simultaneously
Detection, it is ensured that do not occur the identical situation of logical channel number (LCN)；In addition the logical channel number (LCN) recovered in route is arbitrary, and is connect
Receiving end must also re-start sequence by 0 to 19 number order.
S4：Logical channel delay alignment：It will lead to during MLD transmission data between logical channel there are delay deviation,
Compensation of delay must be carried out in receiving end, is eliminated interchannel delay inequality (deskew), logical channel frame alignment (FP) identifies conduct
The mark of deskew.By in the logical channel number (LCN) and the corresponding correction FIFO of data write-in after sequence, then pass through correction FIFO
The Different Logic channel frame alignment home position of middle reading controls the read operation (read address and reading are enabled) of each lane deskew FIFO,
The registration process of data delay difference between completion logical channel；In addition, the correction size of logical channel depends entirely on correction FIFO
Depth.
Logical channel delay alignment includes the following steps:
B1, during step S20 and S30, such as any logical channel there is LOF or LOR state, then all corrections
The channel FIFO will be in reset state；FP mark is sequentially written in correction FIFO when all logical channels are in IF and IR state
And data, the read-write operation of FIFO persistently carry out.According to the distribution mechanism of OTU4 multichannel, adjacent FP signal is solid there are 1
Fixed OTU4 frame period migration in (lane0) FP of the channel 0 mark 19 OTU4 frame periods of delay that will be read in the FIFO that rectifies a deviation, leads to
(lane1) FP of road 1 mark 18 OTU4 frame periods of delay, and so on, (lane19) the frame FP of channel 19 does not need to be delayed；Delay
FP afterwards is indicated with FP_DLY.After delay process, interchannel FP only exists transmission delay deviation, communication channel delay in this programme
Deviation maximum correction value requires the half for being not more than the channel frame period, and otherwise delay inequality will be unable to compensate.
B2, the reading side in FIFO, the FP_DLY signal after real-time sampling delay, when some channel for detecting correction FIFO
FP_DLY=1 when, the reading in the channel is made to can request that rdreq sets 0, channel pause is controlled and reads data, and continue to test
Thereafter the channel reached；
The rdreq in all correction channels FIFO is subjected to line or operation (| rdreq), obtains rdreq_or control signal.It will
The FP_DLY in all correction channels FIFO carries out line and operation (&fp_dly), obtain fp_dly_and control signal；When detecting
When rdreq_or is 0, the maximum channel correction FIFO that shows to be delayed be arrived, at this time by the rdreq signal of all logical channels
1 is set simultaneously, restores the normal read operations in all correction channels FIFO；It is subsequent after detecting fp_dly_and=1, show from entangling
The channel data read in inclined FIFO has been aligned, and the delay deviation of interchannel has been eliminated, and delay correction processing is completed；If
Any channel correction FIFO occurs writing spill-over (overflow) alarm out, then be delayed processing failure of rectifying a deviation.
S5：Logical channel successively interleaves repeating query by 16byte, and to recombinate out original OTU4 data frame and corresponding OTU4 frame fixed
Position signal.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn that the knots made under the inspiration of the present invention
Structure variation, the technical schemes that are same or similar to the present invention are fallen within the scope of protection of the present invention.
Claims (9)
1. optical transfer network multichannel distribution interface adaption system, which is characterized in that including：
Bit_demux module：Physical channel data bit is demultiplexed into logical channel according to bit polling mode；
Ll_align module：For completing the detection of the frame alignment byte of logical channel, FP mark is obtained, and after exporting framing
Channel data and alarm indication signal, framing are completed by the framing state machine of standard；
Llm_recovery module：For completing the recovery and sequence of logical channel number (LCN), and recovery process restores state by standard
Machine carries out；
Deskew_pro module：For identifying the delay registration process for completing logical channel according to the FP, by deskew_ctrl
Submodule and FIFO submodule composition, wherein FIFO submodule completes the adjustment of logical channel delay correction and depth is entangled by maximum
Inclined parameter determines, and the read-write operation of deskew_ctrl submodule error correct fifo module；
Ll_mux module:For completing the recombination of the data frame in logical channel after alignment of data.
2. the system as claimed in claim 1, which is characterized in that the bit polling mode includes but is not limited to：
For OTL4.10 data-interface, every 2 bits by 1 physical channel data distribution to 2 logical channels, logical channel
Rate be original physical channel half；
For OTL4.4 data-interface, every 5 bits by 1 physical channel data distribution to 5 logical channels, logical channel
Rate is 1/5th of original physical channel；
After the completion of bit demultiplexing, raw 20 logical channels of common property, each logical channel is the 16320-byte of standard
OTU frame structure, and there is fixed OA1OA2 frame alignment byte and logical channel label L LM byte.
3. the system as claimed in claim 1, which is characterized in that the framing state machine defines 3 alarm status:OOF,IF
And LOF, wherein：
In the OOF state, every 16320-byte periodically 2 × OA1 of search and 2 × OA2 framing pattern, such as in M 16320-
It is determined after the byte period and has found framing pattern, search process enters the IF state；
In the IF state, it is carried out continuously the detection of OA1OA2OA2 framing sub-pattern in scheduled frame start position, such as in M company
Without discovery framing pattern in the continuous 16320-byte period, search process returns to the OOF state；
If the OOF state continues 3ms, the LOF state will be entered；When the IF state uninterruptedly continues 3ms, described in removing
LOF alarm.
4. the system as claimed in claim 1, which is characterized in that the logical channel number (LCN) is obtained by 20 operation of LLM modulus, extensive
Multiple process is carried out by standard state machine.
5. the system as claimed in claim 1, which is characterized in that the recovery state machine defines 3 alarm status：OOR,IR
And LOR, wherein：
It is identical by continuous multiple " LLM MOD 20 " values in the 16320-byte period, such as obtained, then receive this and is identified as logic
Channel number, into the IR state；
In the IR state, when " LLM MOD20 " value each received in continuous multiple 16320-byte periods with it is accepted
When ident value is not identical, into the OOR state, and retain the last one received index value as logical channel number (LCN)；
When the OOR state continues 3ms, into the LOR state；When the IR state continues 3ms, LOR state is exited.
6. optical transfer network multichannel distribution interface adaptation method, which is characterized in that include the following steps：
Physical channel data bit is demultiplexed into logical channel according to bit polling mode；
FP mark is generated simultaneously in each logical channel inner search OA1OA2 framing byte-pattern according to framing detecting state machine
Channel data after exporting framing, and corresponding alarm status is exported, the framing state machine defines 3 alarm status:
OOF, IF and LOF；
Each logical channel has logical channel label L LM byte, obtains logical channel number (LCN) by 20 operation of LLM modulus, restores
Process is restored state machine by standard and is carried out, and exports corresponding alarm status；The recovery state machine defines 3 alarm shapes
State:Restore step-out OOR, restore correct IR and restore to lose LOR；
It will lead between logical channel that there are delay deviations during multichannel Distributed Transmission data, must be delayed in receiving end
Interchannel delay inequality is eliminated in compensation, and logical channel frame alignment identifies the mark as interchannel delay inequality, then will be after sequence
It is then fixed by the Different Logic channel frame read in correction FIFO in logical channel number (LCN) and the corresponding correction FIFO of data write-in
The registration process of data delay difference between logical channel is completed in the read operation of each lane deskew FIFO of bit identification position control；In addition,
The correction size of logical channel depends on the depth of correction FIFO；
Logical channel successively interleaves repeating query by 16byte and recombinates out original OTU4 data frame and corresponding OTU4 frame alignment signal.
7. method as claimed in claim 6, which is characterized in that the process of framing includes the following contents：
In the OOF state, every 16320-byte periodically 2 × OA1 of search and 2 × OA2 framing pattern, such as in M 16320-
It is determined after the byte period and has found framing pattern, search process enters the IF state；
In the IF state, it is carried out continuously the detection of OA1OA2OA2 framing sub-pattern in scheduled frame start position, such as in M company
Without discovery framing pattern in the continuous 16320-byte period, search process returns to the OOF state；
If the OOF state continues 3ms, the LOF state will be entered；When the IF state uninterruptedly continues 3ms, described in removing
LOF alarm.
8. method as claimed in claim 6, which is characterized in that logical channel number (LCN) recovery process following content：
It is identical by continuous multiple " LLM MOD 20 " values in the 16320-byte period, such as obtained, then receive this and is identified as logic
Channel number, into the IR state；
In the IR state, when " LLM MOD20 " value each received in continuous multiple 16320-byte periods with it is accepted
When ident value is not identical, into the OOR state, and retain the last one received index value as logical channel number (LCN)；
When the OOR state continues 3ms, into the LOR state；When the IR state continues 3ms, LOR state is exited.
9. method as claimed in claim 6, which is characterized in that the registration process of data delay difference includes between the logical channel
Following steps：
When LOF or LOR state occurs in any logical channel, then all logical channels will be in reset state；When all logics
FP mark is sequentially written in correction FIFO when channel is in IF and IR state and data, the read-write operation of FIFO persistently carry out；It will
FP mark 19 OTU4 frame periods of delay in the channel 0 read in correction FIFO, the FP mark in channel 1 are delayed 18 OTU4 frame weeks
Phase, and so on, the FP mark in channel 19 does not need to be delayed；FP after delay is indicated with FP_DLY, after delay process, channel
Between FP only exist transmission delay deviation；Communication channel delay deviation maximum correction value requires the half for being not more than the channel frame period, otherwise
Delay inequality will be unable to compensate；
FP_DLY signal behind the reading side for rectifying a deviation FIFO, real-time sampling delay, when some channel for detecting correction FIFO
When FP_DLY=1, the reading in the channel is made to can request that rdreq sets 0, controls channel pause and read data, and continue to test it
The channel reached afterwards；
The rdreq in all correction channels FIFO is subjected to line or operation, obtains rdreq_or control signal；By all correction FIFO
Channel FP_DLY carries out line and operation, obtains fp_dly_and control signal；When detecting rdreq_or is 0, entangled all
The rdreq signal in the inclined channel FIFO sets 1 simultaneously, restores the normal read operations in all correction channels FIFO；
It is subsequent after detecting fp_dly_and=1, then be delayed correction processing complete；
If any channel correction FIFO occurs writing spill-over alarm out, then be delayed processing failure of rectifying a deviation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610124011.XA CN105812062B (en) | 2016-03-04 | 2016-03-04 | Optical transfer network MLD method for interface adaptation and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610124011.XA CN105812062B (en) | 2016-03-04 | 2016-03-04 | Optical transfer network MLD method for interface adaptation and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105812062A CN105812062A (en) | 2016-07-27 |
| CN105812062B true CN105812062B (en) | 2018-11-30 |
Family
ID=56467650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610124011.XA Active CN105812062B (en) | 2016-03-04 | 2016-03-04 | Optical transfer network MLD method for interface adaptation and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105812062B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018098684A1 (en) * | 2016-11-30 | 2018-06-07 | 华为技术有限公司 | Communication method and apparatus for passive optical network |
| CN109861807A (en) * | 2019-02-28 | 2019-06-07 | 烽火通信科技股份有限公司 | Logical channel alignment schemes and system under multi-channel mode |
| CN111416630A (en) * | 2020-03-05 | 2020-07-14 | 烽火通信科技股份有限公司 | Coding and decoding method and system |
| CN113660033B (en) * | 2021-08-31 | 2022-09-16 | 烽火通信科技股份有限公司 | Method and system for rapidly recovering instantaneous interruption of high-speed interface |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999030440A1 (en) * | 1997-12-10 | 1999-06-17 | L-3 Communications Corporation | S-cdma fixed wireless loop system employing subscriber unit/radio base unit super-frame alignment |
| CN1334655A (en) * | 2001-08-17 | 2002-02-06 | 清华大学 | Filling method of protecting gap in orthogonal frequency division multiplexing modulation system |
| CN1534906A (en) * | 2003-04-02 | 2004-10-06 | ��Ϊ��������˾ | Frame aligning method and circuit |
| CN1571328A (en) * | 2003-07-17 | 2005-01-26 | 深圳市中兴通讯股份有限公司 | Super large-scale cross connection device and method used for synchronous digital transmission system |
| CN1926896A (en) * | 2004-04-23 | 2007-03-07 | Ut斯达康通讯有限公司 | Method and apparatus for multi-antanna signal transmission in RF long-distance wireless BS |
| CN101039158A (en) * | 2006-03-13 | 2007-09-19 | 中兴通讯股份有限公司 | Apparatus for canceling frame dislocation |
| US7373454B1 (en) * | 2003-10-28 | 2008-05-13 | Altera Corporation | Pattern detect and byte align circuit using CAM |
| CN102316061A (en) * | 2010-07-07 | 2012-01-11 | 中国科学院微电子研究所 | Time synchronization method and device for frequency hopping orthogonal frequency division multiplexing system |
| CN103152118A (en) * | 2013-02-07 | 2013-06-12 | 中兴通讯股份有限公司 | Base band unit and remote radio unit data service synchronization method, device and system |
| CN103561472A (en) * | 2013-10-30 | 2014-02-05 | 中国人民解放军理工大学 | Multi-service link distribution and reorganization device and method |
| CN104125053A (en) * | 2014-08-12 | 2014-10-29 | 电子科技大学中山学院 | Method and device for capturing synchronous frame |
| CN104935393A (en) * | 2015-06-02 | 2015-09-23 | 瑞斯康达科技发展股份有限公司 | Frame synchronization method and device |
| CN105024745A (en) * | 2015-05-31 | 2015-11-04 | 中国电子科技集团公司第十研究所 | Method for adjusting time delays of multiple broadband receiving signals |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101658204B1 (en) * | 2010-12-17 | 2016-09-30 | 한국전자통신연구원 | Apparatus and method for estimating timestamp |
-
2016
- 2016-03-04 CN CN201610124011.XA patent/CN105812062B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999030440A1 (en) * | 1997-12-10 | 1999-06-17 | L-3 Communications Corporation | S-cdma fixed wireless loop system employing subscriber unit/radio base unit super-frame alignment |
| CN1334655A (en) * | 2001-08-17 | 2002-02-06 | 清华大学 | Filling method of protecting gap in orthogonal frequency division multiplexing modulation system |
| CN1534906A (en) * | 2003-04-02 | 2004-10-06 | ��Ϊ��������˾ | Frame aligning method and circuit |
| CN1571328A (en) * | 2003-07-17 | 2005-01-26 | 深圳市中兴通讯股份有限公司 | Super large-scale cross connection device and method used for synchronous digital transmission system |
| US7373454B1 (en) * | 2003-10-28 | 2008-05-13 | Altera Corporation | Pattern detect and byte align circuit using CAM |
| CN1926896A (en) * | 2004-04-23 | 2007-03-07 | Ut斯达康通讯有限公司 | Method and apparatus for multi-antanna signal transmission in RF long-distance wireless BS |
| CN101039158A (en) * | 2006-03-13 | 2007-09-19 | 中兴通讯股份有限公司 | Apparatus for canceling frame dislocation |
| CN102316061A (en) * | 2010-07-07 | 2012-01-11 | 中国科学院微电子研究所 | Time synchronization method and device for frequency hopping orthogonal frequency division multiplexing system |
| CN103152118A (en) * | 2013-02-07 | 2013-06-12 | 中兴通讯股份有限公司 | Base band unit and remote radio unit data service synchronization method, device and system |
| CN103561472A (en) * | 2013-10-30 | 2014-02-05 | 中国人民解放军理工大学 | Multi-service link distribution and reorganization device and method |
| CN104125053A (en) * | 2014-08-12 | 2014-10-29 | 电子科技大学中山学院 | Method and device for capturing synchronous frame |
| CN105024745A (en) * | 2015-05-31 | 2015-11-04 | 中国电子科技集团公司第十研究所 | Method for adjusting time delays of multiple broadband receiving signals |
| CN104935393A (en) * | 2015-06-02 | 2015-09-23 | 瑞斯康达科技发展股份有限公司 | Frame synchronization method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105812062A (en) | 2016-07-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105812062B (en) | Optical transfer network MLD method for interface adaptation and system | |
| CN101729940B (en) | Method for sending data to multiple communication channels and method for receiving data | |
| KR101881561B1 (en) | Ethernet signal transport method and scheduling method, and apparatus and system thereof | |
| CN104113740B (en) | A kind of mixed format signal transmission by optical fiber device | |
| US6496540B1 (en) | Transformation of parallel interface into coded format with preservation of baud-rate | |
| US7127645B2 (en) | Skew compensation method | |
| US9281911B1 (en) | Method of multiple lane distribution (MLD) deskew | |
| US8848747B2 (en) | Method and device for recovering OTUk frame, and system for transporting OTUk frame | |
| US20100162033A1 (en) | Ethernet apparatus capable of lane fault recovery and methods for transmitting and receiving data | |
| JP2003516678A (en) | System and method for transmitting data on a return path of a cable television system | |
| CN1864352A (en) | Method, apparatus and system for optical communication | |
| CN102726058A (en) | Optical network switching nodes, optical burst synchronization method and circuit frame of multi-frame cluster | |
| CN105208467B (en) | The frame alignment means of broadband access network system | |
| CA2472074A1 (en) | Receiving streams over asynchronous networks | |
| CN102318303B (en) | Transmission of parallel data flows on a parallel bus | |
| US20110249968A1 (en) | Fast Transceiver Control Interface | |
| CN105281883A (en) | Multi-channel synchronization method, synchronization device and system | |
| US9584307B2 (en) | Transmission apparatus | |
| US20050036524A1 (en) | Method and apparatus for multiplexing Ethernet channels | |
| CN110535532A (en) | It is a kind of to polarize unrelated pulse amplitude modulated signal coherent reception method and system | |
| US20100008678A1 (en) | Multi-Channel Optical Transport Network Training Signal Wrapper | |
| CN108322483A (en) | A kind of implementation method of the receiving terminal circuit based on JESD204B agreements | |
| JP5863595B2 (en) | Time slot interleave transmission method and time slot interleave transmission system | |
| US9143420B2 (en) | Data transport system, receiver and transmitter | |
| US20150010312A1 (en) | Optical data interface with electrical forwarded clock |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |