CN1713602A - Improvement of virtual cascade delay compensation - Google Patents
Improvement of virtual cascade delay compensation Download PDFInfo
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- CN1713602A CN1713602A CN 200410049840 CN200410049840A CN1713602A CN 1713602 A CN1713602 A CN 1713602A CN 200410049840 CN200410049840 CN 200410049840 CN 200410049840 A CN200410049840 A CN 200410049840A CN 1713602 A CN1713602 A CN 1713602A
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Abstract
First makes write-in direction process for storage device: changes numbering method for time slot, and copies location indicating signal and SQ value of VC-3 or VC-4 to N VC-12 branches; then makes read-out direction process for storage device, and separately generates read-out time sequence of VC-12 branch and N virtual VC-12 branches, and adjusting chance bit of VC-3 and VC-4; N virtual VC-12 branches are taken as N members in one VCG group to make independent processing, to monitor distance of read-write address and to make relevant process.
Description
Technical field
The present invention relates to the Digital Transmission field, specifically, relate to Virtual Concatenation delay compensation method in SDH (Synchronousdigital hierarchy, the i.e. SDH (Synchronous Digital Hierarchy)) system.
Background technology
In the SDH system, for flexible networking and improve bandwidth usage efficient, usually with the mode Data transmission of Virtual Concatenation.The Virtual Concatenation technology is exactly to allow arbitrarily a plurality of little containers to cascade up and assemble to become a bigger container and come transmitting data service.This technology can cascade VC-11, VC-12, the container of different rates such as VC-3, VC-4, and allow very short grained bandwidth adjustment, provide than the more accurate bandwidth of continuous cascade.In addition, because the Virtual Concatenation business is regarded as a plurality of independently containers (being the container of non-cascade) in network, so can be by SDH/SONET Network Transmission traditional, that do not support cascade, as long as terminal equipment has the Virtual Concatenation function.The passage that the advantage of Virtual Concatenation maximum is to make the SDH network that suitable size can be provided has been avoided the waste of bandwidth to data service.Owing to constitute the path difference that the member walked of Virtual Concatenation, cause different branch that different time-delays is arranged.In order to obtain correct data, the receiving chip in downstream must align the branch road that receives according to original rule, this process is " recovering virtual cascades " or " compensation of delay ", the recovering virtual cascades ability of chip is strong more, it is just big more to delay time between the branch road that system allowed, and the performance of system is also just high more thereupon.The method that realizes the Virtual Concatenation compensation of delay generally be will have time delay metadata cache in memory, according to the rule of alignment data are read again.Under identical processing method, the amount of capacity of memory has determined Virtual Concatenation compensation of delay ability.In order to improve Virtual Concatenation compensation of delay ability, generally adopt the bigger external RAM of capacity (RandomAccess Memory, random access memory) data cached, Virtual Concatenation compensation of delay ability is subjected to the influence of the processing method of external RAM capacity and employing simultaneously.
In actual applications, the VCG that has in the same system (Virtual ConcatenationGroup, be virtual cascade group) be to be the mapping particle with VC-12, have with VC-3 or VC-4 as the mapping particle, in this case, adopt the different disposal method to produce very big influence to the VCG compensation of delay ability of VC-3 member or VC-4 member's formation.
Prior art usually the memory space that is used for buffer memory (inside or external RAM) from being divided into the N piece in logic, wherein N is the VCG greatest member number of system, have at the same time in the system of VC-4, VC-3 and VC-12, in order to tackle various possible configuring conditions, N is exactly whole members ways when being VC-12.Use the high position of member's time-gap number then, to distinguish logical block as the read/write address of RAM.Like this, VC-4, VC-3 take identical memory space with VC-12 member, because the speed ratio VC-12 of VC-3, VC-4 is high a lot, thereby fail to make full use of the space of RAM, cause the compensation of delay ability of VC-4, VC-3 has been differed from much than VC-12.
Summary of the invention
Technical problem to be solved by this invention is that prior art existence ram space is utilized is insufficient, cause shortcoming, so that the method that makes full use of ram space, improves high-order virtual cascade group compensation of delay ability to be provided in a kind of system that VC-12 and VC-3 or VC-4 virtual cascade group arranged at the same time to high-order mapping particle VC-4 and VC-3 compensation of delay ability.
For achieving the above object, the present invention proposes the method for a kind of VC-3 of raising or VC-4 Virtual Concatenation compensation of delay ability, it is characterized in that having at the same time in the system of VC-12 and VC-3 or VC-4, may further comprise the steps:
(1) memory device is write the processing of Inbound: change the time-gap number method, make VC-3 or VC-4 branch road become in form independently N bar VC-12 branch road, and location index signal and the SQ value of VC-3 or VC-4 duplicated the branch road to this N bar VC-12, this N bar VC-12 branch road is handled according to independent VC-12 branch road;
(2) memory device is read the processing of direction: the adjustment chance position of reading direction sequential, VC-3 or VC-4 that generates VC-12 branch road and N virtual VC-12 branch road respectively, N virtual VC-12 branch road carried out independent process as the member that same VCG organizes, and the distance of supervision read/write address, carry out respective handling.
Described step (1) further may further comprise the steps:
A, change time-gap number method, change discontinuous coded system into the continuous programming code mode, make VC-3 or VC-4 branch road remove path overhead outer each time slot independently numbering is arranged, the VC-3 or the VC-4 branch road that change after numbering become in form independently N bar VC-12 branch road, this N VC-12 branch road occupies N * 4 row of SDH frame structure, and the part overhead digit is put payload, and data capacity is consistent with VC-3 or VC-4;
B, the location index signal J1 of VC-3 or VC-4 is duplicated to above-mentioned N bar VC-12 branch road;
C, the SQ value is duplicated to the N of VC-3 or VC-4 branch road virtual VC-12 branch road.Every VC-3 or VC-4 branch road have only a SQ value, by transforming, this SQ value are converted into the individual virtual VC-12 SQ value separately of N;
D, VC-12 that above-mentioned N bar is virtual handle according to VC-12 branch road independently, and the payload data of every virtual VC-12 branch road is write each self-corresponding memory device logical block.
SQ value among the described step c is extracted from expense position H4, SQ value be converted into N virtual VC-12 separately the processing method of SQ value be: SQ_new=SQ*N+tslot, wherein tslot is the numbering that N is listed as in original VC-3 or the VC-4 branch road.
Described step (2) further may further comprise the steps:
A, generate the sequential read direction according to the rate-matched principle, original VC-12 branch road generates according to the SDH sequential of standard; Original VC-3 or VC-4 branch road generate according to the sequential of N virtual VC-12 branch road, interleave principle according to time slot and carry out time-gap number, and the path overhead position of VC-12 is made as payload, and in N payload position of section overhead position arrangement;
The adjustment chance position of b, generation VC-3 or VC-4, the adjustment chance position of VC-3 or VC-4 are evenly distributed on N the virtual VC-12 branch road;
C, virtual N bar VC-12 branch road is carried out independent process as the member of same VCG group, according to the counterlogic piece reading of data of time-gap number from memory device;
D, monitor the distance of read/write address, judge read-write directional rate difference, be higher than and write directional rate, then the positive justification position is made as and fills in byte if read the speed of direction; Otherwise, then the negative justification position is made as payload, to guarantee read-write directional rate unanimity.
Among the described step c, need to guarantee the adjustment chance position adjacent continuous of N virtual VC-12.
Have at the same time in the system of VC-12 and VC-3, the value of described N is 21;
Have at the same time in the system of VC-12 and VC-4, the value of described N is 65.
The present invention is by changing the read/write address Methods for Coding to external RAM, and adjustment VC-3, the time-gap number method of VC-4 branch road, framing signal and chance are adjusted the position, the VC-3 branch road is used as 21 VC-12 branch road virtual concatenation group to be handled, the VC-4 branch road is used as 65 VC-12 virtual concatenations handles, improved compensation of delay ability the virtual cascade group of VC-3 and VC-4 branch road.Described method is when handling the system of system that VC-3 and VC-12 are arranged simultaneously or VC-4 and VC-12, can utilize the space of external RAM to greatest extent, externally under the situation that the RAM volume space is certain, improve the compensation of delay ability of chip, can make the compensation of delay scope of VC-3 and VC-4 improve about 21 and 65 times respectively virtual cascade group.
Description of drawings
Fig. 1 is the flow chart of the method for the invention.
Fig. 2 is the schematic diagram of adjustment VC-3 branch road time-gap number of the present invention.
Fig. 3 is the expense J1 indication schematic diagram that duplicates the VC-3 branch road.
Fig. 4 is that VC-3 of the present invention reads the schematic diagram that the direction sequential generated and adjusted the generation of chance position.
Embodiment
Below in conjunction with accompanying drawing, the method for the invention is described in detail.
Fig. 1 is the flow chart of the method for the invention.According to function with system divides for writing direction and read two big modules of direction, generate the write address of memory device respectively and read the address.Wherein write direction and comprise the time-gap number conversion, frame head duplicates, and SQ regeneration and write address generate several sections; Read direction and comprise that reading the direction sequential generates, adjust the chance position and generate, read the directional rate adjustment and read the address to generate several modules; The distance of the read/write address by monitoring memory device is dynamically adjusted the speed of reading direction.
One, have at the same time in the system of VC-12 and VC-3, VC-3 virtual cascade group delay compensation method of the present invention may further comprise the steps:
1, memory device is write the processing of Inbound: a, is changed the time-gap number method, change discontinuous coded system into the continuous programming code mode, make the VC-3 branch road remove path overhead outer each time slot independently numbering is arranged, the VC-3 branch road that changes after numbering becomes in form independently 21 VC-12 branch roads, these 21 VC-12 branch roads occupy 84 row of SDH frame structure, and the path overhead position also places payload, and data capacity is consistent with VC-3.
B, the location index signal (J1) of VC-3 is duplicated to 21 above-mentioned VC-12 branch roads;
C, SQ value (extracting from expense position H4, referring to related protocol) is duplicated to 21 of the VC-3 branch road virtual VC-12 branch roads.Every the VC-3 branch road has only a SQ, needs by transforming this SQ to be converted into 21 virtual VC-12 SQ separately.Processing method is as follows: SQ_new=SQ*21+tslot, wherein tslot is the numbering of 21 row in original VC-3 branch road.
D, above-mentioned 21 virtual VC-12 are handled according to VC-12 branch road independently, the payload data of every virtual VC-12 branch road is write each self-corresponding memory device logical block.
2, memory device is read the processing of direction:
A, generate the sequential read direction according to the rate-matched principle, original VC-12 branch road generates according to the SDH sequential of standard; Original VC-3 branch road generates according to the sequential of 21 virtual VC-12, and the principle time-gap number according to time slot interleaves is made as payload to the path overhead position of VC-12, also in 21 payload position of section overhead position arrangement, referring to accompanying drawing 4.
The adjustment chance position of b, generation VC-3, the adjustment chance position of VC-3 is evenly distributed on 21 virtual VC-12 branch roads, adjustment chance position shown in the accompanying drawing is placed on first row of each multi-frame, but the present invention is not so limited, as long as guarantee the adjustment chance position adjacent continuous of 21 virtual VC-12.
C, with the member of 21 virtual VC-12 branch roads as same VCG group, independent process is according to the counterlogic piece reading of data of time-gap number from memory device.D, monitor the distance of read/write address, judge read-write directional rate difference, be higher than and write directional rate, then the positive justification position is made as and fills in byte if read the speed of direction, otherwise, then the negative justification position is made as payload, to guarantee read-write directional rate unanimity.
Two, have at the same time in the system of VC-12 and VC-4, VC-4 virtual cascade group delay compensation method of the present invention may further comprise the steps:
1, memory device is write the processing of Inbound:
A, change time-gap number method, change discontinuous coded system into the continuous programming code mode, make the VC-4 branch road remove path overhead outer each time slot independently numbering is arranged, the VC-4 branch road that changes after numbering becomes in form independently 65 VC-12 branch roads, these 65 VC-12 branch roads occupy 260 row of SDH frame structure, and the path overhead position also places payload, and data capacity is consistent with VC-4.
B, the location index signal (J1) of VC-4 is duplicated to 65 VC-12 branch roads;
C, SQ value (extracting from expense position H4, referring to related protocol) is duplicated to 65 of the VC-4 branch road virtual VC-12 branch roads.Every the VC-4 branch road has only a SQ, needs by transforming this SQ to be converted into 65 virtual VC-12 SQ separately.Processing method is as follows: SQ_new=SQ*65+tslot, wherein tslot is the numbering of 65 row in original VC-4 branch road.
D, above-mentioned 65 virtual VC-12 are handled according to VC-12 branch road independently, the payload data of every virtual VC-12 branch road is write each self-corresponding memory device logical block.
2, memory device is read the processing of direction:
A, generate the sequential read direction according to the rate-matched principle, original VC-12 branch road generates according to the SDH sequential of standard; Original VC-4 branch road generates according to the sequential of 65 virtual VC-12, and the principle time-gap number according to time slot interleaves is made as payload to the path overhead position of VC-12, also in 65 payload position of section overhead position arrangement.
The adjustment chance position of b, generation VC-4, the adjustment chance position of VC-4 is evenly distributed on 65 virtual VC-12 branch roads, as long as guarantee the adjustment chance position adjacent continuous of 65 virtual VC-12.
C, with the member of 65 virtual VC-12 branch roads as same VCG group, independent process is according to the counterlogic piece reading of data of time-gap number from memory device.
D, monitor the distance of read/write address, judge read-write directional rate difference, be higher than and write directional rate, then the positive justification position is made as and fills in byte if read the speed of direction, otherwise, then the negative justification position is made as payload, to guarantee read-write directional rate unanimity.
Fig. 2 has represented to change the process of time-gap number.The system that VC-3, VC-4, VC-12 branch road are arranged simultaneously, { numbering of tslot} is to time-gap number for M, N in general employing.Wherein tslot is the numbering of the row of 21 among the TUG-3 for the VC-3 branch road; For the VC-4 branch road, be the numbering of the row of 65 among the TUG-3; For VC-12, be exactly the time-gap number of VC-12.W is the numbering of three AU3 among AUG of expression for VC-3, then is zero for VC-4; M represents in the STM_n structure, from the numbering of 0-n-1.In processing method of the present invention, change this discontinuous numbering into continuous numbering, for VC-3, conversion formula is:
vc_num＝(tslot*3+W)*n+M
For the VC-4 conversion formula be:
vc_num＝(tslot*n)+M
By such conversion, can convert discontinuous time-gap number to continuous numbering, and in a TUG-3,21 row of VC-3 and 65 row of VC-4 all there has been independently numbering.The AUG-3 form that Fig. 2 is multiplexed into three AU-3 is an example, and wherein preceding two AU-3 are made of VC-3, and the 3rd AU-3 is made of VC-12." type " represented the type of multiplexing order and each time slot.Former numbering is according to { coded system of tslot} is to time-gap number for AUG, AU3.The 0-62 that newly is encoded to that obtains according to conversion formula changes in proper order.
Fig. 3 is the schematic diagram that duplicates the J1 indication, for graphic simplicity, and the situation of only having drawn one road VC-3.J1 represents the path overhead of VC-3 branch road among the figure, also is first byte of VC-3 branch road, in the Virtual Concatenation compensation of delay, is used as one of sign of alignment VC-3 payload.C3_en, vc_num are respectively the payload indication and the time-gap numbers of VC-3 branch road.J1_new is newly-generated J1 indication, and as can be seen, originally 21 of VC-3 total J1 indications of time slot are duplicated to each time slot, and j1_new at this moment only uses as framing signal, does not indicate the path overhead position.
Fig. 4 generates the schematic diagram of reading the direction sequential and adjusting the chance position, for graphic simplicity, and the situation of only having drawn one road VC-3 branch road among the figure.Two frames are represented two frames in the VC-12 multi-frame among the figure, and wherein not having the dot-hatched interval of numbering is between non-payload section, and all the other are between payload section and adjust the chance position; Be between the payload section that takies of the section overhead position from standard SDH structure between numbered first three columns shadow region; The left oblique line and the right oblique line interval of 0-21 numbering are respectively positive justification opportunity position and negative justification opportunity position; In the multi-frame, except first frame is done the special processing, its excess-three frame is identical with " second frame " structure shown in Figure 2.This figure only shows the adoptable a kind of structure of basic principle of the present invention, and concrete locations of structures is not limited.
Claims (8)
1, a kind of method that improves VC-3 or VC-4 Virtual Concatenation compensation of delay ability is characterized in that having at the same time in the system of VC-12 and VC-3 or VC-4, may further comprise the steps:
(1) memory device is write the processing of Inbound: change the time-gap number method, make VC-3 or VC-4 branch road become in form independently N bar VC-12 branch road, and location index signal and the SQ value of VC-3 or VC-4 duplicated the branch road to this N bar VC-12, this N bar VC-12 branch road is handled according to independent VC-12 branch road;
(2) memory device is read the processing of direction: the adjustment chance position of reading direction sequential, VC-3 or VC-4 that generates VC-12 branch road and N virtual VC-12 branch road respectively, N virtual VC-12 branch road carried out independent process as the member that same VCG organizes, and the distance of supervision read/write address, carry out respective handling.
2, the method for raising VC-3 according to claim 1 or VC-4 Virtual Concatenation compensation of delay ability is characterized in that described step (1) further may further comprise the steps:
A, change time-gap number method, change discontinuous coded system into the continuous programming code mode, make VC-3 or VC-4 branch road remove path overhead outer each time slot independently numbering is arranged, the VC-3 or the VC-4 branch road that change after numbering become in form independently N bar VC-12 branch road, this N VC-12 branch road occupies N * 4 row of SDH frame structure, and the part overhead digit puts payload, and data capacity is consistent with VC-3 or VC-4;
B, the location index signal J1 of VC-3 or VC-4 is duplicated to above-mentioned N bar VC-12 branch road;
C, the SQ value is duplicated to the N of VC-3 or VC-4 branch road virtual VC-12 branch road.Every VC-3 or VC-4 branch road have only a SQ value, by transforming, this SQ value are converted into the individual virtual VC-12 SQ value separately of N;
D, VC-12 that above-mentioned N bar is virtual handle according to VC-12 branch road independently, and the payload data of every virtual VC-12 branch road is write each self-corresponding memory device logical block.
3, the method for raising VC-3 according to claim 2 or VC-4 Virtual Concatenation compensation of delay ability is characterized in that the SQ value among the described step c is extracted from expense position H4.
4, the method for raising VC-3 according to claim 2 or VC-4 Virtual Concatenation compensation of delay ability, it is characterized in that, the SQ value be converted into N virtual VC-12 separately the processing method of SQ value be: SQ_new=SQ*N+tslot, wherein tslot is the numbering that N is listed as in original VC-3 or the VC-4 branch road.
5, the method for raising VC-3 according to claim 1 and 2 or VC-4 Virtual Concatenation compensation of delay ability is characterized in that the method for described change time-gap number is:
For VC-3:vc_num=(tslot*3+W) * n+M; For VC-4:vc_num=(tslot*n)+M, W is the numbering of three AU3 among AUG of expression for VC-3, then is zero for VC-4; M represents in the STM_n structure, from the numbering of 0-n-1.
6, the method for raising VC-3 according to claim 1 or VC-4 Virtual Concatenation compensation of delay ability is characterized in that described step (2) further may further comprise the steps:
A, generate the sequential read direction according to the rate-matched principle, original VC-12 branch road generates according to the SDH sequential of standard; Original VC-3 or VC-4 branch road generate according to the sequential of N virtual VC-12 branch road, interleave principle according to time slot and carry out time-gap number, and the path overhead position of VC-12 is made as payload, and in N payload position of section overhead position arrangement;
The adjustment chance position of b, generation VC-3 or VC-4, the adjustment chance position of VC-3 or VC-4 are evenly distributed on N the virtual VC-12 branch road;
C, virtual N bar VC-12 branch road is carried out independent process as N member of same virtual cascade group, according to the counterlogic piece reading of data of time-gap number from memory device;
D, monitor the distance of read/write address, judge read-write directional rate difference, be higher than and write directional rate, then the positive justification position is made as and fills in byte if read the speed of direction; Otherwise, then the negative justification position is made as payload, to guarantee read-write directional rate unanimity.
7, the method for raising VC-3 according to claim 6 or VC-4 Virtual Concatenation compensation of delay ability is characterized in that, among the described step c, needs to guarantee the adjustment chance position adjacent continuous of N virtual VC-12.
8, according to the method for claim 1,2 or 5 described raising VC-3 or VC-4 Virtual Concatenation compensation of delay ability, it is characterized in that having at the same time in the system of VC-12 and VC-3, the value of described N is 21; Have at the same time in the system of VC-12 and VC-4, the value of described N is 65.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010020191A1 (en) * | 2008-08-20 | 2010-02-25 | 中兴通讯股份有限公司 | Method and apparatus for improving the effect of the synchronous digital hierarchy virtual concatenation delay compensation buffer |
| CN101136710B (en) * | 2006-10-25 | 2011-06-22 | 中兴通讯股份有限公司 | Data storage control method of virtual cascade recover |
| CN1983887B (en) * | 2006-04-22 | 2011-09-14 | 华为技术有限公司 | Method and system for processing different time-gap number strategy |
| CN101621344B (en) * | 2008-06-30 | 2011-12-28 | 华为技术有限公司 | Method for determining virtual concatenation alignment out-of-limit and device for processing communication services |
| WO2014012405A1 (en) * | 2012-07-16 | 2014-01-23 | 中兴通讯股份有限公司 | Method and apparatus for processing vcg differential delay |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001053705A (en) * | 1999-08-09 | 2001-02-23 | Nippon Telegr & Teleph Corp <Ntt> | Transmission device |
| US7167442B2 (en) * | 2001-05-22 | 2007-01-23 | Nortel Networks Limited | Hitless protection switching |
| CN100414899C (en) * | 2002-08-05 | 2008-08-27 | 华为技术有限公司 | Treating method for great transmission delay virtual cascade virtual container image |
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- 2004-06-25 CN CNB2004100498403A patent/CN100369429C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1983887B (en) * | 2006-04-22 | 2011-09-14 | 华为技术有限公司 | Method and system for processing different time-gap number strategy |
| CN101136710B (en) * | 2006-10-25 | 2011-06-22 | 中兴通讯股份有限公司 | Data storage control method of virtual cascade recover |
| CN101621344B (en) * | 2008-06-30 | 2011-12-28 | 华为技术有限公司 | Method for determining virtual concatenation alignment out-of-limit and device for processing communication services |
| WO2010020191A1 (en) * | 2008-08-20 | 2010-02-25 | 中兴通讯股份有限公司 | Method and apparatus for improving the effect of the synchronous digital hierarchy virtual concatenation delay compensation buffer |
| RU2465731C1 (en) * | 2008-08-20 | 2012-10-27 | ЗетТиИ Корпорейшн | Method and apparatus for improving efficiency of synchronous digital hierarchy virtual concatenation delay compensation buffer |
| KR101228511B1 (en) * | 2008-08-20 | 2013-01-31 | 지티이 코포레이션 | Method and apparatus for improving the effect of the synchronous digital hierarchy virtual concatenation delay compensation buffer |
| CN101656586B (en) * | 2008-08-20 | 2013-08-07 | 中兴通讯股份有限公司 | Method and device for improving virtual concatenation delay compensation caching efficiency in synchronous digital hierarchy |
| WO2014012405A1 (en) * | 2012-07-16 | 2014-01-23 | 中兴通讯股份有限公司 | Method and apparatus for processing vcg differential delay |
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