CN1571427A - Method for decreasing operating frequency of virtual cascade restoring module - Google Patents
Method for decreasing operating frequency of virtual cascade restoring module Download PDFInfo
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- CN1571427A CN1571427A CN 200410037382 CN200410037382A CN1571427A CN 1571427 A CN1571427 A CN 1571427A CN 200410037382 CN200410037382 CN 200410037382 CN 200410037382 A CN200410037382 A CN 200410037382A CN 1571427 A CN1571427 A CN 1571427A
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Abstract
The invention relates to a method which can reduce working frequency of the virtual cascade connection resume module. The data bus frequency is reduced through changing the bit wide of the data. It includes: first, at the interface of the virtual cascade connection resume module and the SDH transaction, the byte format of the SDH data is changed into 8xN ( the N equals to two, three, four, five, and so on ) bit format, and the other corresponding indication signal is changed; second, the 8xN bit data is transmitted to the virtual cascade connection resume module; third, the 8xN bit data sent out after the disposing of the virtual cascade connection resume module is changed into 8 bit data, and the corresponding indication signal is changed. The invention can reduce the highest working frequency in the chip and the data frequency at the outer RAM interface, thus, the exploitation difficulty of the chip is reduced. Moreover, at mapping path of the two poles pointer, the high-order pointer is adjusted to low-order pointer, this can further simplify the transaction of the virtual cascade connection resume.
Description
Technical field
The present invention relates to the Digital Transmission field, specifically, relate to recovering virtual cascades method in SDH (Synchronous digitalhierarchy, the i.e. SDH (Synchronous Digital Hierarchy)) system.
Background technology
In the SDH system, for flexible networking and raising bandwidth usage efficient, the Virtual Concatenation technology has become the main method of Data transmission day by day, and its principle is to allow arbitrarily a plurality of little containers to cascade up and assemble to become a bigger container and come transmitting data service.This technology can cascade VC-11, VC-12, and the container of different rates such as VC-3, VC-4 allows very short grained bandwidth adjustment, provides than the more accurate bandwidth of Adjacent Concatenation.In addition, because the business of Virtual Concatenation is to be seen as to be a plurality of independently containers (being the container of non-cascade) in network, so can be by SDH/SONET Network Transmission traditional, that do not support Virtual Concatenation, as long as terminal equipment has the Virtual Concatenation function.The advantage of Virtual Concatenation maximum is that passage that SDH network from then on can provide suitable size to data service, avoided the waste of bandwidth.Owing to constitute VCG (Virtual Concatenation Group, be virtual cascade group) the path difference that the member walked, cause different branch that different time-delays is arranged, in order to obtain correct data, the receiving equipment in downstream must align a circuit-switched data that receives according to original rule, this process is " recovering virtual cascades ".The recovering virtual cascades ability of chip is strong more, and the time-delay between the branch road that system allowed is just big more, and the performance of system also just improves thereupon.The method that realizes recovering virtual cascades generally be will have time delay metadata cache in memory, according to the rule of alignment data are read again.Under identical processing method, the amount of capacity of memory has determined the recovering virtual cascades ability.In order to improve the recovering virtual cascades ability, generally adopt the bigger external RAM of capacity (RandomAccess Memory random access memory) data cached.
Because all branch roads of recovering virtual cascades and SDH are relevant, can't as other parts of SDH, make demultiplexing and handle, be that whole SDH handles the highest part of medium frequency; In addition, generally, external RAM often adopts BDB Bi-directional Data Bus to carry out the transmitting-receiving of data, and the clock frequency of bus will double than data.Like this, if according to existing processing method, chip will double than inter-process highest frequency clock with the clock frequency of RAM interface section again, make this part clock frequency become " bottleneck " of whole system, greatly increase the difficulty of design, checking and the rear end work of chip.
Summary of the invention
The technical problem to be solved in the present invention is that prior art exists because the recovering virtual cascades clock frequency is too high, shortcomings such as the chip design that causes, checking and rear end work difficulty are big, can reduce recovering virtual cascades module operating frequency in the hope of providing a kind of, reduce chip internal maximum operating frequency and and the data frequency of external RAM interface, thereby reduce the method for chip development difficulty.
The method of reduction recovering virtual cascades module operating frequency of the present invention is characterized in that, reduces the frequency of data/address bus by the bit wide of data transfer, specifically may further comprise the steps:
One, at recovering virtual cascades module and SDH Processing Interface place, with the SDH transformation of data of byte format be 8xN (N=2 wherein, 3,4,5 ...) and bit format, and transform other corresponding indicating signals, deliver to the recovering virtual cascades module;
1, the SDH payload data is stored according to branch road, read when taking turns to this branch road and the current data of this branch road is merged into the data of 16 bit wides next time.These 16 bit wide data are identical with frequency before the conversion, but have only one in per two such data effectively, discern this valid data by an index signal.
2 if convert 24 bit wide forms to, then in process 1 with the data of buffer memory after once once more according to the branch road storage, read when taking turns to this branch road next time, will not have buffer memory and buffer memory once, the data of twice of buffer memory merge, and obtain the data of 24 bit wides.Whether the data frequency after the conversion is preceding identical with conversion, but has only one in per three such data effectively, effective by index signal identification.
3 if convert 8xN bit wide form to, then analogizes according to process 2, by repeatedly merging behind the buffer memory, obtains the data of 8xN bit wide, identical before this data frequency and the conversion, but have only N/one data effective, discerns by index signal.
4, the memory space with memory device is divided into a plurality of logical blocks according to SDH branch road sum, with the logical block of the effective 8xN bit wide data write storage device correspondence of each bar branch road;
5, generate memory device with the clock of the former clock frequency of 1/N and read that direction enables and the address, read 8XN bit wide data, obtaining frequency is original frequency 1/N, and bit wide is former bit wide N data doubly.
5.1 read the direction frame structure with the former clock frequency generation of 1/N, this frame structure has between payload and non-payload section according to the frame head location of former SDH, guarantees that in principle the area of payload position is consistent with standard SDH frame structure area, and positive negative justification opportunity position is set; Alignment high-order pointer is arranged in the mapping path of high-order and low order two-level pointer at the same time;
5.2 between the payload section of reading the direction frame structure, increase and read the address;
5.3 by monitoring the distance between the memory device read/write address, judge whether read-out speed is consistent with writing rate, and, keep read-write speed unanimity by adjusting in the adjustment chance position of reading direction.
5.4 from the memory device logical block of branch number correspondence, read 8xN bit wide data and corresponding index signal is delivered to the recovering virtual cascades module together.
Two, the data of 8xN bit are delivered to the recovering virtual cascades resume module.
Three, the transformation of data with the 8xN bit sent after the recovering virtual cascades resume module becomes 8 Bit datas, and transforms corresponding index signal.
1, the data that the recovering virtual cascades module is sent are according to the VCG demultiplexing, and each VCG data are sent into separately processing module.
2, the 8xN Bit data is write the RAM buffer memory according to VCG, the change frequency of write address is the 1/N of original clock frequency;
3, according to the order of branch road data are read N time from RAM, get 8 effectively at every turn, the change frequency of reading the address is original clock frequency.
By the bit wide method of data transfer of the present invention, the operating frequency of recovering virtual cascades module is reduced N doubly, thereby reduce the difficulty of chip development and hardware designs; And in conversion process, the high-order pointer of the former SDH system of having alignd is convenient to the processing of recovering virtual cascades module.
Description of drawings
Fig. 1 is the method for the invention schematic flow sheet.
Fig. 2 is a 8-8xN merging process schematic diagram.
Fig. 3 reads the frame structure schematic diagram that direction generates.
Fig. 4 is the control of memory device described in the step 5 block diagram.
Fig. 5 is a 8-8xN bit width conversion process data Structure Conversion schematic diagram.
Fig. 6 is the demultiplexing schematic diagram of 8xN-8 bit width conversion.
Fig. 7 is the data structure schematic diagram in the 8xN-8 bit width conversion process.
Embodiment
Below in conjunction with accompanying drawing, the method for the invention is described in detail.
Fig. 1 is the schematic diagram that concerns of bit width conversion module and recovering virtual cascades module.Introduction of the present invention be hypographous two modules among the figure.The 8-8xN module is between SDH and recovering virtual cascades module interface, and the 8xN-8 module is between recovering virtual cascades and downstream module.
Fig. 2 is the functional block diagram of 8-8xN merging process, the data data of 8 bit wides is through obtaining data b1 behind the buffer memory for the first time, through obtaining data b2 behind the buffer memory for the second time, by obtaining data bN behind the N time buffer memory, the data of this N 8 bit wides are combined in order the data of 8xN bit wide, this data frequency is preceding identical with conversion, delivers to storage device processes shown in Figure 4.
Fig. 3 is the frame structure schematic diagram of introducing in the step 5 that direction generates of reading.Last figure is the SDH structural representation (STM-1 that constitutes with four VC-4 is an example) of standard among Fig. 5; Figure below is to read the frame structure signal that direction generates among Fig. 5, and this figure is an example to convert 16 bit wides to.Numeral time-gap number among the figure; The frame structure high-order pointer that generates is fixed, and uses the identical frame position of deciding with original SDH, can simplify the processing of downstream recovering virtual cascades module like this.Diagonal line hatches and dot-hatched are represented positive negative justification position respectively.The frame structure midrange than standard SDH structure decrease one times, the width of each row has enlarged one times, promptly the clock frequency reduces by one times, keeps the payload gross area unanimity of two frame structures in principle.The positive negative justification position that the present invention introduces can not limited by this legend at an arbitrary position.
Fig. 4 is the control block diagram of the memory device of introduction in the step 5.Step 4 produces the write address of memory device, and step 5 produces reads the direction sequential, and generates the address of reading of memory device.By read/write address relatively, do positive negative justification reading direction, make read-write speed unanimity.From the memory device sense data shown in the figure, this data frequency is former data frequency N/one, and bit wide is 8xN, delivers to the recovering virtual cascades module.
Fig. 5 is a data structure schematic diagram in the 8-8xN bit width conversion process, is converted to example with 8-16 and describes.Data represents the data of each time slot among the figure, and wherein data 0,3,6th, the data of same VC, 1,4,7th, the data of another VC; Vc_num is the VC branch number; Pre_data is the data of reading according to time slot through behind buffer memory; Data_16_t merges the 16 bit wide data that obtain to data behind the buffer memory and time slot current data, this data frequency is preceding the same with conversion, data 03 expression data most-significant byte numerical value is 0, least-significant byte numerical value is 3, and (the high low level relation that the present invention requires the data merging process to be maintained fixed gets final product, be not subjected to this example restriction), remainder data and the like; Data_16 is the 16 bit wide data that memory device is read from Fig. 4, and frequency is 1/2nd of a legacy data frequency.
Fig. 6 is the demultiplexing process schematic diagram of introducing in the step 3, opens according to the VCG branch from the 8xN bit wide data that the recovering virtual cascades module is sent, and delivers to 8xN-8 bit width conversion module separately respectively.
Fig. 7 is the data structure schematic diagram in the 8xN-8 bit width conversion process, is example with the 16-8 bit width conversion.Data_16_i is the 16 bit wide data of sending here behind the demultiplexing introduced of Fig. 6 among the figure, and these data all belong to same VCG, and this VCG has 0,1,2 three VC branch road; Data 03 expression data most-significant byte numerical value is 0 among the figure, and least-significant byte numerical value is 3 (the high low level relation that the present invention requires the data merging process to be maintained fixed gets final product, and is not subjected to this example restriction), remainder data and the like; Vc_num_16_i is corresponding VC branch number; Data_8 is the 8 bit wide data that obtain after the conversion.
Claims (8)
1, a kind of method that reduces recovering virtual cascades module operating frequency is characterized in that, reduces the frequency of data/address bus by the bit wide of data transfer, specifically may further comprise the steps:
(1) at recovering virtual cascades module and SDH Processing Interface place, be the bit format of 8 * N with the SDH transformation of data of byte format, N=2,3,4,5 ... and transform other corresponding indicating signals;
(2) data of 8 * N bit are delivered to the recovering virtual cascades resume module;
(3) transformation of data with 8 * N bit of sending after the recovering virtual cascades resume module becomes 8 Bit datas, and transforms corresponding index signal.
2, the method for reduction recovering virtual cascades module operating frequency as claimed in claim 1 is characterized in that described step (one) further may further comprise the steps:
(1) the SDH payload data is stored according to branch road, read when taking turns to this branch road and the current data of this branch road is merged into the data of 16 bit wides next time;
(2) if convert 24 bit wide forms to, then in step (1) with the data of buffer memory after once once more according to the branch road storage, read when taking turns to this branch road next time, will not have buffer memory and buffer memory once, the data of twice of buffer memory merge, and obtain the data of 24 bit wides;
(3) if convert 8 * N bit wide form to, then analogize according to step (2), by repeatedly merging behind the buffer memory, obtain the data of 8 * N bit wide;
(4) memory space with memory device is divided into a plurality of logical blocks according to SDH branch road sum, with the logical block of effective 8 * N bit wide data write storage device correspondence of each bar branch road;
(5) generate memory device with the clock of the former clock frequency of 1/N and read that direction enables and the address, read 8 * N bit wide data, obtaining frequency is original frequency 1/N, and bit wide is former bit wide N data doubly.
3, the method for reduction recovering virtual cascades module operating frequency as claimed in claim 2, it is characterized in that, 16 bit wide data in the described step (1) are identical with frequency before the conversion, but have only one in per two such data effectively, discern this valid data by an index signal.
4, the method for reduction recovering virtual cascades module operating frequency as claimed in claim 2, it is characterized in that, whether the data frequency in the described step (2) after the conversion is preceding identical with conversion, but has only one in per three such data effectively, effective by index signal identification.
5, the method for reduction recovering virtual cascades module operating frequency as claimed in claim 2 is characterized in that, the data frequency in the described step (3) after the conversion is preceding identical with conversion, but has only N/one data effective, discerns by index signal.
6, the method for reduction recovering virtual cascades module operating frequency as claimed in claim 2 is characterized in that, described step (5) further may further comprise the steps:
(5.1) read the direction frame structure with the former clock frequency generation of 1/N;
(5.2) between the payload section of reading the direction frame structure, increase and read the address;
(5.3) by monitoring the distance between the memory device read/write address, judge whether read-out speed is consistent with writing rate, and, keep read-write speed unanimity by adjusting in the adjustment chance position of reading direction;
(5.4) from the memory device logical block of branch number correspondence, read 8 * N bit wide data and corresponding index signal is delivered to the recovering virtual cascades module together.
7, the method for reduction recovering virtual cascades module operating frequency as claimed in claim 6, it is characterized in that, frame structure in the described step (5.1) is according to the frame head location of former SDH, have between payload and non-payload section, the area that guarantees payload position in principle is consistent with standard SDH frame structure area, and positive negative justification opportunity position is set; Alignment high-order pointer is arranged in the mapping path of high-order and low order two-level pointer at the same time.
8, the method for reduction recovering virtual cascades module operating frequency as claimed in claim 1 is characterized in that described step (three) further may further comprise the steps:
(1) data that the recovering virtual cascades module is sent are according to the virtual cascade group demultiplexing, and each virtual cascade group data are sent into separately processing module;
(2) 8 * N Bit data is write the RAM buffer memory according to virtual cascade group, the change frequency of write address is the 1/N of original clock frequency;
(3) according to the order of branch road data are read N time from RAM, get 8 effectively at every turn, the change frequency of reading the address is original clock frequency.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100373821A CN100417159C (en) | 2004-04-30 | 2004-04-30 | Method for decreasing operating frequency of virtual cascade restoring module |
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| CNB2004100373821A CN100417159C (en) | 2004-04-30 | 2004-04-30 | Method for decreasing operating frequency of virtual cascade restoring module |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104834483A (en) * | 2015-05-11 | 2015-08-12 | 江苏宏云技术有限公司 | Implementing method for improving property of embedded MCU (microprogrammed control unit) |
| CN105843106A (en) * | 2015-01-12 | 2016-08-10 | 深圳市中兴微电子技术有限公司 | Dedicated digital signal processor and device and method for achieving data interaction and conversion therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1248399A1 (en) * | 2001-04-02 | 2002-10-09 | Lucent Technologies Inc. | Transporting a gigabit per second datastream over a SONET/SDH network |
| CN100414899C (en) * | 2002-08-05 | 2008-08-27 | 华为技术有限公司 | Treating method for great transmission delay virtual cascade virtual container image |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105843106A (en) * | 2015-01-12 | 2016-08-10 | 深圳市中兴微电子技术有限公司 | Dedicated digital signal processor and device and method for achieving data interaction and conversion therefor |
| CN105843106B (en) * | 2015-01-12 | 2019-04-30 | 深圳市中兴微电子技术有限公司 | Dedicated digital signal processor and its device and method for realizing data interaction conversion |
| CN104834483A (en) * | 2015-05-11 | 2015-08-12 | 江苏宏云技术有限公司 | Implementing method for improving property of embedded MCU (microprogrammed control unit) |
| CN104834483B (en) * | 2015-05-11 | 2018-02-27 | 江苏宏云技术有限公司 | A kind of implementation method for lifting embedded MCU performance |
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Granted publication date: 20080903 Termination date: 20140430 |