CN1929476B - Method for realizing nondestructive virtual cascade recovery - Google Patents
Method for realizing nondestructive virtual cascade recovery Download PDFInfo
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- CN1929476B CN1929476B CN2005100983009A CN200510098300A CN1929476B CN 1929476 B CN1929476 B CN 1929476B CN 2005100983009 A CN2005100983009 A CN 2005100983009A CN 200510098300 A CN200510098300 A CN 200510098300A CN 1929476 B CN1929476 B CN 1929476B
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Abstract
This invention discloses one method to realize lossless virtual linkage recover age method, which comprises the following steps: dividing maximum number of member of RAM virtual linkage into multiple memory blocks with each for one memory block and writing each memory block according to time lag codes; according to member order and deflection indication and through inner cross RAM generation compensation RAM address reading high level; generating read direction sequence and under read out net load indicating, adding read address low level to generate compensation RAM address low level to read data from compensation RAM address.
Description
Technical field
The present invention relates to the Digital Transmission field, specifically, relate to the recovering virtual cascades method in a kind of SDH (Synchronousdigital hierarchy, SDH (Synchronous Digital Hierarchy)) system.
Background technology
In the SDH system, for flexible networking and improve bandwidth usage efficient, usually with the mode Data transmission of Virtual Concatenation.The principle of Virtual Concatenation technology is to allow arbitrarily a plurality of little containers to cascade up and assemble to become a bigger container and come transmitting data service.This technology can cascade VC-n different rates such as (n=11,12,2,3,4) container, allow very short grained bandwidth adjustment, provide than the more accurate bandwidth of Adjacent Concatenation.
Owing to constitute the path difference that the member walked of virtual concatenation group VCG (Virtual Concatenation Group), cause different members that different time-delays is arranged; In addition, cause the port data of transmitter side transmission not necessarily to send owing to add the sequencing of deletion according to the order of time-gap number, but the data of transmission course are arranged according to time-slot sequence, in order to obtain correct data, the receiving chip in downstream must align the member who receives according to original rule, the alignment preface of laying equal stress on, this process is " recovering virtual cascades "; Wherein the process of align data is called as " compensation of delay ", and the process of data rearrangement is called as " order rearrangement ".
LCAS (Link Capacity Adjustment Scheme) is a kind of agreement that can dynamically change VCG bandwidth in the transmission net based on Virtual Concatenation that proposes in the ITU-TG.7042 industry standard.It allows to adjust with no damage the link capacity of virtual concatenation signal in the transmission network, and LCAS can be implemented on the basis that has bandwidth now and dynamically increase and decrease bandwidth capacity, satisfies the variation requirement of Virtual Concatenation business.
For high-order (VC-m, m=2,3) Virtual Concatenation and low order (VC-k, k=11,12,2) Virtual Concatenation, LCAS has utilized the H4 byte of VC-m path overhead and the K4 byte transfer control frame of VC-n path overhead respectively.Comprise source to destination and place the information that is used for specific function in the control frame, can realize that by control frame LCAS the variation of source and place VCG bandwidth is synchronous to the source both direction.
The LCAS agreement has been stipulated dynamic increase VCG member, dynamically dynamically 3 kinds of operations such as adjustment of the VCG after reducing VCG member and member and losing efficacy.By webmaster increase or the deletion virtual cascade group in during the member, require not obliterated data of system, i.e. smoothly increase and decrease; For because after " disconnected fine " or reasons such as " alarms " cause the member invalid, when deleting virtual cascading member (being also referred to as " interim deletion ") automatically, can recover normal behind the obliterated data on a small quantity; The inefficacy member recover normal after, this member recovers automatically for effectively in system, requires this process can not obliterated data.
The conventional method of realizing recovering virtual cascades be will have time delay metadata cache in inside or external RAM (Random Access Memory random access memory), according to the rule of alignment data are read again.
In practical operation, following situation may occur: fault has taken place in certain of VCG or a plurality of member, deleted, and this moment, system needs to carry out the operation of other LCAS regulation, for example increased removing members temporarily.During this time, the part member's of transmitter side VCG order SQ will change, but because link failure, receiver side can not obtain fault member's true SQ from transmitter side, and that obtain is the wrong SQ or the preceding SQ of fault of process buffer memory, like this, the VCG member's that the recovering virtual cascades module receives SQ is with discontinuous or repetition arranged, if such SQ is sorted, will expend a large amount of hardware resources or processing time, cause difficulty to increase.
Present method is not all considered this special circumstances usually, in relevant processing method, the requirement that can not satisfy the LCAS agreement that has, the method of a kind of retracing sequence of introducing of the Chinese publication number 1462118 of patent " in the Virtual Concatenation sequence number ordering processing method " number for example, the method that this patent proposes requires to reset when configuration variation and intersects RAM, can cause obliterated data when configuration variation like this.The patent of the applicant's application, China's application number 200410080496.4, can solve the problem of the interpolation deletion obliterated data under the normal condition, but under special circumstances, be that VCG has had the member that the situation that all the other members are deleted in interim deletion has again taken place, still can obliterated data, the present invention has promptly proposed improvement project at this situation.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method that realizes nondestructive virtual cascade recovery, after in VCG, having the member by interim deletion, other LCAS operation takes place again, the problem of recovering virtual cascades process possibility obliterated data proposes a kind of method that can realize nondestructive virtual cascade recovery in this case.
Technical scheme of the present invention comprises:
A kind of method that realizes nondestructive virtual cascade recovery, it comprises the following steps:
A, will compensate RAM and be divided into a plurality of memory blocks according to maximum numbers of Virtual Concatenation member, corresponding one of them memory block of each member, this member's data are only deposited in pairing memory block;
B, member's data are write each self-corresponding memory block according to the order of time-gap number;
C, according to member's order and interim deletion indication, read an address high position by what internal chiasma RAM generated compensation RAM, specifically comprise:
C1, described intersection RAM generate the intersection address: the high address of intersection RAM and the maximum virtual cascade group number correspondence of system, and the greatest member of low order address and single virtual cascade group counts correspondence;
C2, with virtual cascade group numbering as high-order write address, the order of time-gap number is as the low level write address, as write control signal, the member's that temporarily do not deleted time-gap number is write described intersection RAM with effective indication with member's interim deletion indication;
C3, count according to time-slot sequence in same virtual cascade group: when the member of time-gap number minimum in the virtual cascade group occurred, this count value was reset to 0, and when counting down to the member of time-gap number maximum, this count value reaches maximum;
C4, read the address as intersecting the low level of RAM, read address reading of data from described intersection RAM as intersecting the high position of RAM with the virtual cascade group numbering with described count value;
C5, with the time-gap number read by way of compensation the high position of RAM read the address;
D, generate and to read the direction sequential, all members of same virtual cascade group to read sequential identical, and set up positive negative justification opportunity position, under the payload indication of reading direction, increase and read the address low level, what generate compensation RAM reads the address low level;
E, read address sense data from compensation RAM with the compensation RAM of above-mentioned generation.
Described method, wherein, described method also comprises: when virtual cascade group occur to increase, during one or more configuration variation in recovering of deletion, deletion temporarily or interim deletion back, do following the processing:
The write address low level of A1, the compensation RAM when record changes, this value as the border of reading direction;
B1, increase to when reading the direction border when the address low level of reading of described compensation RAM, set up free segment reading direction, be used to upgrade configuration information and this compensation RAM that resets;
C1, to keep reading the address in described free segment be currency, and it is invalid that the data of reading are set to;
D1, at the reset pairing intersection of this virtual cascade group RAM row of described free segment;
After E1, configuration information update finish, read direction and use new configuration information.
Described method, wherein, described step C4 also comprises:
Judge according to effective indication of reading whether the member is deleted temporarily, and the branch road information of temporarily being deleted is considered as invalid data.
A kind of method that realizes nondestructive virtual cascade recovery provided by the present invention, by generate the high address of compensation RAM with intersection RAM, reach the purpose of order rearrangement, the read-write of the interim deletion indication of use control intersection RAM, when configuration changes, the direction free segment is read in setting, upgrade configuration information in free segment, and the intersection RAM of this VCG correspondence that resets row, like this, not only interpolation deletion generally speaking can obliterated data, and have the member take place interim deletion simultaneously all the other members have under the situation of adding deletion also not can obliterated data, realized nondestructive virtual cascade recovery.
Description of drawings
Fig. 1 is the theory diagram of the recovering virtual cascades in the inventive method;
Fig. 2 is the schematic flow sheet of the inventive method;
Fig. 3 is the schematic diagram of the several main signals of rearrangement process in the specific embodiment of the inventive method;
Fig. 4 is the storage schematic diagram of the intersection RAM of the inventive method.
Embodiment
Below in conjunction with accompanying drawing, will be described in detail the method for the invention.
The core concept of the method for realization nondestructive virtual cascade recovery of the present invention is: adopt the mode of multiplexing process to finish Virtual Concatenation order rearrangement process, the shared RAM of data rearrangement process and compensation of delay; By the intersection RAM of chip internal, generate the intersection address; Use the read-write of the common control of deletion indication temporarily and member's enable signal to intersection RAM; VCG take place configuration variation the time, set " free segment " of reading direction, be listed as at " free segment " pairing intersections of this VCG RAM that resets.
The inventive method realizes the process that not damaged recovers in the recovering virtual cascades process after interim deletion occurring, comprise the following steps:
The first step, will compensate RAM and be divided into a plurality of memory blocks according to maximum numbers of Virtual Concatenation member, corresponding one of them memory block of each member, this member's data are only deposited in pairing memory block;
Second step, member's data are write each self-corresponding memory block according to the order of time-gap number;
The 3rd goes on foot, indicates according to member's SQ and interim deletion, generates a high position that compensates RAM by internal chiasma RAM and reads the address;
The 4th step, generate compensation RAM read the address low level: generate according to the SDH normal structure and read the direction sequential, all members of same virtual cascade group to read sequential identical, and set up positive negative justification opportunity position, under the payload indication of reading direction, increase and read the address low level;
The 5th step, read address sense data from compensate RAM with the compensation RAM of above-mentioned generation.
The inventive method is when VCG occur to increase, during one or more configuration variation in recovering of deletion, deletion temporarily or interim deletion back, can do following processing:
(1), record changes the write address low level that compensates RAM constantly, this value as the border of reading direction;
(2) the address low level of reading as compensation RAM increases to when reading the direction border, is reading to set up free segment on the direction, is used to upgrade configuration information and the RAM that resets;
(3) keeping reading the address in free segment is currency, and it is invalid that the data of reading are set to;
(4) at the reset pairing intersection of this VCG RAM row of free segment;
(5) after configuration information update finishes, read direction and use new configuration information.
The inventive method generation method that the high position of compensation RAM is read the address in above-mentioned the 3rd step specifically also comprises:
The RAM that intersects is different from an internal RAM that compensates RAM, is used for generating the intersection address.The high address of intersection RAM and the maximum virtual cascade group number correspondence of system, the greatest member of low order address and single virtual cascade group counts correspondence; Number as high-order write address with virtual cascade group, SQ is as the low level write address,, the member's that temporarily do not deleted time-gap number write with effective indication intersect RAM as write control signal with member's interim deletion indication, effectively this member of indication expression is not deleted temporarily.
Count according to time-slot sequence in same virtual cascade group: when the member of time-gap number minimum in the virtual cascade group occurred, this count value was reset to 0, and when counting down to the member of time-gap number maximum, this count value reaches maximum; Read the address with described count value as the low level of intersection RAM, read address reading of data from intersection RAM as the high position of intersection RAM with the virtual cascade group numbering; Judge according to effective indication of reading whether the member is deleted temporarily.The branch road information of temporarily being deleted is considered as invalid data, then with the time-gap number read by way of compensation the high position of RAM read the address.
Be the theory diagram of recovering virtual cascades during this is specially invented as shown in Figure 1, wherein memory device is to be used for data cached inside or external RAM, is exactly described compensation RAM.The data of writing into RAM are to treat data recovered, and the data of reading from RAM are the data of having carried out compensation of delay and order rearrangement.Write the write address that the Inbound module generates memory device, read the direction module and generate the initial value that memory device is read the low level of address and read an address high position; These two addresses also will be delivered to the read/write address comparison module simultaneously and compare, and comparative result is delivered to and read the direction generation module, adjust the speed that the address increases of reading.The high position that Cross module will be read the address is reset and is read the address low level and delivers to memory device together according to SQ.
Be that the described compensation of the method RAM low level that the present invention proposes is read the flow chart that the address generates as shown in Figure 2, the method that the present invention proposes comprises the following steps:
At first detect VCG whether one or more variations in the configuration variation such as increase, deletion, deletion temporarily or interim deletion back recovery have taken place;
Secondly, if configuration variation has taken place, record changes the write address low level that compensates RAM constantly, this value as the border of reading direction; Otherwise continue to increase low level and read the address;
Once more, judge reading the address low level and whether increasing to and read the direction border of compensation RAM, do not read address boundary, continue to increase low level and read the address if arrive.If arrived boundary position, set up free segment reading direction.
Operation below described free segment is done: 1, upgrade configuration information, after configuration information update finishes, read direction and use new configuration information in free segment; 2, the pairing intersection of the VCG RAM row that reset and change; 3, keeping reading the address in free segment is currency, and it is invalid that the data of reading are set to.Otherwise continue to increase low level and read the address.
As shown in Figure 3, be the schematic diagram of the several main signals of rearrangement process.Wherein only with six members as example, wherein time-gap number is that 0 and 2 member belongs to first VCG, all the other four members belong to second VCG; SQ represents each member's SQ value, is the foundation of resetting." interim deletion " is that the 1 corresponding member of expression is deleted temporarily, is that 0 expression is not deleted temporarily.Reset-to-zero when " arrange counting " occurs the member of the time-gap number minimum of VCG adds 1 when occurring the member of this VCG once more.Cross time-slot is from intersecting the time-gap number that RAM reads, with the high position of reading the address of RAM by way of compensation.Shown in Fig. 3 (a) table is the state of all member's operate as normal; (b) be that time-gap number is 3 the member state when deleted shown in the table; (c) table be time-gap number be 3 member by interim deletion after, time-gap number is that 1 member is deleted." * " in the form represents unconcerned content.
Being the storage schematic diagram of the intersection RAM of the inventive method as shown in Figure 4, is that the square among the figure is represented each memory cell at the signal of the intersection RAM storage mode of example among Fig. 3, an address high position and the low level of the then corresponding intersection RAM of row and column.The maximum VCG number correspondence of M wherein and system, for example system is maximum supports 24 VCG, then M should get and 24 immediate 2 integer power 32.The number of members correspondence of N and each VCG maximum possible among the figure, for example VCG has 63 members at most, and then N should get and 63 immediate 2 integer power 64.Numeral high position among the figure is effective indication of member, is that 1 expression is not deleted temporarily, and the member is effective, is that 0 expression member is invalid; Low level is represented member's time-gap number, and for example (1,2) expression time-gap number is 2, and the member is effective; The back content that resets is (0,0).According to example shown in Figure 3, time-gap number 0 and 2 member belong to and are numbered 0 VCG, the high address of depositing the position of time-gap number is 0, corresponding with the VCG numbering, the low order address of deposit position is SQ, is respectively 1,0, the data (1 among the figure in the square, 2), (1,0) be respectively the expression member effectively and member's time-gap number; Time-gap number 1,3,4,5 member belongs to and is numbered 1 VCG, and the high address of the position of depositing is 1, and the low level of deposit position is respectively 0,1,2,3, and the data 1,3,4,5 among Fig. 4 (a) in the square are exactly respectively member's time-gap number.Intersect RAM to read the address high-order identical with a write address high position, be exactly the VCG numbering under the member, it is " arrange and count " shown in Figure 3 that low level is read the address.The time-gap number of reading from intersection RAM is exactly " cross time-slot " shown in Fig. 3.(a) among Fig. 4, (b), (c) table is respectively corresponding among Fig. 3 (a), (b), (c) situation shown in the table, wherein (b), (c) among the figure because time-gap number is 3 member is deleted temporarily, so this time-gap number is not written into and intersects RAM; (b), (c) among the figure form (0,0) to occur be the result who after the configuration variation secondary series is resetted.
The inventive method is passed through such scheme, generate the high address of compensation RAM with intersection RAM, reach the purpose of order rearrangement, the read-write of the interim deletion indication of use control intersection RAM, when configuration changes, the direction free segment is read in setting, upgrade configuration information in free segment, and the intersection RAM of this VCG correspondence that resets row, like this, not only interpolation deletion generally speaking can obliterated data, and have the member take place interim deletion simultaneously all the other members have under the situation of adding deletion also not can obliterated data, realized nondestructive virtual cascade recovery.
But should be understood that above-mentioned description at specific embodiment is comparatively concrete, can not therefore think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (3)
1. method that realizes nondestructive virtual cascade recovery, it comprises the following steps:
A, will compensate RAM and be divided into a plurality of memory blocks according to maximum numbers of Virtual Concatenation member, corresponding one of them memory block of each member, this member's data are only deposited in pairing memory block;
B, member's data are write each self-corresponding memory block according to the order of time-gap number;
C, according to member's order and interim deletion indication, read an address high position by what internal chiasma RAM generated compensation RAM, specifically comprise:
C1, described intersection RAM generate the intersection address: the high address of intersection RAM and the maximum virtual cascade group number correspondence of system, and the greatest member of low order address and single virtual cascade group counts correspondence;
C2, with virtual cascade group numbering as high-order write address, the order of time-gap number is as the low level write address, as write control signal, the member's that temporarily do not deleted time-gap number is write described intersection RAM with effective indication with member's interim deletion indication;
C3, count according to time-slot sequence in same virtual cascade group: when the member of time-gap number minimum in the virtual cascade group occurred, this count value was reset to 0, and when counting down to the member of time-gap number maximum, this count value reaches maximum;
C4, read the address as intersecting the low level of RAM, read address reading of data from described intersection RAM as intersecting the high position of RAM with the virtual cascade group numbering with described count value;
C5, with the time-gap number read by way of compensation the high position of RAM read the address;
D, generate and to read the direction sequential, all members of same virtual cascade group to read sequential identical, and set up positive negative justification opportunity position, under the payload indication of reading direction, increase and read the address low level, what generate compensation RAM reads the address low level;
E, read address sense data from compensation RAM with the compensation RAM of above-mentioned generation.
2. method according to claim 1 is characterized in that, described method also comprises: when virtual cascade group occur to increase, during one or more configuration variation in recovering of deletion, deletion temporarily or interim deletion back, do following the processing:
The write address low level of A1, the compensation RAM when record changes, this value as the border of reading direction;
B1, increase to when reading the direction border when the address low level of reading of described compensation RAM, set up free segment reading direction, be used to upgrade configuration information and this compensation RAM that resets;
C1, to keep reading the address in described free segment be currency, and it is invalid that the data of reading are set to;
D1, at the reset pairing intersection of this virtual cascade group RAM row of described free segment;
After E1, configuration information update finish, read direction and use new configuration information.
3. method according to claim 2 is characterized in that, described step C4 also comprises:
Judge according to effective indication of reading whether the member is deleted temporarily, and the branch road information of temporarily being deleted is considered as invalid data.
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| CN101656586B (en) * | 2008-08-20 | 2013-08-07 | 中兴通讯股份有限公司 | Method and device for improving virtual concatenation delay compensation caching efficiency in synchronous digital hierarchy |
| CN101938320B (en) * | 2010-09-07 | 2014-11-05 | 中兴通讯股份有限公司 | Method and device for sequencing multiple virtual concatenation group members |
| CN109712268B (en) * | 2018-12-13 | 2022-01-04 | 北京遥测技术研究所 | High-speed aircraft black-barrier area data measurement processing method and processor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1134768A (en) * | 1994-08-31 | 1996-10-30 | 摩托罗拉公司 | A method and apparatus for packet alignment in a communication system |
| CN1462118A (en) * | 2002-05-27 | 2003-12-17 | 华为技术有限公司 | Treatment method of sequence number ordering in virtual cascade connection |
| CN1474559A (en) * | 2002-08-05 | 2004-02-11 | 华为技术有限公司 | Treating method for great transmission delay virtual cascade virtual container image |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1134768A (en) * | 1994-08-31 | 1996-10-30 | 摩托罗拉公司 | A method and apparatus for packet alignment in a communication system |
| CN1462118A (en) * | 2002-05-27 | 2003-12-17 | 华为技术有限公司 | Treatment method of sequence number ordering in virtual cascade connection |
| CN1474559A (en) * | 2002-08-05 | 2004-02-11 | 华为技术有限公司 | Treating method for great transmission delay virtual cascade virtual container image |
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