CN1941333A - Chip packing structure - Google Patents
Chip packing structure Download PDFInfo
- Publication number
- CN1941333A CN1941333A CNA200510105922XA CN200510105922A CN1941333A CN 1941333 A CN1941333 A CN 1941333A CN A200510105922X A CNA200510105922X A CN A200510105922XA CN 200510105922 A CN200510105922 A CN 200510105922A CN 1941333 A CN1941333 A CN 1941333A
- Authority
- CN
- China
- Prior art keywords
- chip
- packaging structure
- active surface
- carrier
- excessive glue
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention is concerned with the CMOS chip sealing structure, including: the CMOS chip, the carrier, several welding line and the sealing colloid; the CMOS chip is with the initiative surface, the back surface related with the initiative surface, several over-colloid protecting surfaces located between the initiative surface and the sidewalls; the carrier connects with the back surface of the CMOS chip in order to loading the CMOS chip; the welding line electric connects with the carrier; the sealing colloid sets on the carrier, and covers the welding lines, the part area of the initiative surface, the sidewalls, and at least part area of the over-colloid protecting surfaces. The invention is: the over-colloid protecting surfaces can avoid the sealing colloid to pollute the initiative surface.
Description
Technical field
The present invention relates to a kind of chip-packaging structure, and be particularly related to a kind of chip-packaging structure that excessive glue prevents the surface that has.
Background technology
In semiconductor industry, (Integrated Circuits, production IC) mainly are divided into three phases to integrated circuit: the making of the manufacturing of wafer (Wafer), integrated circuit (IC) and the encapsulation (Package) of integrated circuit etc.Wherein, bare chip is finished by steps such as wafer fabrication, circuit design, photo etched mask making and cut crystals, and each cuts formed bare chip by wafer, by the contact on the bare chip with after external signal is electrically connected, can with adhesive material bare chip be coated again.The purpose of its encapsulation is to prevent that bare chip is subjected to moisture, heat, The noise, and the media that is electrically connected between bare chip and the external circuit is provided, and so promptly finishes the encapsulation step of integrated circuit.
Please refer to Fig. 1, it is the schematic perspective view of known a kind of chip-packaging structure.Known chip-packaging structure 100 comprises chip 110, substrate 120, many bonding wires 130 and packing colloid 140.Wherein, chip 110 have active surface 112, with active surface 112 opposing backside surface 114 and a plurality of sidewall 116.In addition, substrate 120 is connected with the back side 114 of chip 110, and in order to carries chips 110, these bonding wires 130 then make chip 110 and substrate 120 be electrically connected to each other.In addition, packing colloid 140 is arranged on the substrate 120, and packing colloid 140 coats the subregion and the sidewall 116 of bonding wire 130, active surface 112.
Please refer to Fig. 2, its for the chip-packaging structure of Fig. 1 in the generalized section of carrying out sealing adhesive process.Yet, known chip-packaging structure 100 is in sealing (Mold) technology, because dies with epoxy compound M makes so with the corresponding profile of chip 110, therefore when the packing colloid 140 of half melting is injected among the dies with epoxy compound M, on the active surface 112 of chip 110, form the active surface 112 (also visible Fig. 1) that overflows the glue phenomenon and pollute chip 110 easily.From the above, known chip-packaging structure 100 has improved necessity in fact.
Summary of the invention
In view of the foregoing, purpose of the present invention just provides a kind of chip-packaging structure, and it has excessive glue and prevents that the surface is to avoid packing colloid to produce the phenomenon of excessive glue pollution on the active surface of chip.
Based on above-mentioned purpose, the present invention proposes a kind of chip-packaging structure, comprises chip, carrier, many bonding wires and packing colloid.Wherein, chip have active surface, and active surface opposing backside surface, a plurality of sidewall and a plurality of excessive glue between active surface and these sidewalls prevent the surface.In addition, carrier is connected with the back side of chip, and with carries chips, and these bonding wires are electrically connected chip and carrier.In addition, packing colloid is arranged on the carrier, and wherein the packing colloid subregion, these sidewalls and these the excessive glue that coat these bonding wires, active surface prevents the subregion at least on surface.
Described according to preferred embodiment of the present invention, said chip for example comprises charge coupled cell, cmos image sensor, fingerprint identifier or optical diode.
Described according to preferred embodiment of the present invention, for active surface, above-mentioned excessive glue prevents that the surface from for example being the inclined-plane.
Described according to preferred embodiment of the present invention, above-mentioned excessive glue prevents that the surface from for example comprising first surface and second surface, and wherein first surface is connected with active surface, and second surface is connected between first surface and these sidewalls.In addition, first surface is approximately vertical with active surface, and second surface is approximately parallel with active surface.
Chip-packaging structure of the present invention can pass through the particular design of wafer cutting tool owing to the glue that overflows prevents the surface, and is formed in the technology of wafer cutting, therefore need not increase any processing step.In addition, because chip-packaging structure prevents the design on surface by the glue that overflows, can effectively improve the excessive glue pollution phenomenon on the active surface of chip.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the schematic perspective view of known a kind of chip-packaging structure.
Fig. 2 for the chip-packaging structure of Fig. 1 in the generalized section of carrying out sealing adhesive process.
Fig. 3 is the schematic perspective view of the chip-packaging structure of first embodiment of the invention.
Fig. 4 A to Fig. 4 B for the chip-packaging structure of Fig. 2 in the generalized section of carrying out the wafer cutting technique.
Fig. 5 for the chip-packaging structure of Fig. 2 in the generalized section of carrying out sealing adhesive process.
Fig. 6 is the generalized section of the chip-packaging structure of second embodiment of the invention.
Fig. 7 A to Fig. 7 B for the chip-packaging structure of Fig. 6 in the generalized section of carrying out the wafer cutting technique.
The main element description of symbols
100: known chip-packaging structure
110,210,310: chip
112,212,312: active surface
114,214: the back side
116,216,316: sidewall
120: substrate
130,230: bonding wire
140,240: packing colloid
200,300: chip-packaging structure of the present invention
218,318: excessive glue prevents the surface
220: carrier
318a: first surface
318b: second surface
W: wafer
B, B ': cutting tool
M: dies with epoxy compound
Embodiment
First embodiment
Please refer to Fig. 3, it is the schematic perspective view of the chip-packaging structure of first embodiment of the invention.The chip-packaging structure 200 of present embodiment comprises chip 210, carrier 220, many bonding wires 230 and packing colloid 240.Wherein, chip 210 has active surface 212, prevents surface 218 with active surface 212 opposing backside surface 214, a plurality of sidewall 216 and a plurality of excessive glue.These excessive glue prevent that surface 218 is between active surface 212 and these sidewalls 216.In addition, carrier 220 is connected with the back side 214 of chip 210, and in order to carries chips 210, these bonding wires 230 then make chip 210 and carrier 220 be electrically connected to each other.In addition, packing colloid 240 is arranged on the carrier 220, and the scope that packing colloid 240 coats comprises that subregion, these sidewalls 216 and the excessive glue of these bonding wires 230, active surface 212 prevent the subregion at least on surface 218.
Below elaborate for the wafer cutting technique and the sealing adhesive process of the chip-packaging structure 200 of present embodiment.Please refer to Fig. 4 A to Fig. 4 B, its for the chip-packaging structure of Fig. 2 in the generalized section of carrying out the wafer cutting technique.After slices being had the wafer W payment encapsulation factory of a plurality of chips when wafer factory, semi-conductive last part technology will be responsible for processing by encapsulation factory.At first, encapsulation factory must be with a plurality of chips 210 cutting and separating on the wafer W, and this is wafer cutting (Wafer Saw) technology.Prevent surface 218 in order to cut out the above-mentioned excessive glue that is rendered as the inclined-plane, must be by special cutting tool B in the technology of cut crystal W, isolate a plurality of chips 210 and cutting and form as the excessive glue as the inclined-plane and prevent surperficial 218.
Second embodiment
Please refer to Fig. 6, it is the generalized section of the chip-packaging structure of second embodiment of the invention.Second embodiment and first embodiment different be in, the excessive glue that chip 310 had among second embodiment prevents that surface 318 is for stepped.As shown in Figure 6, excessive glue prevents that surface 318 from for example comprising first surface 318a and second surface 318b, and first surface 318a is connected with active surface 312, and second surface 318b then is connected between first surface 318a and these sidewalls 316.In addition, first surface 318a is approximately vertical with active surface 312, and second surface 318b is approximately parallel with active surface 312.
Please refer to Fig. 7 A to Fig. 7 B, its for the chip-packaging structure of Fig. 6 in the generalized section of carrying out the wafer cutting technique.When the chip-packaging structure 300 of second embodiment when carrying out the cutting technique of wafer W, the external form of cutting tool B ' also has corresponding change, prevents surface 318 to cut out above-mentioned stair-stepping excessive glue.In this mandatory declaration be, only glue prevents surface 318 functions of avoiding the excessive glue pollution on the active surface 312 that are designed otherwise influence is overflow, excessive glue prevents that the surface 318 ladder numbers that presented and profile from all can do corresponding change according to design requirement, therefore present embodiment is not in order to limit the present invention only in order to illustrate.It is described then to be same as first embodiment as for the sealing adhesive process of second embodiment, so no longer repeat in this.
In sum, chip-packaging structure of the present invention has following advantage:
One, excessive glue prevents that the surface from can form, and need not increase any processing step by the particular design of wafer cutting tool in the technology of wafer cutting;
Two, chip-packaging structure prevents the design on surface by the glue that overflows, and can effectively improve the excessive glue pollution phenomenon of active surface in sealing adhesive process of chip.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (5)
1. chip-packaging structure is characterized in that comprising:
Chip, this chip have active surface, and this active surface opposing backside surface, a plurality of sidewall and a plurality of excessive glue between this active surface and above-mentioned these sidewalls prevent the surface;
Carrier is connected with this back side of this chip, to carry this chip;
Many bonding wires are electrically connected this chip and this carrier; And
Packing colloid is arranged on this carrier, and wherein this packing colloid coats the subregion at least that above-mentioned these bonding wires, the subregion of this active surface, above-mentioned these sidewalls and above-mentioned these excessive glue prevent the surface.
2. chip-packaging structure according to claim 1 is characterized in that this chip comprises charge coupled cell, cmos image sensor, fingerprint identifier or optical diode.
3. chip-packaging structure according to claim 1 is characterized in that for this active surface, and this excessive glue prevents that the surface from being the inclined-plane.
4. chip-packaging structure according to claim 1, it is characterized in that this excessive glue prevents that the surface from comprising first surface and second surface, wherein this first surface is connected with this active surface, and this second surface is connected between this first surface and above-mentioned these sidewalls.
5. chip-packaging structure according to claim 4 it is characterized in that this first surface is vertical with this active surface, and this second surface is parallel with this active surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB200510105922XA CN100444361C (en) | 2005-09-30 | 2005-09-30 | Chip packing structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CNB200510105922XA CN100444361C (en) | 2005-09-30 | 2005-09-30 | Chip packing structure |
Publications (2)
Publication Number | Publication Date |
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CN1941333A true CN1941333A (en) | 2007-04-04 |
CN100444361C CN100444361C (en) | 2008-12-17 |
Family
ID=37959326
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CNB200510105922XA Expired - Fee Related CN100444361C (en) | 2005-09-30 | 2005-09-30 | Chip packing structure |
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CN (1) | CN100444361C (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111090185A (en) * | 2019-12-24 | 2020-05-01 | 豪威半导体(上海)有限责任公司 | Dispensing method |
CN112897451A (en) * | 2021-01-19 | 2021-06-04 | 潍坊歌尔微电子有限公司 | Sensor packaging structure, manufacturing method thereof and electronic equipment |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100292033B1 (en) * | 1998-05-13 | 2001-07-12 | 윤종용 | Semiconductor chip package and method for manufacturing same |
CN1171311C (en) * | 2000-11-17 | 2004-10-13 | 矽品精密工业股份有限公司 | Semiconductor package whose conductor possesses concave portion |
CN1157781C (en) * | 2000-12-14 | 2004-07-14 | 胜开科技股份有限公司 | IC package structure and its manufacture |
-
2005
- 2005-09-30 CN CNB200510105922XA patent/CN100444361C/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111090185A (en) * | 2019-12-24 | 2020-05-01 | 豪威半导体(上海)有限责任公司 | Dispensing method |
CN112897451A (en) * | 2021-01-19 | 2021-06-04 | 潍坊歌尔微电子有限公司 | Sensor packaging structure, manufacturing method thereof and electronic equipment |
CN112897451B (en) * | 2021-01-19 | 2023-12-22 | 潍坊歌尔微电子有限公司 | Sensor packaging structure, manufacturing method thereof and electronic equipment |
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Publication number | Publication date |
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CN100444361C (en) | 2008-12-17 |
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