CN1909707A - TD-SCDMA shrouding system and its time slot power reading method - Google Patents
TD-SCDMA shrouding system and its time slot power reading method Download PDFInfo
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Abstract
The invention relates to a method for reading the time slit power of TD-SCDMA cover system, which comprises: a, checking the radio signal on the needed point of ascending and descending chains, to obtain the envelope check signal that represent the intensity of power; b, obtaining the time slit switch point information of ascending and descending signals from the detecting host; c, combining the frame synchronous instruct signal and the time slit switch point information to generate time slit instruction signal; d, based on the time slit instruction signal, outputting relative control information to sample each envelope signal, to obtain the power sample value of each time slit of each checking point, and reporting the power sample value to the host. In addition, the invention also provides a relative TD-SCDMA cover system. Compared with traditional technique, the invention can make the cover system obtain the time slit accuracy power of each position inside the system.
Description
[technical field]
The present invention relates to mobile communication covering system field, relate in particular to a kind of TD-SCDMA covering system and time slot power reading method thereof.
[technical background]
When application TD-SCDMA system carries out networking; also can run into the communication blind district problem; because in the communication process of signal; run into obstacle through regular meeting; as building, mountain range, various complex-terrains etc.; at the back side of obstacle and the inside of various underground structures, in market place builet below the ground, subway, tunnel, because signal can not cover the generation communication blind district.Direct discharging station has the low and characteristics in increase coverage territory rapidly of cost of investment, becomes an indispensable part in radio network optimization and covering.Direct discharging station is divided into outdoor repeater and indoor repeater.When building the indoor or outdoors covering system, only use the repeater also to be difficult to solve the extensive requirement that covers, need to be used trunk amplifier sometimes.
When covering system is carried out remote monitoring,, require covering system that the input and output power read functions of uplink and downlink link can be provided owing to need to understand the operational environment of covering system and the operating state of covering system itself.Traditional frequency division multiplexing covering system, as GSM, CDMA, WCDMA repeater, the input and output power that carries out the uplink and downlink link all is to use detecting circuit to obtain the rectified signal of radiofrequency signal at corresponding point when reading, because rectified signal level amplitude has characterized the power level of signal, re-use MCU corresponding rectified signal is carried out the A/D sampling, can obtain the performance number of each point of covering system.
The TD-SCDMA signal has time-multiplexed characteristics, and each TD-SCDMA radio frames can be the subframe of two 5ms of branch, and the structure of two subframes is identical.Single subframe is made up of the conventional time slot (representing with TS0 to TS6) of seven equal length and three kinds of special time slots (DwPTS, GP and UpPTS), and each subframe has two transfer points, and up-downgoing can be asymmetric.As everyone knows, the TS0 time slot of the subframe of TD-SCDMA and DwPTS (descending synchronous code) time slot often have, and to make things convenient for terminal use's access, wherein DwPTS (descending synchronous code) time slot is a firm power.Other time slot just has burst when customer service is arranged, the number of users difference of access, and the level range value difference of rectified signal has characterized different power, and at the time slot that does not have the user to insert, its power is characterized by noise power.Owing to do not distinguish corresponding time slot, power read so can't carry out accurately, thereby can't obtain the input and output power of uplink and downlink link accurately when the power of traditional covering system read technology and is applied in the TD-SCDMA covering system.
[summary of the invention]
Purpose of the present invention will overcome above-mentioned deficiency exactly, and a kind of TD-SCDMA covering system time slot power reading method that can realize correctly reading the power of its time slot in covering systems such as TD-SCDMA repeater, trunk amplifier is provided.
Another object of the present invention is to provide a kind of TD-SCDMA covering system of using above-mentioned time slot power reading method.
First purpose of the present invention is achieved by the following technical solution:
TD-SCDMA covering system time slot power reading method of the present invention comprises the steps:
On a, the point that in the uplink and downlink link, needs to detect radiofrequency signal is carried out detection, obtain to have characterized the envelope detection signal of power level;
B, obtain the time slot switching point information of uplink and downlink signal from monitoring host computer;
C, produce time slit instruction signal in conjunction with frame synchronization index signal and uplink and downlink time slot switching point information;
D, each envelope detection signal is sampled, obtain each time slot power sampled value of each test point, and the power samples value is reported to monitoring host computer for further use according to time slit instruction signal output corresponding control information.
Among the described step a, obtain the TD-SCDMA signal by the coupler coupling earlier, export independently hardware detecting circuit realization obtaining again to the envelope detection signal.
Perhaps in described step a, obtain the TD-SCDMA signal by the coupler coupling earlier, export the detecting circuit that is built in the uplink and downlink amplifying circuit again to, realize obtaining the envelope detection signal.
Another object of the present invention is by the application said method, is achieved through the following technical solutions:
TD-SCDMA covering system of the present invention comprises near-end built-up circuit, descending amplifying circuit, up amplifying circuit, far-end built-up circuit, synchronization module and monitoring host computer;
Described near-end built-up circuit, descending amplifying circuit, far-end built-up circuit electrically connect the formation down link successively; The downstream signal that descending amplifying circuit comes near-end built-up circuit transmission amplifies after the far-end built-up circuit transfers to far-end covers;
Described far-end built-up circuit, up amplifying circuit, near-end built-up circuit electrically connect the formation up link successively; Up amplifying circuit will carry out power amplification after the near-end built-up circuit transfers to the base station through the upward signal that the transmission of far-end built-up circuit comes;
Described synchronization module obtains downstream signal by a coupler, and produces synchronizing signal, this signal is transferred in the uplink and downlink link realize Synchronization Control;
Monitoring host computer is monitored the various parameters of TD-SCDMA covering system by wired or wireless mode, can the time slot switching point be set by it;
In addition, also comprise at least one coupler and at least one envelope detection circuit, an and time slot power read module, described coupler is connected on the point that needs in the uplink and downlink link to connect, envelope detection circuit is connected with the time slot power read module with coupler respectively, and the time slot power read module then is connected with monitoring host computer;
Coupler detection radiofrequency signal exports envelope detection circuit then to and carries out detection, obtains to have characterized the envelope detection signal of power level; The time slot power read module obtains the time slot switching point information of uplink and downlink signal from monitoring host computer, and frame synchronization index signal and the uplink and downlink time slot switching point information in conjunction with the synchronization module input produces time slit instruction signal then; According to time slit instruction signal output corresponding control information the envelope detection signal is sampled at last, obtain the power samples value of each time slot, and the power samples value is reported to monitoring host computer for further using.
Particularly, described time slot power read module comprises that the MCU submodule, MCU Control on Communication submodule, the time slit instruction signal that electrically connect in turn produce submodule, ADC controlling of sampling submodule and power samples ADC submodule, in addition, described time slit instruction signal produces submodule and also is responsible for being connected with described synchronization module, ADC controlling of sampling module also is connected with MCU Control on Communication submodule, and power samples ADC module then also is responsible for being connected with envelope detection circuit;
The MCU submodule in order to communicating by letter with described monitoring host computer, obtains the time slot switching point information of uplink and downlink signal from monitoring host computer, and reports the power samples value to monitoring host computer;
MCU Control on Communication submodule, in order to receive data that the MCU submodule transmits by data/address bus and this data forwarding to connected time slit instruction signal is produced submodule, also be responsible for simultaneously the power samples value that the transmission of ADC controlling of sampling module comes is uploaded to the MCU submodule;
Time slit instruction signal produces submodule, and the frame synchronization index signal and the uplink and downlink time slot switching point information that are obtained in order to combination produce time slit instruction signal, and transfer to described ADC controlling of sampling submodule;
ADC controlling of sampling submodule, in order to according to the time slit instruction signal output control signal corresponding of input to power samples ADC submodule, and the power samples value that power samples ADC submodule is passed back transferred to described MCU Control on Communication submodule;
Power samples ADC submodule, in order to accept from the rectified signal of envelope detection circuit and from the control signal of ADC controlling of sampling submodule, and the envelope detection signal is carried out power samples based on this control signal, then the power samples value is transferred to described ADC controlling of sampling submodule.
Described MCU Control on Communication submodule, time slit instruction signal produce submodule and ADC controlling of sampling submodule is integrated in the same control chip, and control chip can be among FPGA, CPLD, the EPLD any one.
Described coupler and envelope detection circuit system in like manner, also can be built in the described uplink and downlink amplifying circuit by independently hardware circuit realization.
Described up amplifying circuit, descending amplifying circuit all can be may one of make up arbitrarily in low noise amplifier, frequency selection circuit, the power amplifier.
Compared with prior art, the present invention possesses following advantage: solved tradition and read the problem that technology is unsuitable for the TD-SCDMA covering system, by adopting the method that is suitable for mutually with the sub-frame formats of TD-SCDMA, make the TD-SCDMA covering system can accurately know the time slot power of each position of internal system.
[description of drawings]
Fig. 1 is a TD-SCDMA covering system principle schematic of the present invention;
Fig. 2 is the principle schematic of time slot power read module of the present invention.
[embodiment]
The present invention is further illustrated below in conjunction with drawings and Examples:
As everyone knows, when the TD-SCDMA covering system is worked, by coupler and envelope detection circuit the radiofrequency signal of covering system is carried out detection and can obtain the envelope detection signal, and the level amplitude of rectified signal has characterized the power level of signal.
Based on the above-mentioned rectified signal that characterizes signal power strength, design according to following thinking among the present invention: the TD-SCDMA covering system uses synchronization module to obtain the frame synchronization index signal, and exports the time slot power read module to.The TD-SCDMA covering system uses the time slot power read module to finish the time slot power read functions, this module produces the initial moment that index signal is indicated each time slot according to the frame synchronization index signal of input and the uplink and downlink time slot switching point position that obtains by communicating by letter with monitoring host computer, use power samples ADC submodule that the rectified signal of a plurality of inputs is sampled respectively to be controlled at each corresponding time slot, obtained the power of each time slot of each rectified signal.The time slot power read module is communicated by letter with monitoring host computer by a MCU submodule, and monitoring host computer can be provided with the time slot switching point of TD-SCDMA signal, and the time slot power that the power read module is obtained reads simultaneously.
See also Fig. 1, based on above-mentioned mentality of designing, the present invention now discloses a kind of TD-SCDMA covering system, comprises near-end built-up circuit 11, descending amplifying circuit 21, up amplifying circuit 22, far-end built-up circuit 12, synchronization module 4 and monitoring host computer (not shown).
Described near-end built-up circuit 11, descending amplifying circuit 21, far-end built-up circuit 12 electrically connect successively and constitute down link; The downstream signal that descending amplifying circuit 21 comes near-end built-up circuit 11 transmission amplifies after far-end built-up circuit 12 transfers to far-end MT covers.
Described far-end built-up circuit 12, up amplifying circuit 22, near-end built-up circuit 11 electrically connect successively and constitute up link; Up amplifying circuit 22 will carry out power amplification after near-end built-up circuit 12 transfers to the base station at near-end DT through the upward signal that 12 transmission of far-end built-up circuit come.
Described up amplifying circuit 21, descending amplifying circuit 22 all can be may one of make up arbitrarily in low noise amplifier, frequency selection circuit, the power amplifier, select according to the actual needs of covering system.
Described synchronization module 4 obtains downstream signal by a coupler 31, and generation synchronizing signal, this signal is transferred in the uplink and downlink link, utilize different time-gap to switch the different on off operating mode of uplink and downlink link, realization is to the Synchronization Control of whole TD-SCDMA covering system, this is a known technology, pardons not all right giving unnecessary details.
Monitoring host computer is (not shown, down together), monitor the various parameters of TD-SCDMA covering system by wired or wireless mode, can the time slot switching point be set by it, in known a kind of mode, monitoring host computer is being connected by wired or wireless modulator-demodulator (being MODEM, not shown) realization and covering system generally.
In addition, also comprise coupler 31,33,35 and envelope detection circuit 32,34,36, and a time slot power read module 5.Described coupler 31,33,35 is connected on the point that needs the detection power sampled value in the uplink and downlink link, also can with described synchronization module 4 shared same couplers 31, the point of concrete detection power sampled value optionally and deciding.Envelope detection circuit 32,34,36 are connected between described coupler 31 and the time slot power read module 5, and 5 of time slot power read modules are connected with monitoring host computer.Wherein, coupler 33,35 and envelope detection circuit 34,36 are by independently hardware circuit realization (referring to Fig. 1), in like manner, also can be built in the described uplink and downlink amplifying circuit 21,22 because of actual needs.
During work, coupler 31,33,35 detect radiofrequency signal exports envelope detection circuit 32,34 then respectively to, and 36 carry out detection, obtain to have characterized the envelope detection signal of power level; Time slot power read module 5 obtains the time slot switching point information of uplink and downlink signal from monitoring host computer, and frame synchronization index signal and the uplink and downlink time slot switching point information in conjunction with synchronization module 4 inputs produces time slit instruction signal then; According to time slit instruction signal output corresponding control information the envelope detection signal is sampled at last, obtain the power samples value of each time slot, and the power samples value is reported to monitoring host computer for further using.
Particularly, described time slot power read module 5 comprises that the MCU submodule 51, MCU Control on Communication submodule 52, the time slit instruction signal that electrically connect in turn produce submodule 53, ADC controlling of sampling submodule 54 and power samples ADC submodule 55, in addition, described time slit instruction signal produces submodule 53 and also is responsible for being connected with described synchronization module 4, ADC controlling of sampling module 54 also is connected with MCU Control on Communication submodule 52,55 of power samples ADC modules also are responsible for and envelope detection circuit 32,34,36 connect;
MCU Control on Communication submodule 52, in order to receive data that MCU submodule 51 transmits by data/address bus and this data forwarding to connected time slit instruction signal is produced submodule 53, also be responsible for simultaneously the power samples value that 54 transmission of ADC controlling of sampling module come is uploaded to MCU submodule 51;
Time slit instruction signal produces submodule 53, and the frame synchronization index signal and the uplink and downlink time slot switching point information that are obtained in order to combination produce time slit instruction signal, and transfer to described ADC controlling of sampling submodule 54;
ADC controlling of sampling submodule 54, in order to according to the time slit instruction signal output control signal corresponding of input to power samples ADC submodule 55, and the power samples value that power samples ADC submodule 55 is passed back transferred to described MCU Control on Communication submodule 52;
Power samples ADC submodule 55, in order to accept from envelope detection circuit 32,34,36 rectified signal reaches the control signal from ADC controlling of sampling submodule 54, and the envelope detection signal is carried out power samples based on this control signal, then the power samples value is transferred to described ADC controlling of sampling submodule 54.
Described MCU Control on Communication submodule 52, time slit instruction signal produce submodule 53 and ADC controlling of sampling submodule 54 is integrated in the same control chip 50, and control chip 50 can be among FPGA, CPLD, the EPLD any one.
In conjunction with the internal structure of above-mentioned TD-SCDMA covering system, the present invention follows the function that following method realizes that it is existing, and is specific as follows:
On a, a plurality of points in the uplink and downlink link, comprise near-end DT one place, each place of uplink and downlink link, utilize three envelope detected circuit 32,34,36 detect three couplers 31,33 of three routes respectively, the radiofrequency signal that 35 couplings obtain is carried out detection then, obtains to have characterized the envelope detection signal of power level;
B, the MCU submodule 51 by time slot power read module 5 obtain the time slot switching point information of uplink and downlink signal and further transfer to the MCU Control on Communication submodule 52 from monitoring host computer, are forwarded to time slit instruction signal again by this MCU communication letter submodule 52 and produce submodule 53;
C, in time slit instruction signal produces submodule 53, have two kinds of extraneous signals, one is the frame synchronization index signal that synchronization module 4 transmission come, another then is the uplink and downlink time slot switching point information that 52 transmission of MCU Control on Communication submodule come, time slit instruction signal produces submodule 53 and produces time slit instruction signal in conjunction with described frame synchronization index signal and uplink and downlink time slot switching point information, and transfers to ADC controlling of sampling submodule 54;
D, ADC controlling of sampling submodule 54 are according to time slit instruction signal output corresponding control information, 55 pairs of envelope detection signals of power controlling sampling ADC submodule are sampled, obtain the power samples value of each time slot, and the power samples value reported to monitoring host computer for further use by described MCU Control on Communication submodule 52, monitoring host computer will be finished various functions according to this power samples value.
The present invention is applicable in the TD-SCDMA covering systems such as wireless discharging-directly station, optical fiber repeater, electric light mixing repeater, tower amplifier and trunk amplifier.Utilize time slot power of the present invention to read technology, solved that original power reads inaccurate problem in the system, reached the purpose that the uplink and downlink input and output power of covering system is realized monitoring.
The present invention is described in narrative mode all the time, and wherein employed term is intended to describe and unrestricted.According to above description, can make many further modifications to the present invention, also can do many variations according to actual needs.Therefore, in additional claim scope, the present invention can adopt various implementation to specifically described embodiment.
Claims (10)
1, a kind of TD-SCDMA covering system time slot power reading method is characterized in that comprising the steps:
On a, the point that in the uplink and downlink link, needs to detect radiofrequency signal is carried out detection, obtain to have characterized the envelope detection signal of power level;
B, obtain the time slot switching point information of uplink and downlink signal from monitoring host computer;
C, produce time slit instruction signal in conjunction with frame synchronization index signal and uplink and downlink time slot switching point information;
D, each envelope detection signal is sampled, obtain the power samples value of each time slot of each test point, and the power samples value is reported to monitoring host computer for further use according to time slit instruction signal output corresponding control information.
2, TD-SCDMA covering system time slot power reading method according to claim 1 is characterized in that among the step a, obtains the TD-SCDMA signal by the coupler coupling earlier, exports independently hardware detecting circuit realization obtaining the envelope detection signal again to.
3, TD-SCDMA covering system time slot power reading method according to claim 1, it is characterized in that among the step a, obtain the TD-SCDMA signal by the coupler coupling earlier, export the detecting circuit that is built in the uplink and downlink amplifying circuit again to, realize obtaining the envelope detection signal.
4, a kind of TD-SCDMA covering system comprises near-end built-up circuit, descending amplifying circuit, up amplifying circuit, far-end built-up circuit, synchronization module and monitoring host computer;
Described near-end built-up circuit, descending amplifying circuit, far-end built-up circuit electrically connect the formation down link successively; The downstream signal that descending amplifying circuit comes near-end built-up circuit transmission amplifies after the far-end built-up circuit transfers to far-end covers;
Described far-end built-up circuit, up amplifying circuit, near-end built-up circuit electrically connect the formation up link successively; Up amplifying circuit will carry out power amplification after the near-end built-up circuit transfers to the base station through the upward signal that the transmission of far-end built-up circuit comes;
Described synchronization module obtains downstream signal by a coupler, and produces synchronizing signal, this signal is transferred in the uplink and downlink link realize Synchronization Control;
Monitoring host computer is monitored the various parameters of TD-SCDMA covering system by wired or wireless mode, can the time slot switching point be set by it;
It is characterized in that:
Also comprise at least one coupler and at least one envelope detection circuit, an and time slot power read module, described coupler is connected on the point that needs in the uplink and downlink link to connect, envelope detection circuit is connected with the time slot power read module with coupler respectively, and the time slot power read module then is connected with monitoring host computer;
Coupler coupling radiofrequency signal exports envelope detection circuit then to and carries out detection, obtains to have characterized the envelope detection signal of power level; The time slot power read module obtains the time slot switching point information of uplink and downlink signal from monitoring host computer, and frame synchronization index signal and the uplink and downlink time slot switching point information in conjunction with the synchronization module input produces time slit instruction signal then; According to time slit instruction signal output corresponding control information the envelope detection signal is sampled at last, obtain the time slot power sampled value of each test point, and the power samples value is reported to monitoring host computer for further using.
5, TD-SCDMA covering system according to claim 4 is characterized in that:
Described time slot power read module comprises that the MCU submodule, MCU Control on Communication submodule, the time slit instruction signal that electrically connect in turn produce submodule, ADC controlling of sampling submodule and power samples ADC submodule, in addition, described time slit instruction signal produces submodule and also is responsible for being connected with described synchronization module, ADC controlling of sampling module also is connected with MCU Control on Communication submodule, and power samples ADC module then also is responsible for being connected with envelope detection circuit;
The MCU submodule in order to communicating by letter with described monitoring host computer, obtains the time slot switching point information of uplink and downlink signal from monitoring host computer, and reports the power samples value to monitoring host computer;
MCU Control on Communication submodule, in order to receive data that the MCU submodule transmits by data/address bus and this data forwarding to connected time slit instruction signal is produced submodule, also be responsible for simultaneously the power samples value that the transmission of ADC controlling of sampling module comes is uploaded to the MCU submodule;
Time slit instruction signal produces submodule, and the frame synchronization index signal and the uplink and downlink time slot switching point information that are obtained in order to combination produce time slit instruction signal, and transfer to described ADC controlling of sampling submodule;
ADC controlling of sampling submodule, in order to according to the time slit instruction signal output control signal corresponding of input to power samples ADC submodule, and the power samples value that power samples ADC submodule is passed back transferred to described MCU Control on Communication submodule;
Power samples ADC submodule, in order to accept from the rectified signal of envelope detection circuit and from the control signal of ADC controlling of sampling submodule, and the envelope detection signal is carried out power samples based on this control signal, then the power samples value is transferred to described ADC controlling of sampling submodule.
6, TD-SCDMA covering system according to claim 5 is characterized in that: described MCU Control on Communication submodule, time slit instruction signal produce submodule and ADC controlling of sampling submodule is integrated in the same control chip.
7, TD-SCDMA covering system according to claim 6 is characterized in that: described control chip be among FPGA, CPLD, the EPLD any one.
8, according to any described TD-SCDMA covering system in the claim 5 to 7, it is characterized in that: described coupler and envelope detection circuit are built in the described uplink and downlink amplifying circuit.
9, according to any described TD-SCDMA covering system in the claim 5 to 7, it is characterized in that: described up amplifying circuit can be may one of make up arbitrarily in low noise amplifier, frequency selection circuit, the power amplifier.
10, according to any described TD-SCDMA covering system in the claim 5 to 7, it is characterized in that: described descending amplifying circuit can be may one of make up arbitrarily in low noise amplifier, frequency selection circuit, the power amplifier.
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| CNB2006100371420A CN100463555C (en) | 2006-08-22 | 2006-08-22 | TD-SCDMA shrouding system and its time slot power reading method |
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| CNB2006100371420A CN100463555C (en) | 2006-08-22 | 2006-08-22 | TD-SCDMA shrouding system and its time slot power reading method |
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| CN100463555C CN100463555C (en) | 2009-02-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108377505A (en) * | 2017-09-26 | 2018-08-07 | 深圳市唐诚兴业科技有限公司 | TDD-LTE and FDD-LTE mobile phone uplink signal detecting systems |
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| CN1330192C (en) * | 2003-07-31 | 2007-08-01 | 华为技术有限公司 | Method for high-frequency amplifying station to gain switching point in TD-SCDMA system |
| KR100663525B1 (en) * | 2004-06-10 | 2007-02-28 | 삼성전자주식회사 | Interference power measurement apparatus and method required space-time beam forming |
| CN100380841C (en) * | 2004-09-28 | 2008-04-09 | 北京信威通信技术股份有限公司 | Automatic power adjusting apparatus and method for repeater in TDD system |
| CN1756122A (en) * | 2004-09-28 | 2006-04-05 | 北京信威通信技术股份有限公司 | Trunk line amplifier for realizing TD-SCDMA system blind area covering |
| CN100370711C (en) * | 2006-01-24 | 2008-02-20 | 京信通信技术(广州)有限公司 | TD-SCDMA repeater system for third generation mobile communication system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108377505A (en) * | 2017-09-26 | 2018-08-07 | 深圳市唐诚兴业科技有限公司 | TDD-LTE and FDD-LTE mobile phone uplink signal detecting systems |
| CN108377505B (en) * | 2017-09-26 | 2021-05-14 | 深圳市唐诚兴业科技有限公司 | TDD-LTE and FDD-LTE mobile phone uplink signal detection system |
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Effective date of registration: 20160606 Address after: Nansha District Fengze road Guangzhou city Guangdong province 510000 No. 106 (self building No. 1) X1301-F322 (only for office use) (JM) Patentee after: GUANGZHOU ZHONGDING MULIN NETWORK TECHNOLOGY CO.,LTD. Address before: 510663 Guangzhou Science City, Guangdong Shenzhou Road, No. 10 Patentee before: COMBA TELECOM TECHNOLOGY (GUANGZHOU) Ltd. |
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Granted publication date: 20090218 Termination date: 20210822 |