CN108377505B

CN108377505B - TDD-LTE and FDD-LTE mobile phone uplink signal detection system

Info

Publication number: CN108377505B
Application number: CN201710884306.1A
Authority: CN
Inventors: 蒋俊荣; 曾庆和; 吴麓峰
Original assignee: Shenzhen Tangcheng Xingye Technology Co ltd
Current assignee: Shenzhen Tangcheng Xingye Technology Co ltd
Priority date: 2017-09-26
Filing date: 2017-09-26
Publication date: 2021-05-14
Anticipated expiration: 2037-09-26
Also published as: CN108377505A

Abstract

The invention discloses a TDD-LTE (time division duplex-long term evolution) and FDD-LTE mobile phone uplink signal detection system, which relates to the technical field of signal detection; the TDD-LTE synchronization module automatically completes cell search and wireless signaling processing of a TD-LTE wireless network to obtain accurate TDD uplink and downlink time slot timing and uplink and downlink time slot ratio information, and outputs uplink and downlink time slot indication signals through a GPIO interface; the TD-SCDMA synchronization module automatically completes cell search and wireless signaling processing of a TD-SCDMA wireless network to obtain accurate TD-SCDMA downlink time slot timing and downlink time slot information, and outputs a downlink time slot indication signal through a GPIO interface; the invention controls the detection receiving channel through the time slot to only start the detection at the uplink time, the system sensitivity meets the design requirement, the detection distance is long, and the problem of false operation of the system detected by the downlink signals of the base station is thoroughly solved.

Description

TDD-LTE and FDD-LTE mobile phone uplink signal detection system

The technical field is as follows:

the invention relates to a TDD-LTE (time division duplex-long term evolution) and FDD-LTE mobile phone uplink signal detection system, belonging to the technical field of signal detection.

Background art:

most of the current market mobile phone signal detectors are FDD working mode detectors, and with the popularization of 4G mobile phone systems, the detectors comprise FDD and TDD modes, so that the detectors in the market cannot accurately detect mobile phone signals of the TDD mode system, and show false alarm and short detection distance. At present, the working mode of the existing TD-LTE mobile phone signal detector is to continuously and simultaneously detect uplink and downlink signals, and as long as the frequency band of the TD-LTE signals is provided, downlink signals of a base station and uplink signals emitted by a mobile phone are also acquired by the TD-LTE mobile phone signal detector, so that the defects that the receiving sensitivity cannot be too high, and the wrong operation can be caused by the too high downlink base station signals, so that the sensitivity of a detection system is in self-contradiction, and the detection distance is short due to the system.

The invention content is as follows:

aiming at the problems, the technical problem to be solved by the invention is to provide a TDD-LTE and FDD-LTE mobile phone uplink signal detection system.

The invention relates to a TDD-LTE and FDD-LTE mobile phone uplink signal detection system, which comprises a TDD-LTE synchronization module, a TD-SCDMA synchronization module, an MCU & Ethernet control circuit, a radio frequency receiving module and a power supply; the TDD-LTE synchronization module and the TD-SCDMA synchronization module are both electrically connected with the MCU and the Ethernet control circuit, the TDD-LTE synchronization module automatically completes cell search and wireless signaling processing of a TD-LTE wireless network to obtain accurate TDD uplink and downlink time slot timing and uplink and downlink time slot ratio information, and uplink and downlink time slot indication signals are output through a GPIO interface; the TD-SCDMA synchronization module automatically completes cell search and wireless signaling processing of a TD-SCDMA wireless network to obtain accurate TD-SCDMA downlink time slot timing and downlink time slot information, and outputs a downlink time slot indication signal through a GPIO interface; the radio frequency receiving module enables an aerial operator network signal picked up by an antenna to be subjected to three-zero and one-filtering by a low-pass or high-pass filter, the signal is sent to a low-noise amplifier for three-zero and amplification, then the signal is divided into two paths of signals by a seven-zero and one-pass splitter, the two paths of signals respectively pass through an uplink channel and a downlink channel, the uplink filter passes through an uplink frequency band signal, the downlink filter passes through a downlink frequency band signal, then the signal passes through a three-level low-noise amplifier and a three-level filter, the amplified radio frequency signal is sent to a peak value logarithmic detector, direct-current component signals output by the detection; the MCU and the Ethernet control circuit are a processing center of the detector system, execute and complete various functions of the system according to a preset program, set a certain threshold through a plurality of ADC processes, enable each detection channel to complete detection, and for TDD mode network signals, a synchronization module gives out a time slot signal which is a detection working instruction, the MCU starts detection according to the time slot instruction according to the preset program uplink time and closes the detection according to the downlink time, thereby realizing the real meaning of TDD-lte & TD-SCDMA to realize time division detection and only detecting the mobile phone uplink signal; the Ethernet-to-serial communication module realizes the communication of the converted serial port forty-five with the MCU through the 10 pin and the 11 pin TRX of the Ethernet-to-serial communication module, and the power supply supplies power to the system.

Preferably, after the TDD-LTE synchronization module is powered on, the antenna picks up a TD-LTE network signal, and a cell search process is as follows: firstly, PSS is searched to obtain 5ms timing information, OFDM symbol time and the like, then SSS is searched to obtain 10ms timing information and cell group ID, and then more accurate time and frequency synchronization is carried out; and reading the MIB and SIB information, and obtaining the TDD uplink and downlink time slot ratio and special subframe format information in the SIB information.

Preferably, the antenna of the TD-SCDMA synchronization module picks up signals in the air, the signals are coupled by a capacitor three-zero-one, then useful signals filtered by a filter three-zero-one are sent to a low noise amplifier three-zero-one for amplification, then the signals are filtered by a first-stage filter three-zero-two, then clean TD-SCDMA signals are filtered by a low noise amplifier three-zero-two for amplification and a filter three-zero-three, the amplified signals are attenuated by a numerical control attenuator three-zero-five control signal, then the signals pass through a two-stage amplification and two-stage filter circuit, the signals are input to a detector one-zero-one for envelope detection by the coupling capacitor three-two-zero, the detected dc signals are output by a sixth pin of the detector one-zero-one for outputting the TD-SCDMA synchronization signals through a resistor one-zero-six and a resistor one-zero-nine for an MCU and a 11 pin of the detector two-zero-one, the MCU processes the detection signals from the detector according to a predetermined program, and the TD-, and outputting the signals to an MCU control unit for synchronous identification at pins 7 of the second, the third and the fourth connectors.

Preferably, the system also comprises a detection module, wherein the detection module picks up an aerial signal through a receiving antenna, the aerial signal is sent to a low-pass filter three-zero-one through coupling of a coupling capacitor three-zero-one, then is sent to a low-noise amplifier three-zero-one through coupling of a coupling capacitor three-zero-two, the signal is amplified, the amplified signal is sent to a power divider seven-zero-one through a capacitor three-zero-seven, the signal is divided into two paths, the two paths are respectively sent to an uplink channel and a downlink channel, one path of signal is sent to a 2 pin of a downlink signal filter three-zero-two, the 5 pin output of the downlink signal filter three-zero-two is amplified through a capacitor three-zero-eight and is sent to a 1 pin of a low-noise amplifier four-zero-one pair detector through the capacitor three-zero-two, then the signal is filtered through the filter three-zero-three, then is sent to the low-noise amplifier four-zero-one through a 5 pin of the capacitor three, The 6 pins are output to a main control board MCU for processing; and the other path of signal is sent to 2-pin input of a filter two zero one of an uplink channel through a power divider seven zero one, is output through 5 pins, then is similarly subjected to three-level low noise amplification and three-level filtering, is output to 1-pin input of a detector one zero one through 5 pins of a filter two zero four, and is output to 7 and 8 pins of a radio frequency receiving module four zero one to be processed by a system mainboard MCU after signal detection processing is carried out on the 5 pins.

Preferably, the MCU & Ethernet control circuit mainly comprises a core element of a low noise amplifier one-zero-one & Ethernet serial port communication module of the MCU, a 5 pin and a 6 pin of a four-zero-one radio frequency receiving module output downlink detection signals and 7 pin and 8 pin uplink detection signals of the four-zero-one radio frequency receiving module are respectively sent to corresponding pins from a three-zero-one to a three-two main board, namely, an uplink signal 5 pin and a 6 pin of the three-two corresponding pins of the main board do uplink mobile phone signal detection downlink signals, the 7 pin and the 8 pin do downlink signal field strength indication, then a CH1-CH24 pin of the one-zero-one low noise amplifier of the MCU does ADC signal acquisition and is processed according to a preset program, a mobile operator frequency division multiplexing signal FDD is detected, according to the detection level as a judgment basis, a 50 pin which exceeds a set voltage value and then sends a high level to drive a two-zero-nine triode to be conducted, and then a two, meanwhile, a pin 55 of a zero-one low-noise amplifier I of the MCU sends a high level to drive a second zero-seven triode to be conducted, and then the second zero-six triode acts to output the high level to a pin 3 of a second bus to output an alarm signal; detecting a mobile operator time division multiplexing signal TDD, outputting a time slot signal to 89-91 pins of a 7 pin, a8 pin and an enable signal of a three-to-five pin of a mainboard according to a detection level and a synchronization module, and transmitting the time slot signal to a zero pin and a zero pin of a low noise amplifier of an MCU (microprogrammed control unit), wherein the MCU receives Sync _ s & Sync _ s _ EN signals, and uses the detection level of a TD-LTE radio frequency receiving module as a judgment basis according to a preset program in uplink time, detects that the voltage value exceeds a set voltage value, then sends 50 pins of the zero pin and the zero pin of the low noise amplifier of the MCU out a high level to drive a two-to-nine conduction of a triode, then a two-to-zero-one action of a relay, simultaneously sends 55 pins of the zero pin and the one pin of the low noise amplifier of the MCU out a high level to drive a two; and the Sync _ s _ EN is high level, only 89-91 pins of a zero-one low noise amplifier of the MCU in the uplink time are used for ADC acquisition according to a Sync _ s signal, and the function parameter setting and the multi-computer combined system linkage centralized management are realized through a communication interface, a four-zero-one low noise amplifier and an Ethernet-to-serial port communication module according to a preset program.

Compared with the prior art, the invention has the beneficial effects that: the time slot control detection receiving channel only starts detection at the uplink time, the system sensitivity meets the design requirement, the detection distance is long, and the problem that the base station downlink signals detect the system malfunction is thoroughly solved.

Description of the drawings:

for ease of illustration, the invention is described in detail by the following detailed description and the accompanying drawings.

FIG. 1 is a schematic structural view of the present invention;

FIG. 2 is a block diagram of a TDD-LTE synchronization module according to the present invention;

FIG. 3 is a flow chart of a cell search signal according to the present invention;

FIG. 4 is a block diagram of a TD-SCDMA synchronization module according to the present invention;

FIG. 5 is a block diagram of an RF receiving module according to the present invention;

FIGS. 6a to 6e are schematic circuit diagrams of the MCU & Ethernet control circuit according to the present invention;

fig. 7a to 7d are schematic circuit diagrams of a TDD-LTE synchronization module according to the present invention;

fig. 8a to 8d are schematic circuit diagrams of TD-SCDMA synchronization module according to the present invention;

fig. 9a to 9d are schematic circuit diagrams of the rf receiving module according to the present invention;

fig. 10 is a schematic diagram of the MCU & ethernet control circuit of the present invention.

The specific implementation mode is as follows:

in order that the objects, aspects and advantages of the invention will become more apparent, the invention will be described by way of example only, and in connection with the accompanying drawings. It is to be understood that such description is merely illustrative and not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.

As shown in fig. 1 to 10, the following technical solutions are adopted in the present embodiment: the system comprises a TDD-LTE synchronization module, a TD-SCDMA synchronization module, an MCU & Ethernet control circuit, a radio frequency receiving module and a power supply; the TDD-LTE synchronization module and the TD-SCDMA synchronization module are both electrically connected with the MCU and the Ethernet control circuit, the TDD-LTE synchronization module automatically completes cell search and wireless signaling processing of a TD-LTE wireless network to obtain accurate TDD uplink and downlink time slot timing and uplink and downlink time slot ratio information, and uplink and downlink time slot indication signals are output through a GPIO interface; the TD-SCDMA synchronization module automatically completes cell search and wireless signaling processing of a TD-SCDMA wireless network to obtain accurate TD-SCDMA downlink time slot timing and downlink time slot information, and outputs a downlink time slot indication signal through a GPIO interface; the radio frequency receiving module filters an aerial operator network signal picked up by an antenna through a low-pass or high-pass filter three-zero one F301, sends the signal to a low-noise amplifier three-zero and U301 for amplification, then is divided into two paths of signals through a splitter seven-zero one S701, the two paths of signals respectively pass through an uplink channel and a downlink channel, the uplink filter passes through an uplink frequency band signal, the downlink filter passes through a downlink frequency band signal, then the signal passes through a three-level low-noise amplifier and a three-level filter, then the amplified radio frequency signal is sent to a peak value logarithmic detector, a direct current component signal (0.5-1.8V) is output through detection and respectively sent to an MCUADC IO functional port; the MCU and Ethernet control circuit is a processing center of the detector system, each function of the system is completed according to the execution of a preset program, a certain threshold is set through a plurality of ADC processes, each detection channel finishes detection, for TDD mode network signals, a synchronization module gives a time slot signal which is a detection working instruction, the MCU starts detection according to the time slot instruction (a synchronization signal output by a TD-LTE synchronization module) according to the preset program uplink time, and closes detection according to the downlink time, so that the time division detection is realized in the real sense of TDD-LTE & TD-SCDMA, and only uplink signals of a mobile phone are detected. The Ethernet-to-serial port communication module U402 realizes the communication of the converted serial port forty-five RJ45 with the MCU through the 10 pin and 11 pin TRX of the Ethernet-to-serial port communication module U402, and the power supply supplies power to the system.

Further, after the TDD-LTE synchronization module is powered on, the antenna picks up the TD-LTE network signal, and the cell search process is as follows: as shown in fig. 3, PSS is searched first to obtain 5ms timing information, OFDM symbol time, etc., SSS is searched to obtain 10ms timing information and cell group ID, and then more accurate time and frequency synchronization is performed; and reading the MIB and SIB information, and obtaining information such as TDD uplink and downlink time slot ratio, special subframe format and the like in the SIB information.

The 16 feet of the J201 output downlink synchronous indication signals, then the downlink synchronous indication signals are sent to the 3 feet of the U201 to be subjected to level conversion to be changed into 3.3V levels, the downlink synchronous indication signals are output through the 4 feet after being converted by an AND gate of the U203, the downlink synchronous signals are output to the 93 feet of the MCU through the 6 feet of the J203, the control unit makes the foot signals serve as synchronous identification signals judged by an ADC detection port, the downlink synchronous signals are high in downlink time and low in uplink time, and according to the characteristic, an ADC acquisition channel of the MCU opens a detection channel to acquire ADC work in the uplink time according to a preset program, so that the TDD-LTE system only carries out cyclic detection and acquisition in the uplink time.

Further, the antenna of the TD-SCDMA synchronization module picks up the air signal, couples the air signal through the capacitor tri-zero-one C301, then the useful signal is filtered out through the filter tri-zero-one F301, then the useful signal is sent to the low noise amplifier tri-zero-one U301 to be amplified through the coupling capacitor tri-zero-two C302, then the useful signal is filtered out through the filter tri-zero-two F302, then the clean TD-SCDMA signal is filtered out through the low noise amplifier tri-zero-two U302 and the filter tri-zero-three F303, the amplified signal is controlled to be attenuated through the numerical control attenuator tri-zero-five U305, then the signal is sent to the detector mono-zero-one U101 through the two-stage amplification and two-stage filter circuit by the signal coupling capacitor tri-two-zero C320 to be envelope-detected, the detected direct current signal is output from the detector mono-zero-one U101 through the resistor mono-zero-six R106 and the resistor mono-nine R109 to be sent to the MCU, the 11 th pin, through processing operation, TD-SCDMA synchronous signals are output through 29 pins of a second zero and a first U201 of a detector of the MCU, and are output to an MCU control unit through 7 pins of a second zero and a third P203 of a connector to be synchronous identification signals.

The radio frequency receiving module further comprises a detection module, wherein the detection module picks up aerial signals through a receiving antenna, the aerial signals are transmitted to a low-pass filter three-zero-one F301 through coupling of a coupling capacitor three-zero-one C301, then transmitted to a low-noise amplifier three-zero-one U301 through a coupling capacitor three-zero-two C302 to amplify the signals, the amplified signals are transmitted to a power divider seven-zero-one S701 through a capacitor three-zero seven C307 to divide the signals into two paths, the two paths are respectively transmitted to an uplink channel and a downlink channel, one path of signals are transmitted to a 2 pin of a downstream signal filter three-zero-two F302, a 5 pin output is transmitted to a 1 pin of a low-noise amplifier three-zero-two U302 to be amplified, then the signals are filtered through a filter three-zero-three F303, then the signals are subjected to two-stage amplification and filtering processing, then the signals are transmitted to a 1 pin detection of a low-noise amplifier four-zero-one U401 logarithm through a 5 pin of a filter three-zero-five F320 and a capacitor three-two C320, the detected signals are

Pins

5 and 6 of a J401 are output to a main control board MCU for processing; the other path of signals are sent to a 2-pin input and a 5-pin output of a two-zero one-F201 filter of an uplink channel through a seven-zero one S701 power divider, then are similarly subjected to three-level low noise amplification and three-level filtering, and finally are output to a 1-pin input of a one-zero one U101 detector through 5 pins of a two-zero four F204 filter, and the 5 pins are output to 7 and 8 pins of a four-zero one J401 radio frequency receiving module after signal detection processing and then are output to a system mainboard MCU for processing. It should be noted that the low-pass filters and band-pass filters corresponding to the receiving modules in different frequency bands are correspondingly matched; because the radio frequency receiving module circuit is the same as the PCB, the filter has corresponding matching in different network systems, for example, the filter adopts a low-pass filter in the telecommunication CDMA800MHZ network system, the band-pass filter adopts an uplink 825 plus 835MHZ filter and a downlink 870 plus 880MHZX filter, the mobile and communication GSM900MHZ network system receiving module filter also adopts a low-pass filter, the band-pass filter adopts an uplink 890 plus 915MHZ filter and a downlink 930 plus 960MHZX filter; the mobile and communication GSM1800MHZ network system receiving module filter needs to adopt a high-pass filter, the band-pass filter adopts an uplink 1710-1750MHZ filter and a downlink 1805-1850MHZX filter; the through WCDMA network system receiving module needs to adopt a high-pass filter, the band-pass filter adopts an uplink 1920-1980 MHZ filter and a downlink 2110-2170MHZX filter, and the like, so that the useful signal can be taken out to suppress the unwanted signal.

Furthermore, the MCU & Ethernet control circuit mainly comprises core elements of a low noise amplifier one-zero-one U101(STM32F205ZGT6) of the MCU and an Ethernet transfer serial port communication module U402(IPort-2), wherein a downlink detection signal (with a direct current voltage range of 0.5-1.8V corresponding to a receiving sensitivity of-75-/-25 dBm) is output by a pin 5 and a pin 6 of a four-zero-one J401 of the radio frequency receiving module, a 7-pin uplink detection signal and an 8-pin uplink detection signal (with a direct current voltage range of 0.5-1.8V corresponding to a receiving sensitivity of-85-/-25 dBm) of the four-zero-one J401 of the radio frequency receiving module are respectively sent to a pin 5 and a pin 6 of a mainboard three-one-two J301-312 corresponding to an uplink signal of the mainboard, an uplink mobile phone signal detection downlink signal is carried out by the pin 6, a pin 7 and a downlink signal field intensity indication is carried out by the pin 8, then a pin 1-CH24 of the low noise amplifier one-zero-, detecting a mobile operator frequency division multiplexing signal FDD (such as a GSM900 system, an uplink 890-plus 915MHZ and a downlink 925-plus 960MHZ)), and according to the detection level (0.5-1.8V) as a judgment basis, detecting that the voltage value exceeds a set voltage value, then sending a high level from a pin 50 of a zero-plus-U101 of a low noise amplifier of an MCU to drive a two-zero nine Q209 of a triode to be conducted, then actuating a two-zero-plus-JK 201 of a relay, meanwhile sending a high level from a pin 55 of the zero-plus-U101 of the low noise amplifier of the MCU to drive a two-zero seven Q207 of the triode to be conducted, and then actuating a two-zero six Q206 of the triode to output a high level to a pin 3 of a bus; the TDD signal of the detection mobile operator time division multiplexing is sent to the

pins

7 and 8 of the low noise amplifier one-zero-one U101 of the MCU according to the detection level (0.5-1.8V) + the time slot signal output by the synchronization module, and the enable signal (Sync _ s & Sync _ s _ EN when receiving the signal is high level) is sent to the pins 89-91 of the low noise amplifier one-zero-one U101 of the MCU, the MCU receives the Sync _ s & Sync _ s _ EN signal and sends the high level to drive the transistor two-zero-nine Q209 to be conducted and then the relay two-zero-one JK201 to be conducted according to the detection level (0.5-1.8V) of the TD-LTE radio frequency receiving module at the uplink time according to the preset program, the pin 50 of the low noise amplifier one-zero-one U101 of the MCU is detected to exceed the set voltage value, and the high level is sent to drive the transistor two-zero-nine Q207 to be conducted, and simultaneously the pin 55 of the low noise amplifier one-, then the triode two-zero six Q206 acts to output high level to the 3 pin of the bus two JP201 to output alarm signal; the Sync _ s _ EN is high level, ADC acquisition is carried out only by 89-91 pins of a zero-one-U101 of a low noise amplifier of the MCU in uplink time according to Sync _ s signals, and function parameter setting (detection threshold) and multi-computer combined system linkage centralized management are realized through a communication interface RS-485, a four-zero-one-U401 of the low noise amplifier and an Ethernet-to-serial communication module U402 according to a preset program.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

TDD-LTE and FDD-LTE cell-phone uplink signal detecting system which characterized in that: the system comprises a TDD-LTE synchronization module, a TD-SCDMA synchronization module, an MCU & Ethernet control circuit, a radio frequency receiving module and a power supply; the TDD-LTE synchronization module and the TD-SCDMA synchronization module are both electrically connected with the MCU and the Ethernet control circuit, the TDD-LTE synchronization module automatically completes cell search and wireless signaling processing of a TD-LTE wireless network to obtain accurate TDD uplink and downlink time slot timing and uplink and downlink time slot ratio information, and uplink and downlink time slot indication signals are output through a GPIO interface; the TD-SCDMA synchronization module automatically completes cell search and wireless signaling processing of a TD-SCDMA wireless network to obtain accurate TD-SCDMA downlink time slot timing and downlink time slot information, and outputs a downlink time slot indication signal through a GPIO interface; the radio frequency receiving module enables an aerial operator network signal picked up by an antenna to be subjected to three-zero and one-filtering by a low-pass or high-pass filter, the signal is sent to a low-noise amplifier for three-zero and amplification, then the signal is divided into two paths of signals by a seven-zero and one-pass splitter, the two paths of signals respectively pass through an uplink channel and a downlink channel, the uplink filter passes through an uplink frequency band signal, the downlink filter passes through a downlink frequency band signal, then the signal passes through a three-level low-noise amplifier and a three-level filter, the amplified radio frequency signal is sent to a peak value logarithmic detector, direct-current component signals output by the detection; the MCU and the Ethernet control circuit are a processing center of the detector system, execute and complete various functions of the system according to a preset program, set a certain threshold through a plurality of ADC processes, enable each detection channel to complete detection, and for TDD mode network signals, a synchronization module gives out a time slot signal which is a detection working instruction, the MCU starts detection according to the time slot instruction according to the preset program uplink time and closes the detection according to the downlink time, thereby realizing the real meaning of TDD-lte & TD-SCDMA to realize time division detection and only detecting the mobile phone uplink signal; the Ethernet-to-serial communication module realizes the communication between the Ethernet-to-serial port forty-five and the MCU through the 10 pin and the 11 pin TRX of the Ethernet-to-serial communication module, and the power supply supplies power to the system; the MCU & Ethernet control circuit mainly comprises a core element of a low noise amplifier one-zero-one & Ethernet serial port communication module of the MCU, a 5 pin and a 6 pin output downlink detection signal of a four-zero-one radio frequency receiving module and a 7 pin and an 8 pin uplink detection signal of the four-zero-one radio frequency receiving module are respectively sent to an uplink signal 5 pin and a 6 pin corresponding to three-zero-one to three-two corresponding pins of a mainboard for uplink mobile phone signal detection downlink signals, the 7 pin and the 8 pin are used for downlink signal field intensity indication, then a CH1-CH24 pin of the low noise amplifier one-zero-one of the MCU is used for ADC signal acquisition and is processed according to a preset program, a mobile operator frequency division multiplexing signal FDD is detected, a 50 pin which exceeds a set voltage value and then sends a high level to drive a two-zero-nine conduction of the triode, then a two-zero-one action of a relay, and simultaneously a 55 pin of the low noise amplifier one-zero-one of the MCU sends a high level to drive the two-seven conduction of the triode, then the triode two-zero-six action outputs high level to the 3 pin of the bus two to output alarm signal; detecting a mobile operator time division multiplexing signal TDD, outputting a time slot signal to 89-91 pins of a 7 pin, a8 pin and an enable signal of a three-to-five pin of a mainboard according to a detection level and a synchronization module, and transmitting the time slot signal to a zero pin and a zero pin of a low noise amplifier of an MCU (microprogrammed control unit), wherein the MCU receives Sync _ s & Sync _ s _ EN signals, and uses the detection level of a TD-LTE radio frequency receiving module as a judgment basis according to a preset program in uplink time, detects that the voltage value exceeds a set voltage value, then sends 50 pins of the zero pin and the zero pin of the low noise amplifier of the MCU out a high level to drive a two-to-nine conduction of a triode, then a two-to-zero-one action of a relay, simultaneously sends 55 pins of the zero pin and the one pin of the low noise amplifier of the MCU out a high level to drive a two; and the Sync _ s _ EN is high level, only 89-91 pins of a zero-one low noise amplifier of the MCU in the uplink time are used for ADC acquisition according to a Sync _ s signal, and the function parameter setting and the multi-computer combined system linkage centralized management are realized through a communication interface, a four-zero-one low noise amplifier and an Ethernet-to-serial port communication module according to a preset program.
2. The TDD-LTE and FDD-LTE mobile uplink signal detection system of claim 1 wherein: after the TDD-LTE synchronization module is powered on, an antenna picks up TD-LTE network signals, and the cell search process comprises the following steps: firstly, PSS is searched to obtain 5ms timing information and OFDM symbol time, then SSS is searched to obtain 10ms timing information and cell group ID, and then more accurate time and frequency synchronization is carried out; and reading the MIB and SIB information, and obtaining the TDD uplink and downlink time slot ratio and special subframe format information in the SIB information.
3. The TDD-LTE and FDD-LTE mobile uplink signal detection system of claim 1 wherein: an antenna of the TD-SCDMA synchronization module picks up an aerial signal, the aerial signal is coupled by a capacitor three zero one, a useful signal is filtered by a filter three zero one, the useful signal is sent to a low noise amplifier three zero one for amplification by a coupling capacitor three zero two, then the TD-SCDMA signal is filtered by a first stage filter three zero two for amplification, then the TD-SCDMA signal is filtered by a low noise amplifier three zero two for amplification and a filter three zero three for clean, the amplified signal is attenuated by a numerical control attenuator three zero five control signal, then the signal passes through a two-stage amplification and two-stage filter circuit, the coupling capacitor three two zero inputs the signal to a detector one zero one for envelope detection, a detected direct current signal is output by a sixth pin of the detector one zero one through a resistor one zero six and a resistor nine to an MCU and a pin 11 of the detector two zero one, then the MCU processes the detection signal from the detector according to a preset program, and the TD-SCDMA synchronization signal is output by a pin 29 of the detector two zero one through processing operation and passing, and outputting the signals to an MCU control unit for synchronous identification at pins 7 of the second, the third and the fourth connectors.
4. The TDD-LTE and FDD-LTE mobile uplink signal detection system of claim 1 wherein: the detection module picks up aerial signals through a receiving antenna, the aerial signals are sent to a low-pass filter three-zero-one through coupling of a coupling capacitor three-zero-one, then sent to a low-noise amplifier three-zero-one through a coupling capacitor three-zero-two to amplify the signals, the amplified signals are sent to a power divider seven-zero-one through a capacitor three-zero-seven to divide the signals into two paths, the two paths are respectively sent to an uplink channel and a downlink channel, one path of signals are sent to a 2 pin of a three-zero-two of a downlink signal filter, the 5 pin output of the one path of signals is amplified through the capacitor three-zero-eight through a low-noise amplifier three-zero-two, then the signals are filtered through the filter three-zero-three, then the signals are subjected to two-stage amplification and filtering processing, then the signals are sent to a 1 pin detection of a four-zero-one-to-one detector of the low-noise amplifier through the capacitor three-zero-two, the detected signals are output through, The 6 pins are output to a main control board MCU for processing; and the other path of signal is sent to 2-pin input of a filter two zero one of an uplink channel through a power divider seven zero one, is output through 5 pins, then is similarly subjected to three-level low noise amplification and three-level filtering, is output to 1-pin input of a detector one zero one through 5 pins of a filter two zero four, and is output to 7 and 8 pins of a radio frequency receiving module four zero one to be processed by a system mainboard MCU after signal detection processing is carried out on the 5 pins.