CN1889390A - Time division synchronous code division multiple access covering system applying related detection synchronization - Google Patents
Time division synchronous code division multiple access covering system applying related detection synchronization Download PDFInfo
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Abstract
This invention applies a coherent detection TD-SCDMA cover system including a coupling circuit, a near end switch circuit, a far end switch circuit, an up amplifying circuit and a down amplifying circuit, a coherent detection synchronous module and a monitor sub-system, in which, the coherent detection synchronous module is composed of a RF detection module and a synchronous process module, which carries out digital process to the received TD-SCDMA signals to get frame synchronous information to output control signals to the near end switch circuit, the far end switch circuit, the up and down amplifying circuits to control the on-off based on the information, the base station signal is the down time slot, then it controls the off of the up link and the on of the down link, otherwise, it controls the off of the down link and the on of the up link.
Description
[technical field]
The present invention relates to moving communicating field, relate in particular to a kind of synchronous time division synchronous code division multiple access covering system of correlation detection of using.
[technical background]
Fast development along with China's mobile communication cause, the 2nd present generation or 2.5 third-generation mobile communication systems are at the great demand that all can not satisfy society aspect capacity and the professional ability, and therefore the 2nd generation or 2.5 third-generation mobile communication systems will be replaced by the third generation (3G) mobile communication system.In order progressively to be evolved into third generation network neatly on the basis of second generation network, 3G has three communication standard: WCDMA, cdma2000, TD-SCDMA.TD-SCDMA (Time Division-Synchronous CodeDivision Multiple Access, TD SDMA, abbreviation TD-SCDMA) technology is proposed by China and formally became the 3G (Third Generation) Moblie international standard in 2000, and the system that follows this standard development has the very high availability of frequency spectrum and lower cost.
TD-SCDMA is called as low spreading rate (1.28MCps, 1.28 million chips/sec) time division multiplexing counting scheme in the ITU standard.
The Elementary Time Unit of TD-SCDMA is a radio frames, and frame length is 10ms, and each radio frames is divided into two 5ms standard subframes, and the structure of two standard subframes is identical.Single subframe is made up of 7 conventional time slots of identical time span and three kinds of special time slots (DWPTS, GP and UPPTS), and each subframe has two transfer points, and up-downgoing can be asymmetric.
TS0 is down direction always, and TS1 is up direction always, and TS2, TS3......TS6 will can be appointed as up direction or down direction dynamically according to actual business requirement.DwPTS is a down direction, and UpPTS is a up direction, and the centre by first switching point GP separately.
As the key player who is played the part of in second generation mobile communication covers, covering systems such as repeater will play important effect in 3-G (Generation Three mobile communication system).Because TD-SCDMA has special physical channel structure, can be according to the needs of business, change the time slot switching point neatly, satisfy the needs of up-downgoing non-symmetrical service, therefore, time synchronized plays a very important role to the TD-SCDMA tool, especially needs to realize the accurate switching of uplink and downlink timeslot as the TD-SCDMA covering system of trunking, amplifies and forwarding capability so that finish seamless signal.
Traditional detection method for synchronous obtains the envelope of TD-SCDMA signal by the radio frequency detecting circuit, utilize the feature of descending synchronous code time slot signal envelope then, find the frame synchronization of TD-SCDMA signal by the envelope position of searching for this specific width for the special time width.The method because simple, that cost is lower etc. is former because the TD-SCDMA covering system provides TD-SCDMA signal frame synchronizing function preferably, makes the TD-SCDMA covering system can realize the switching of uplink and downlink timeslot, finish seamless signal and amplify forwarding capability.
But traditional detection method for synchronous exists some shortcomings, and when the TD-SCDMA Signal-to-Noise of input hanged down, performance was bad, detection this moment synchronized result is inaccurate, can't keep accurately synchronously with the TD-SCDMA signal, therefore, also make its applied covering system also exist in same defective.
[summary of the invention]
The object of the present invention is to provide a kind of synchronous time division synchronous code division multiple access covering system of correlation detection of using, this covering system can be realized the switching of uplink and downlink timeslot accurately and stably under the lower-cost prerequisite of maintenance, finishes seamless amplification and forwarding capability to the TD-SCDMA signal.
The objective of the invention is to be achieved through the following technical solutions:
This uses the synchronous time division synchronous code division multiple access covering system of correlation detection, comprises coupling circuit, near-end built-up circuit, far-end built-up circuit, up amplifying circuit, descending amplifying circuit and Monitor And Control Subsystem;
The base station signal that comes through near-end built-up circuit transmission is carried out descending amplification with descending amplifying circuit after the far-end built-up circuit transfers to far-end covers; Up amplifying circuit amplifies after the near-end built-up circuit transfers to the base station the upward signal that comes through the transmission of far-end built-up circuit;
Monitor And Control Subsystem is monitored the various states of covering system, can the teletransmission state information give Surveillance center, and can accept various parameter settings;
Described near-end built-up circuit is forwarded to the input port of descending amplifying circuit with base station signal, and up output signal is forwarded to the base station; Described far-end built-up circuit is forwarded to the input port of up amplifying circuit with upward signal, and descending output signal is forwarded to far-end;
Described near-end built-up circuit, descending amplifying circuit, the far-end built-up circuit electrically connects the formation down link successively; Described far-end built-up circuit, up amplifying circuit, the near-end built-up circuit electrically connects the formation up link successively;
In addition, set up the correlation detection synchronization module, its output connects down link and up link respectively;
The output of described coupling circuit is connected with the input of described correlation detection synchronization module, and coupling circuit carries out after the signal coupling signal being transferred to the correlation detection synchronization module in any place of down link;
Described correlation detection synchronization module will be handled the back by the base station information that the coupling circuit transmission comes and obtain frame synchronization information, output control signals to the uplink and downlink link to control its break-make according to this frame synchronization information, when base station signal is descending time slot, then control down link and open, up link is closed; Otherwise, then to control up link and open, down link is closed.
Described correlation detection synchronization module comprises radio frequency detection module and synchronous processing module; The TD-SCDMA signal that radio frequency detection module is finished input carries out the function that envelope detection obtains envelope signal; Synchronous processing module carries out obtaining after the Digital Signal Processing frame synchronization to the TD-SCDMA signal to the envelope signal of radio frequency detection module input, and output control signal control covering system carries out the switching of uplink and downlink link, when base station signal is descending time slot, control then that up link is closed, down link is opened; Otherwise, control then that down link is closed, up link is opened.
Described synchronous processing module comprises AD sample circuit, AD control module, related operation module, synchronized result authentication module, control signal generating module, control signal driver module, MCU minimum system, MCU communication module and standard envelope generation module;
The AD sample circuit is finished the analog-to-digital conversion of envelope signal, and its input is connected with the output of radio frequency detection module, and its output is connected with the input of AD control module; The AD sample circuit can use comparator circuit to substitute, and when using comparator circuit to substitute, comparator circuit can be placed on radio frequency detection module;
The sampled data that the AD control module is controlled the AD sample circuit and the AD sample circuit is imported passes to the related operation module according to specific form, its output is connected with the input of related operation module, when the AD sample circuit substituted with comparator circuit, the envelope signal that the AD control module is responsible for importing was through to the related operation module;
The related operation module is carried out related operation respectively with the actual envelope signal of AD control module input and two standard envelopes of standard envelope generation module input, further determine the subframe original position of downstream signal then, the output frame synchronous indicating signal is to the synchronized result authentication module, and its output is connected with the input of synchronized result authentication module;
The synchronized result authentication module is verified the synchronous indicating signal of related operation module input, if checking is correct, then output checking accurate indication and synchronous control signal are given control signal generating module, and its output is connected with the input of control signal generating module;
Control signal generating module produces switch-over control signal according to the synchronous control signal of synchronized result authentication module input and the uplink and downlink switching point information of MCU minimum system input, and its output is connected with the input of control signal driver module;
The MCU minimum system communicates by the Monitor And Control Subsystem of bus and covering system, obtains uplink and downlink time slot switching point information and to the various quantity of states of monitoring host computer reporting system, the MCU minimum system is connected with the MCU communication module;
The MCU communication module transfers to from MCU minimum system acquisition uplink and downlink switching point information and with the uplink and downlink switching point information and is attached thereto the standard envelope generation module that connects;
Standard envelope generation module produces two standard envelope signals and transfers to according to uplink and downlink time slot switching point information and is attached thereto the related operation module that connects.
The control signal driver module is converted to the needed level signal of system with the switch-over control signal of control signal generating module input, and its output is connected with described near-end built-up circuit, far-end built-up circuit, descending amplifying circuit and up amplifying circuit respectively.
Two standard envelopes that described standard envelope generation module is produced are the lasting duration of a standard subframe, and one of them only comprises TS0 and DwPTS time slot signal; Another then is conventional TD-SCDMA subframe, comprises all downstream signal envelopes.
Described related operation module determines that the detailed process of the subframe original position of downstream signal is:
(1) will carry out related operation by the actual envelope signal of AD control module input and two envelope signals importing by standard envelope generation module, obtain two correlation curves;
(2) determine the peak value number and the corresponding peaks ratio of two correlation curves, and use relevant decision algorithm to determine the original position of subframe.
The level signal that described control signal driver module is produced can be differential signal or CMOS level signal.
Described AD control module, related operation module, synchronized result authentication module, control signal generating module, MCU communication module and standard envelope generation module all are integrated in and all are integrated in the fpga chip, also can be integrated in CPLD or EPLD chip.
When covering system was broken down into relay and capped end, described relay and capped end should be provided with described correlation detection synchronization module simultaneously.
Compared with prior art, the present invention possesses following advantage: owing to adopted described correlation detection synchronization module, this module has adopted comparatively advanced person's method of synchronization efficiently, and can utilize chip realizations such as FPGA, can be at the net synchronization capability that keeps providing under the lower-cost prerequisite superior performance, make the TD-SCDMA covering system can realize the switching of uplink and downlink time slot accurately and stably, finish seamless signal and amplify and forwarding capability.
[description of drawings]
Fig. 1 is a theory diagram of the present invention;
Fig. 2 is the theory diagram of synchronous processing module among the present invention;
Fig. 3 is the schematic diagram of two standard envelopes that standard envelope generation module is produced among the present invention;
Fig. 4 a, 4b is the structural representation of second embodiment of the invention respectively;
Fig. 5 is the theory diagram of third embodiment of the invention;
The schematic diagram of the switch-over control signal of the uplink and downlink timeslot that Fig. 6 is provided for correlation detection synchronization module among the present invention.
[embodiment]
The present invention is further illustrated below in conjunction with drawings and Examples:
The invention discloses a kind of synchronous time division synchronous code division multiple access covering system of correlation detection of using, this system adopts the nucleus module of correlation detection synchronization module as the TD-SCDMA covering system, utilize the corresponding signal process technology, realize frame synchronization the TD-SCDMA signal.Control corresponding mains switch at the corresponding switching point of TD-SCDMA signal and switch, thereby between up-downgoing, switch.
The theory diagram that the present invention uses the synchronous time division synchronous code division multiple access covering system of correlation detection as shown in Figure 1.Described covering system (is made up of LNA, frequency-selecting, power amplifier coupling circuit 101, near-end built-up circuit 102, descending amplifying circuit, also can form by a part wherein) 103, far-end built-up circuit 104, up amplifying circuit (be made up of LNA, frequency-selecting, power amplifier, also can be made up of a part wherein) 105, radio frequency detection module 106, synchronous processing module 107 and Monitor And Control Subsystem 108 constitute.Described near-end built-up circuit 102, coupling circuit 101, descending amplifying circuit 103, far-end built-up circuit 104 electrically connect successively and constitute down link; Described far-end built-up circuit 104, up amplifying circuit 105,102 of near-end built-up circuits electrically connect successively and constitute up link.
This covering system is exported to radio frequency detection module 106 with the TD-SCDMA downstream signal of base station after coupling circuit 101 is handled; The TD-SCDMA radiofrequency signal of 106 pairs of inputs of radio frequency detection module carries out obtaining envelope signal after the detection, and with the envelope signal input synchronous processing module 107 that obtains; 107 pairs of TD-SCDMA envelope signals of synchronous processing module carry out digital signal corresponding to be handled the frame synchronization of back acquisition TD-SCDMA signal and controls near-end built-up circuit 102, descending amplifying circuit 103, far-end built-up circuit 104 and up amplifying circuit 105 simultaneously; When synchronous processing module 107 judges that base station signals are descending time slot, control then that up link is closed, down link is opened; Otherwise, then control down link and close and make up link be out state.
See also Fig. 2, described synchronous processing module is by AD sample circuit 201 and FPGA treatment circuit 202, and control signal drive circuit 203 and MCU minimum system 204 constitute.
From the envelope detection signal input AD sample circuit 201 of radio frequency detection module, AD sample circuit 201 can substitute with comparator circuit, can place it in the radio frequency detection module when substituting with comparator circuit; Thereby the signal of AD sample circuit 201 output is sent into described FPGA circuit 202 and is carried out the related synchronization operation and obtain frame synchronization to the TD-SCDMA signal, and the uplink and downlink switch-over control signal of sending the TD-SCDMA covering system is given control signal drive circuit 203; According to the needs of system, control signal drive circuit 203 is with the level type signal of uplink and downlink switch-over control signal driving for needing of input, as CMOS level signal or various differential signal; MCU minimum system 204 communicates by the Monitor And Control Subsystem of 485 buses and covering system, obtains uplink and downlink time slot switching point information and reports various quantity of states.
The core processing module of synchronous processing module is a FPGA circuit 202, and FPGA circuit 202 has been finished the core algorithm of related synchronization, and its inner functional block diagram as shown in Figure 2.Please in conjunction with Fig. 1 and Fig. 2, FPGA circuit 202 each functional module realize among the present invention function and respective handling flow process are as follows:
1) input port of AD control module 213 is connected with the output port of AD sample circuit 201, is responsible for the sampled data that AD sample circuit 201 is controlled and AD sample circuit 201 is imported is passed to related operation module 214 according to specific form; When AD sample circuit 201 usefulness comparator circuits substitute, AD control module 213 be responsible for will input envelope signals through to related operation module 214, perhaps directly do not adopt this AD control module and directly comparator output signal directly exported to described related operation module 214;
2) MCU communication module 211 obtains uplink and downlink time slot switching point information by data/address bus from MCU minimum system 204, and corresponding information is imported standard envelope generation module 212 and control signal generating module 216;
3) standard envelope generation module 212 produces two standard envelope signals according to the uplink and downlink time slot switching point information of input, as Fig. 3, it is the lasting duration of a TD-SCDMA standard subframe that the standard envelope signal that produces continues duration, wherein 1 of standard envelope comprises TS0 and DwPTS time slot signal envelope as shown in Figure 3,2 of standard envelopes comprise all downstream signal envelopes, and the standard envelope 2 among Fig. 3 is standard envelopes that second uplink and downlink time slot point produced for time between TS3 and the TS4; The standard envelope signal of standard envelope generation module 212 outputs is input to related operation module 214;
4) related operation module 214 is carried out related operation respectively with the actual envelope signal of AD control module 213 inputs and two standard envelope signals of standard envelope generation module 212 inputs, will obtain two correlation curves, because the initial frame head position of actual envelope signal and standard envelope are on time, peak value will appear, difference according to the signal of reality input, article two, the peak value number of correlation curve appearance and corresponding peaks are more different than meeting, peak value number and corresponding peaks ratio according to two correlation curves, use relevant decision algorithm, can find out the subframe original position of TD-SCDMA signal; After related operation module 214 was finished relevant synchronous computing, the output frame synchronous indicating signal was given the synchronized result authentication module 215 that is attached thereto;
5) actual signal is because a variety of causes such as noise jamming, multipaths, the down-going synchronous index signal of related operation module 214 outputs, may be wrong, needing could be in order to produce control signal through 215 checkings of synchronized result authentication module, because wireless sub-frame of the every 5ms transmission of TD-SCDMA signal, if the frame synchronization result of all subframes is correct, per two adjacent index signals are at a distance of 5ms in the frame synchronization index signal that then provides.Around this principle, 215 pairs of related operation modules of synchronized result authentication module, 214 input down-going synchronous index signals are verified, after checking was correct, output was verified accurate indication and is exported correct synchronous control signal and produce control signal for control signal generating module 216;
6) control signal generating module 216 produces the uplink and downlink switch-over control signal of covering system according to the synchronous control signal of input and the uplink and downlink time slot switching point information of MCU communication module input, and the switch-over control signal that produces is given the control signal of the level type of control signal drive circuit 203 needing to obtain.
Among the present invention, described FPGA circuit 202 can use fpga chip to realize, also can use CPLD or EPLD chip to realize that promptly described AD control module 213, related operation module 214, synchronized result authentication module 215, control signal generating module 216, MCU communication module 211 and standard envelope generation module 212 all can be integrated in fpga chip, CPLD or the EPLD chip.
Please consult Fig. 1 again, following mask body is set forth the process that described covering system uplink and downlink time slot switches: the base station signal that donor antenna receives through DT port access arrangement after coupling circuit obtains envelope signal to radio frequency detection module and by radiofrequency signal by envelope detection, envelope signal enters synchronous processing module again, through after the respective handling of this module, realize synchronously with base station signal exactly.Control corresponding switch at the corresponding switching point of TD-SCDMA signal and switch, thereby between the uplink and downlink link, switch; If synchronous processing module judges that base station signal is a descending time slot, then to control and open down link after up link is closed, the repeater is handled downstream signal and is amplified, after the MT port is emitted to user mobile phone by user antenna; When the DT port is in the upward signal time slot, after closing, the control down link opens up link, and then upward signal is handled through the repeater and is amplified, and transmits go back to the base station by donor antenna at last.The native system block diagram is equally applicable to electric light mixing repeater and supporting with it tower amplifier and trunk amplifier.
Please consult Fig. 1 again, the various states of 108 pairs of covering systems of Monitor And Control Subsystem are monitored, and can the teletransmission state information give Surveillance center, and can accept various parameter settings.Monitor And Control Subsystem 108 can also be by the switching point of 485 interface configuration correlation detection synchronization module uplink and downlink time slots, 1,6 configuration (acquiescence is between time slot 3,4) arbitrarily of configuration scope time slot; If desired at other time slot, the upper strata supervisory control system can realize the software remote update by the new switching point of 485 serial ports notice MCU configuration so.
In the second embodiment of the present invention, described covering system can be broken down into relay and capped end two parts, and Fig. 4 a and Fig. 4 b represent the theory diagram of its relay and capped end respectively.Comparison diagram 1 and Fig. 4 a and Fig. 4 b in the present embodiment, are separated into the subsystem of two symmetries with first embodiment as can be seen, and the relay is corresponding substantially with the structure of capped end, just in the middle of employing optical fiber connect, to reach the purpose of prolongation communication line.
Among Fig. 4 a, the relay comprises coupling circuit 401, near-end built-up circuit 402, descending amplifying circuit 403, up amplifying circuit 407, radio frequency detection module 409, synchronous processing module 408, Monitor And Control Subsystem 406 and a pair of optical transceiver 404 and 405: described near-end built-up circuit 402, coupling circuit 401, descending amplifying circuit 403, optical transceiver 404 electrically connect successively and constitute down link; Described optical transceiver 405, up amplifying circuit 407, near-end built-up circuit 402 electrically connect successively and constitute up link; Coupling circuit 401 will be transferred to radio frequency detection module 409 and descending amplifying circuit 403 through the downstream signal that near-end built-up circuit 402 obtains from the base station; Descending amplifying circuit 403 downstream signal is amplified after optical transceiver 404 by Optical Fiber Transmission to capped end; Up amplifying circuit 407 will be amplified after near-end built-up circuit 402 transfers to the base station through the upward signal from capped end that optical transceiver 405 transmission come by optical fiber.
Fig. 4 b capped end then comprises coupling circuit 426, radio frequency detection module 418, synchronous processing module 419, Monitor And Control Subsystem 423, far-end built-up circuit 420, up amplifying circuit 422, descending amplifying circuit 421 and a pair of optical transceiver 417 and 424: described optical transceiver 417, coupling circuit 426, descending amplifying circuit 421, far-end built-up circuit 420 electrically connect successively and constitute down link; Described far-end built-up circuit 420, up amplifying circuit 422, optical transceiver 424 electrically connect successively and constitute up link; Coupling circuit 426 will be transferred to radio frequency detection module 418 and descending amplifying circuit 421 through the downstream signal that optical transceiver 417 obtains from the relay by optical fiber; Descending amplifying circuit 421 amplifies downstream signal after 420 outputs of far-end built-up circuit cover; The upward signal that up amplifying circuit 422 comes far-end built-up circuit 420 transmission amplify after optical transceiver 424 by Optical Fiber Transmission to the relay.
In conjunction with Fig. 4 a and Fig. 4 b, the base station signal that the relay donor antenna receives enters the relay after coupling circuit obtains envelope signal to radio frequency detection module and with radiofrequency signal through after the envelope detection through the DT port, envelope signal enters synchronous processing module again, through after the respective handling of this module, realize synchronously with base station signal exactly, if synchronous processing module judges that base station signal is a descending time slot, then controlling up link closes, down link is opened, the relay is handled downstream signal and is amplified, again by optical transceiver by Optical Fiber Transmission to capped end.The capped end optical transceiver receives that the next signal of Optical Fiber Transmission is after opto-electronic conversion, couple a signal to radio frequency detection module, then enter synchronous processing module, through after the base band signal process of this module, if synchronous processing module judges that signal is a descending time slot, then to control up link and close, down link is opened, capped end is handled downstream signal and is amplified, and is emitted to user mobile phone by user antenna; If synchronous processing module judges that signal is an ascending time slot, down link is closed, and capped end and the extreme up link of kind all are in out state, so that upward signal is carried out long-distance transmissions to the base station through optical fiber.
Please consult Fig. 4 a and Fig. 4 b again, the various states of Monitor And Control Subsystem 406 and 423 pairs of covering systems are monitored, and can the teletransmission state information give Surveillance center, and can accept various parameter settings.Monitor And Control Subsystem 406 and 423 can also be by the switching point of 485 interface configuration correlation detection synchronization module uplink and downlink time slots, 1,6 configuration (acquiescence is between time slot 3,4) arbitrarily of configuration scope time slot; If desired at other time slot, the upper strata supervisory control system can realize the software remote update by the new switching point of 485 serial ports notice MCU configuration so.
See also Fig. 5, it is the third embodiment of the present invention.Please consult Fig. 1 again, described coupling circuit 101, radio frequency detection module 106 and synchronous processing module 107 can carry out proper transformation according to application in the position of system and be coupling circuit 501 as shown in Figure 5, radio frequency detection module 507 and synchronous processing module 506, this conversion are applicable to wireless discharging-directly station, optical fiber repeater, electric light mixing repeater and supporting with it tower amplifier and trunk amplifier.In this embodiment, covering system is when initialization, synchronous processing module 506 does not provide before the uplink and downlink timeslot judged result, down link is in normally open, the TD-SCDMA signal of base station via downlink transmission to coupling circuit 501, through radio frequency detection module 507 and synchronous processing module 506, provide difference or cmos signal control near-end built-up circuit 502, descending amplifying circuit 503, far-end built-up circuit 504 and up amplifying circuit 505 by synchronous processing module 506 then, thereby between the uplink and downlink link, switch.。
See also Fig. 6, the correlation detection synchronization module among the present invention is responsible for producing the control signal that the uplink and downlink time slot switches.Open descending/up link again after closing the Uplink/Downlink of operating state among the present invention earlier, the time-delay of service time increases the isolation of uplink and downlink circuit, to avoid the self-excitation of repeater; As an example of using, control that to open up amplifying circuit control line after effective 6 chip of control line that descending amplifying circuit cuts out effective; Control after effective 4 chip of control line that up amplifying circuit cuts out, it is effective to control the control line that descending amplifying circuit opens.In addition, can change effective chip number of the control line that descending amplifying circuit and up amplifying circuit close by corresponding software.
The present invention is applicable to wireless discharging-directly station, optical fiber repeater, in the covering systems such as electric light mixing repeater, tower amplifier and trunk amplifier.
The present invention is described in narrative mode all the time, and wherein employed term is intended to describe and unrestricted.According to above description, can make many further modifications to the present invention, also can do many variations according to actual needs.Therefore, in additional claim scope, the present invention can adopt various implementation to specifically described embodiment.
Claims (10)
1, a kind of synchronous time division synchronous code division multiple access covering system of correlation detection of using comprises coupling circuit, near-end built-up circuit, far-end built-up circuit, up amplifying circuit, descending amplifying circuit and Monitor And Control Subsystem;
The base station signal that comes through near-end built-up circuit transmission is carried out descending amplification with descending amplifying circuit after the far-end built-up circuit transfers to far-end covers; Up amplifying circuit amplifies after the near-end built-up circuit transfers to the base station the upward signal that comes through the transmission of far-end built-up circuit;
Monitor And Control Subsystem is monitored the various states of covering system, can the teletransmission state information give Surveillance center, and can accept various parameter settings;
Described near-end built-up circuit is forwarded to the input port of descending amplifying circuit with base station signal, and up output signal is forwarded to the base station; Described far-end built-up circuit is forwarded to the input port of up amplifying circuit with upward signal, and descending output signal is forwarded to far-end;
Described near-end built-up circuit, descending amplifying circuit, the far-end built-up circuit electrically connects the formation down link successively; Described far-end built-up circuit, up amplifying circuit, the near-end built-up circuit electrically connects the formation up link successively;
It is characterized in that:
Set up the correlation detection synchronization module, its output connects down link and up link respectively;
The output of described coupling circuit is connected with the input of described correlation detection synchronization module, and coupling circuit carries out after the signal coupling signal being transferred to the correlation detection synchronization module in any place of down link;
Described correlation detection synchronization module will be handled the back by the base station information that the coupling circuit transmission comes and obtain frame synchronization information, output control signals to the uplink and downlink link to control its break-make according to this frame synchronization information, when base station signal is descending time slot, then control down link and open, up link is closed; Otherwise, then to control up link and open, down link is closed.
2, the synchronous time division synchronous code division multiple access covering system of application correlation detection according to claim 1 is characterized in that:
Described correlation detection synchronization module comprises radio frequency detection module and synchronous processing module;
Radio frequency detection module will be carried out the envelope signal that envelope detection obtains the TD-SCDMA signal by the downlink radio-frequency signal of coupling circuit input, and export this envelope signal to synchronous processing module; Synchronous processing module will carry out digitized processing to obtain frame synchronization information by the envelope signal that obtains after the detection of radio frequency detection module, the uplink and downlink link that outputs control signals to the TD-SCDMA covering system according to this frame synchronization information is to control its on off operating mode respectively, when base station signal is descending time slot, control then that up link is closed, down link is opened; Otherwise, control then that down link is closed, up link is opened.
3, the synchronous time division synchronous code division multiple access covering system of application correlation detection according to claim 2, it is characterized in that: described coupling circuit can be positioned at any position of down link, and the base station signal of proper strength is provided to the correlation detection synchronization module by the adjustment of the degree of coupling.
4, the synchronous time division synchronous code division multiple access covering system of application correlation detection according to claim 2, it is characterized in that: described descending amplifying circuit and up amplifying circuit can be by LNA, frequency-selecting, the power amplifier three forms, also can form by a part wherein, its characteristics are to finish enlarging function, can carry out opening and closing according to the control signal that the correlation detection synchronization module transmits simultaneously.
5, according to the synchronous time division synchronous code division multiple access covering system of claim 2 to 4 any one described application correlation detection, it is characterized in that: described synchronous processing module comprises AD sample circuit, AD control module, related operation module, synchronized result authentication module, control signal generating module, control signal driver module, MCU minimum system, MCU communication module and standard envelope generation module;
The AD sample circuit is finished the analog-to-digital conversion of envelope signal, and its input is connected with the output of radio frequency detection module, and its output is connected with the input of AD control module; The AD sample circuit can use comparator circuit to substitute, and when using comparator circuit to substitute, comparator circuit can be placed on radio frequency detection module;
The sampled data that the AD control module is controlled the AD sample circuit and the AD sample circuit is imported passes to the related operation module according to specific form, its output is connected with the input of related operation module, when the AD sample circuit substituted with comparator circuit, the envelope signal that the AD control module is responsible for importing was through to the related operation module;
The related operation module is carried out related operation respectively with the actual envelope signal of AD control module input and two standard envelopes of standard envelope generation module input, further determine the subframe original position of downstream signal then, the output frame synchronous indicating signal is to the synchronized result authentication module, and its output is connected with the input of synchronized result authentication module;
The synchronized result authentication module is verified the synchronous indicating signal of related operation module input, if checking is correct, then output checking accurate indication and synchronous control signal are given control signal generating module, and its output is connected with the input of control signal generating module;
Control signal generating module produces switch-over control signal according to the synchronous control signal of synchronized result authentication module input and the uplink and downlink switching point information of MCU minimum system input, and its output is connected with the input of control signal driver module;
The MCU minimum system communicates by the Monitor And Control Subsystem of bus and covering system, obtains uplink and downlink time slot switching point information and to the various quantity of states of monitoring host computer reporting system, the MCU minimum system is connected with the MCU communication module;
The MCU communication module transfers to from MCU minimum system acquisition uplink and downlink switching point information and with the uplink and downlink switching point information and is attached thereto the standard envelope generation module that connects;
Standard envelope generation module produces two standard envelope signals and transfers to according to uplink and downlink time slot switching point information and is attached thereto the related operation module that connects;
The control signal driver module is converted to the needed level signal of system with the switch-over control signal of control signal generating module input, and its output is connected with described near-end built-up circuit, far-end built-up circuit, descending amplifying circuit and up amplifying circuit respectively.
6, the synchronous time division synchronous code division multiple access covering system of application correlation detection according to claim 5, it is characterized in that: described AD control module, related operation module, synchronized result authentication module, control signal generating module, MCU communication module and standard envelope generation module all are integrated in the fpga chip, also can be integrated in CPLD or EPLD chip.
7, the synchronous time division synchronous code division multiple access covering system of application correlation detection according to claim 5, it is characterized in that: two standard envelopes that described standard envelope generation module is produced are the lasting duration of a standard subframe, and one of them only comprises TSO and DwPTS time slot signal; Another then is conventional TD-SCDMA subframe, comprises all downstream signal envelopes.
8, the synchronous time division synchronous code division multiple access covering system of application correlation detection according to claim 5 is characterized in that described related operation module determines that the detailed process of the subframe original position of downstream signal is:
(1) will carry out related operation by the actual envelope signal of AD control module input and two envelope signals importing by standard envelope generation module, obtain two correlation curves;
(2) determine the peak value number and the corresponding peaks ratio of two correlation curves, and use relevant decision algorithm to determine the original position of subframe.
9, according to any synchronous time division synchronous code division multiple access covering system of described application correlation detection in the claim 6 to 8, it is characterized in that: the level signal that described control signal driver module is produced can be differential signal or CMOS level signal.
10, the synchronous time division synchronous code division multiple access covering system of application correlation detection according to claim 5, it is characterized in that: when covering system was broken down into relay and capped end, then described relay and capped end should be provided with described correlation detection synchronization module simultaneously.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102611507A (en) * | 2011-12-26 | 2012-07-25 | 深圳市虹远通信有限责任公司 | Full-synchronizing TD-SCDMA (Time Division-Synchronization Code Division Multiple Access) optical-fiber amplification system |
| CN103167600A (en) * | 2013-03-29 | 2013-06-19 | 京信通信系统（广州）有限公司 | Method and device for synchronizing base stations |
| CN110426722A (en) * | 2019-06-20 | 2019-11-08 | 广州南方卫星导航仪器有限公司 | Movement station and the transmission method of differential corrections data, terminal device, storage medium |
| CN113852436A (en) * | 2021-08-27 | 2021-12-28 | 电子科技大学 | Clock synchronization system applied to 5G small base station |
-
2006
- 2006-07-14 CN CNB2006100364910A patent/CN100568772C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102611507A (en) * | 2011-12-26 | 2012-07-25 | 深圳市虹远通信有限责任公司 | Full-synchronizing TD-SCDMA (Time Division-Synchronization Code Division Multiple Access) optical-fiber amplification system |
| CN102611507B (en) * | 2011-12-26 | 2014-12-31 | 深圳市虹远通信有限责任公司 | Full-synchronizing TD-SCDMA (Time Division-Synchronization Code Division Multiple Access) optical-fiber amplification system |
| CN103167600A (en) * | 2013-03-29 | 2013-06-19 | 京信通信系统（广州）有限公司 | Method and device for synchronizing base stations |
| CN110426722A (en) * | 2019-06-20 | 2019-11-08 | 广州南方卫星导航仪器有限公司 | Movement station and the transmission method of differential corrections data, terminal device, storage medium |
| CN113852436A (en) * | 2021-08-27 | 2021-12-28 | 电子科技大学 | Clock synchronization system applied to 5G small base station |
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| CN100568772C (en) | 2009-12-09 |
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