CN1909416A - TD-SCDMA shrouding system and its digital time slot automatic level control method - Google Patents
TD-SCDMA shrouding system and its digital time slot automatic level control method Download PDFInfo
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Abstract
The invention relates to a digit time-slit automatic voltage control method of TD-SCDMA cover system, wherein it comprises: a, checking the radio signal power of ascending and descending chains, to output enveloped check wave signal; b, obtaining the automatic voltage control start value and ascending, descending switch points; c, combining frame synchronous instruct signal and time slit switch point to generate time slit instruct signal; d, based on said time slit instruct signal, outputting relative control information, and sampling relative enveloped check wave signal, to obtain the power sample value of each time slit; e, based on the time instruct signal, the time slit power sample value and the automatic voltage control start value, generating damping control value of each damper before the start of each time slit. The invention also discloses a relative TD-SCDMA cover system and the invention can effectively protect cover system and accurately control its output power.
Description
[technical field]
The present invention relates to mobile communication covering system field, relate in particular to a kind of TD-SCDMA covering system and digit time slot automatic level control method thereof.
[technical background]
When application TD-SCDMA system carries out networking; also can run into the communication blind district problem; because in the communication process of signal; run into obstacle through regular meeting; as building, mountain range, various complex-terrains etc.; at the back side of obstacle and the inside of various underground structures, in market place builet below the ground, subway, tunnel, because signal can not cover the generation communication blind district.Direct discharging station has the low and characteristics in increase coverage territory rapidly of cost of investment, becomes an indispensable part in radio network optimization and covering.Direct discharging station is divided into outdoor repeater and indoor repeater.When building the indoor or outdoors covering system, only use the repeater also to be difficult to solve the extensive requirement that covers, need to be used trunk amplifier sometimes.
In the TD-SCDMA system, upward signal and downstream signal are in same frequency, distinguish uplink and downlink by time-multiplexed mode.If in the TD-SCDMA system, use traditional repeater or trunk amplifier, repeater or trunk amplifier upstream and downstream treatment system are operated on the same frequency, uplink and downlink signals will produce positive feedback, cause signal degradation, trunk amplifier can't use, therefore need to need in repeater or the trunk amplifier frame synchronization of synchronization module realization, make repeater or trunk amplifier between correct uplink and downlink timeslot, realize switching the TD-SCDMA signal.
For power output, need in repeater and trunk amplifier, realize ALC (Auto Level Control: automatic electric-level control) function to repeater and trunk amplifier enforcement protection and control repeater and trunk amplifier.Traditional ALC function realizes by simulated mode, by output signal is carried out detection, obtain the analogue envelope of signal, because envelope level has characterized signal strength signal intensity, the direct feedback of detection envelope that use obtains comes corresponding ATT (Attenuator: attenuator), promptly finished corresponding ALC function in the control system link.It is very effective that this kind mode is used in the system of frequency division multiplexing, but for the time-multiplexed TD-SCDMA of employing system, owing to just can obtain corresponding rectified signal after each time slot signal reaches detecting circuit, carry out ATT control with the rectified signal feedback that obtains this moment, the beginning part that then can cause each time slot signal is not carried out ALC and but the signal of back has carried out ALC, and the TD-SCDMA signal of reality has been caused destruction.
[summary of the invention]
Purpose of the present invention will overcome above-mentioned deficiency exactly, and a kind of TD-SCDMA covering system digit time slot automatic level control method that can realize the control of precise figures time slot automatic electric-level in covering systems such as TD-SCDMA repeater, trunk amplifier is provided.
Another object of the present invention is to provide a kind of TD-SCDMA covering system of using above-mentioned digit time slot automatic level control method.
First purpose of the present invention is achieved by the following technical solution:
Described TD-SCDMA covering system digit time slot automatic level control method comprises the steps:
A, by detecting the radiofrequency signal power of each relevant position in the uplink and downlink link, output envelope rectified signal, the amplitude of envelope detection signal has characterized power level;
B, obtain the automatic electric-level control control starting value and the uplink and downlink time slot switching point information of uplink and downlink signal;
C, produce time slit instruction signal in conjunction with frame synchronization index signal and uplink and downlink time slot switching point information;
D, according to time slit instruction signal output corresponding control information, each corresponding envelope detection signal in the uplink and downlink link is sampled, obtain the power samples value of each each time slot of relevant position in the uplink and downlink link;
E, the time slit instruction signal during according to the signal uplink and downlink, time slot power sampled value, automatic electric-level control control starting value produce in the uplink and downlink link each time slot of corresponding each attenuator controlling value that decays each time slot begins before;
F, according to the decay controlling value, generation and send the attenuator control signal each time slot begins before.
Attenuator control signal described in the described step f can the arbitrary form output of analog or digital.
Described frame synchronization index signal produces by the TD-SCDMA covering system is unified.
Second purpose of the present invention is achieved by the following technical solution:
Described TD-SCDMA covering system comprises near-end built-up circuit, descending amplifying circuit, up amplifying circuit, far-end built-up circuit, synchronization module and monitoring host computer;
Described near-end built-up circuit, descending amplifying circuit, far-end built-up circuit electrically connect the formation down link successively; The downstream signal that descending amplifying circuit comes near-end built-up circuit transmission amplifies after the far-end built-up circuit transfers to far-end covers;
Described far-end built-up circuit, up amplifying circuit, near-end built-up circuit electrically connect the formation up link successively; Up amplifying circuit will carry out power amplification after the near-end built-up circuit transfers to the base station through the upward signal that the transmission of far-end built-up circuit comes;
Described synchronization module obtains downstream signal by a coupler, and produces synchronizing signal, this signal is transferred in the uplink and downlink link realize Synchronization Control;
Monitoring host computer is monitored the various parameters of TD-SCDMA covering system by wired or wireless mode, can automatic electric-level control control starting value be set by it;
In addition, also comprise digit time slot automatic electric-level control module, it is connected with described synchronization module, uplink and downlink amplifying circuit respectively, described digit time slot automatic electric-level control module receives the frame synchronization index signal of synchronization module, produces time slit instruction signal in conjunction with frame synchronization index signal and uplink and downlink time slot switching point information; Also receive the envelope detection signal that produces by the detecting circuit in the uplink and downlink amplifying circuit; Sample then according to time slit instruction signal output corresponding control information, and to each corresponding envelope detection signal in the uplink and downlink link, obtain the power samples value of each each time slot of relevant position in the uplink and downlink link; Time slit instruction signal during then according to the signal uplink and downlink, time slot power sampled value, automatic electric-level control control starting value, the decay controlling value of each time slot of generation before each time slot begins; At last according to the decay controlling value, each time slot begins before, produce and send the attenuator control signal in the uplink and downlink amplifying circuit, realize that automatic electric-level is controlled accurately.
Particularly, described digit time slot automatic electric-level control module comprises that power samples control module, power samples ADC submodule, MCU submodule, MCU Control on Communication submodule, time slit instruction signal produce submodule, the time slot pad value produces submodule and the attenuator control signal produces submodule;
The MCU submodule is connected with described monitoring host computer, in order to communicate by letter with described monitoring host computer, obtains the automatic electric-level control control starting value and the uplink and downlink time slot switching point information of uplink and downlink signal, and its output connects the input of MCU Control on Communication submodule;
MCU Control on Communication submodule also extremely produces submodule and time slot pad value generation submodule with the time slit instruction signal that its output is connected respectively with this data forwarding in order to the data that transmit by data/address bus reception MCU submodule;
Time slit instruction signal produces submodule, transmit the uplink and downlink time slot switching point information of coming in order to accept MCU Control on Communication submodule from the MCU submodule, and after the frame synchronization index signal generation time slit instruction signal in conjunction with the synchronization module generation, described time slit instruction signal is transferred to the power samples control submodule and the time slot pad value that are attached thereto respectively produces submodule;
Power samples control submodule, according to the corresponding control signal of the time slit instruction signal generation of importing to power samples ADC submodule, power controlling sampling ADC submodule carries out the time slot power sampling to each road envelope detection signal of input, and will be transferred to the time slot pad value generation submodule that is attached thereto by the power samples value that the transmission of power samples ADC submodule comes;
Power samples ADC submodule, it is connected with the uplink and downlink amplifying circuit, in order to the control of accepting described envelope detection signal and accepting power samples control submodule each corresponding envelope detection signal in the uplink and downlink link is carried out power samples, then the power samples value is transferred to described power samples control submodule;
The time slot pad value produces submodule, before each time slot begins, produce each time slot decay controlling value of corresponding each attenuator in the uplink and downlink link in order to time slit instruction signal, each time slot power sampled value, automatic electric-level control control starting value, and transmit it to the attenuator control signal generation submodule that is attached thereto according to input;
The attenuator control signal produces submodule, and it is connected with the uplink and downlink amplifying circuit, in order to according to the decay controlling value, system is produced the control signal of each attenuator before each time slot begins, and in the uplink and downlink amplifying circuit of feed-in uplink and downlink link.
Described MCU communicator module, time slit instruction signal produce submodule, the time slot pad value produces submodule and power samples control submodule is integrated in the same control chip.Described control chip be among FPGA, CPLD, the EPLD any one.
Described attenuator control signal can be analog signal or digital signal, decides according to the covering system demand.
Described up amplifying circuit, descending amplifying circuit all can be may one of make up arbitrarily in low noise amplifier, frequency selection circuit, the power amplifier.
Compared with prior art; the present invention possesses following advantage: solved the problem that traditional ALC is unsuitable for the TD-SCDMA covering system; adopt the method for digital automatic electric-level control, effectively protected TD-SCDMA covering system and realization accurate control its power output.
[description of drawings]
Fig. 1 is a TD-SCDMA covering system principle schematic of the present invention;
Fig. 2 is the principle schematic of digit time slot automatic electric-level control module of the present invention.
[embodiment]
The present invention is further illustrated below in conjunction with drawings and Examples:
As everyone knows, when TD-SCDMA covering system (as repeater and dried putting) is worked, by the envelope detection signal of its inner detecting circuit output radiofrequency signal, the level amplitude of rectified signal has characterized the power level of signal respectively for the descending amplifying circuit of covering system and up amplifying circuit.
Based on the above-mentioned rectified signal that characterizes signal power strength, design according to following thinking among the present invention: the TD-SCDMA covering system uses the synchronizing function module to obtain the frame synchronization index signal, and exports to digit time slot automatic electric-level control module.The TD-SCDMA covering system uses digit time slot automatic electric-level control (being called for short ALC) module to finish digit time slot ALC function, its frame synchronization index signal according to input produces the initial moment that index signal is indicated each time slot, use power samples ADC chip that the rectified signal of uplink and downlink amplifying circuit output is sampled at each corresponding time slot then, obtained the power of each time slot.Digit time slot ALC module is communicated by letter with monitoring host computer by a MCU submodule, monitoring host computer can be provided with the ALC control starting value, each time slot power and ALC control starting value that digit time slot ALC module calculates according to sampling, obtain the different value of setting of each time slot of each ATT (attenuator) in the uplink and downlink link through computing, before each time slot begins, send each ATT control signal of corresponding time slot then, thereby uplink and downlink TD-SCDMA signal has been finished the ALC function of each time slot with the method for digital processing.
See also Fig. 1, according to above-mentioned mentality of designing, the TD-SCDMA covering system that the present invention has used the digit time slot automatic level control method comprises near-end built-up circuit 11, descending amplifying circuit 21, up amplifying circuit 22, far-end built-up circuit 12, synchronization module 32 and monitoring host computer (not shown).
Described near-end built-up circuit 11, descending amplifying circuit 21, far-end built-up circuit 12 electrically connect successively and constitute down link; The downstream signal that descending amplifying circuit 12 comes near-end built-up circuit 11 transmission amplifies after far-end built-up circuit 12 transfers to far-end MT covers.
Described far-end built-up circuit 12, up amplifying circuit 22, near-end built-up circuit 11 electrically connect successively and constitute up link; Up amplifying circuit 22 will carry out power amplification after near-end built-up circuit 11 transfers to the base station through the upward signal that 12 transmission of far-end built-up circuit come.
Uplink and downlink amplifying circuit 21,22 all is built-in with detecting circuit (not shown, down together), can produce the envelope detection signal that has characterized power level.
Described synchronization module 32 obtains downstream signal by a coupler 31, and produces synchronizing signal, this signal is transferred in the uplink and downlink link realize Synchronization Control; This coupler 31 can place any place of down link.
Monitoring host computer (not shown) is monitored the various parameters of TD-SCDMA covering system by the mode of wired mode or radio modem (not shown), can automatic electric-level control control starting value be set by it;
In addition, also comprise digit time slot automatic electric-level control module 4, its respectively with described synchronization module 32, uplink and downlink amplifying circuit 21,22 connect, described digit time slot automatic electric-level control module 4 receives the frame synchronization index signal of synchronization module 32, produces time slit instruction signal in conjunction with frame synchronization index signal and uplink and downlink time slot switching point information; Also receive the envelope detection signal that produces by the detecting circuit in the uplink and downlink amplifying circuit 21,22; Sample then according to time slit instruction signal output corresponding control information, and to each corresponding envelope detection signal in the uplink and downlink link, obtain the power samples value of each each time slot of relevant position in the uplink and downlink link; Time slit instruction signal during then according to the signal uplink and downlink, time slot power sampled value, automatic electric-level control control starting value, each time slot decay controlling value of corresponding each attenuator in the generation uplink and downlink link before each time slot begins; According to the decay controlling value, the control signal that produces and send each attenuator before each time slot begins arrives in the uplink and downlink amplifying circuit 21,22, realizes automatic electric-level control accurately at last.
Please in conjunction with Fig. 1 and Fig. 2, particularly, described digit time slot automatic electric-level control module 4 comprises that power samples control module 44, power samples ADC submodule 46, MCU submodule 45, MCU Control on Communication submodule 41, time slit instruction signal produce submodule 42, time slot pad value submodule 43 and attenuator control signal and produce submodule 47;
MCU Control on Communication submodule 41 also extremely produces submodule 42 and time slot pad value generation submodule 43 with the time slit instruction signal that its output is connected respectively with this data forwarding in order to the data that transmit by data/address bus reception MCU submodule 45;
Time slit instruction signal produces submodule 42, transmit the uplink and downlink time slot switching point information of coming in order to accept MCU Control on Communication submodule 41 from MCU submodule 45, and after the frame synchronization index signal generation time slit instruction signal in conjunction with synchronization module 32 generations, described time slit instruction signal is transferred to the power samples control submodule 44 and the time slot pad value that are attached thereto respectively produces submodule 43;
Power samples control submodule 44, according to the corresponding control signal of the time slit instruction signal generation of importing to power samples ADC submodule 46, each road envelope detection signal of 46 pairs of inputs of power controlling sampling ADC submodule carries out the time slot power sampling, and will be transferred to the time slot pad value generation submodule 43 that is attached thereto by the power samples value that the transmission of power samples ADC submodule comes;
Power samples ADC submodule 46, itself and uplink and downlink amplifying circuit 21,22 connect, in order to accept described uplink and downlink amplifying circuit 21, envelope detection signals that 22 transmission come and the control of accepting power samples control submodule 44 are carried out power samples to the envelope detection signal, then the power samples value are transferred to described power samples control submodule 44;
The time slot pad value produces submodule 43, before each time slot begins, produce each time slot decay controlling value of corresponding each attenuator in the uplink and downlink link in order to time slit instruction signal, each time slot power sampled value, automatic electric-level control control starting value, and transmit it to the automatic attenuation control signal generation submodule 47 that is attached thereto according to input;
The attenuator control signal produces submodule 47, itself and uplink and downlink amplifying circuit 21,22 connect, in order to according to the decay controlling value, before each time slot begins, system is produced the control signal of each respective attenuation device in the uplink and downlink link, and in the uplink and downlink amplifying circuit 21,22 of feed-in uplink and downlink link, be implemented in and send accurate deamplification before each time slot begins, realize accurate ALC control.
Described MCU communicator module 41, time slit instruction signal produce submodule 42, the time slot pad value produces submodule 43 and power samples control submodule 44 is integrated in the same control chip.Described control chip be among FPGA, CPLD, the EPLD any one.
Described attenuator control signal can be analog signal or digital signal, adapts to the requirement of described covering system and decides.
Described up amplifying circuit 22, descending amplifying circuit 21 all can be may one of make up arbitrarily in low noise amplifier, frequency selection circuit, the power amplifier.
In above-mentioned embodiment, can take out digit time slot automatic level control method in the TD-SCDMA covering system of the present invention, specifically comprise the steps:
A, by detecting the radiofrequency signal power of each relevant position in the uplink and downlink link, output envelope rectified signal, the amplitude of envelope detection signal has characterized power level;
B, obtain the automatic electric-level control control starting value and the uplink and downlink time slot switching point information of uplink and downlink signal;
C, the frame synchronization index signal and the uplink and downlink time slot switching point information that produce in conjunction with the synchronization module by the TD-SCDMA covering system produce time slit instruction signal;
D, according to time slit instruction signal output corresponding control information, each corresponding envelope detection signal in the uplink and downlink link is sampled, obtain each time slot power sampled value of each relevant position in the uplink and downlink link;
E, the time slit instruction signal during according to the signal uplink and downlink, time slot power sampled value, automatic electric-level control control starting value, the decay controlling value of each time slot of generation each time slot begins before;
F, according to the decay controlling value, each time slot begins before, produce and send the control signal of each attenuator in the uplink and downlink link, wherein the attenuator control signal can the arbitrary form of analog or digital be exported, and decides according to the demand of applied covering system.
The present invention is applicable to various repeaters and main line repeater, but is not so limited.Utilize the present invention can make the TD-SCDMA covering system be able to better protect, and achieve the control of exact figure time slot automatic electric-level.
Claims (10)
1, a kind of TD-SCDMA covering system digit time slot automatic level control method is characterized in that comprising the steps:
A, by detecting the radiofrequency signal power of each relevant position in the uplink and downlink link, output envelope rectified signal, the amplitude of envelope detection signal has characterized power level;
B, obtain the automatic electric-level control control starting value and the uplink and downlink time slot switching point information of uplink and downlink signal;
C, produce time slit instruction signal in conjunction with frame synchronization index signal and uplink and downlink time slot switching point information;
D, according to time slit instruction signal output corresponding control information, and each corresponding envelope detection signal in the uplink and downlink link sampled, obtain the power samples value of each each time slot of relevant position of uplink and downlink link;
E, the time slit instruction signal during according to the signal uplink and downlink, time slot power sampled value, automatic electric-level control control starting value, the decay controlling value of each time slot of corresponding each attenuator in the generation uplink and downlink link each time slot begins before;
F, according to the decay controlling value, each time slot begins before, produce and send the attenuator control signal, control the pad value of each attenuator in the link.
2, TD-SCDMA covering system digit time slot automatic level control method according to claim 1 is characterized in that the attenuator control signal described in the step f can the arbitrary form output of analog or digital.
3, TD-SCDMA covering system digit time slot automatic level control method according to claim 1 and 2 is characterized in that: described frame synchronization index signal produces by the TD-SCDMA covering system is unified.
4, a kind of TD-SCDMA covering system comprises near-end built-up circuit, descending amplifying circuit, up amplifying circuit, far-end built-up circuit, synchronization module and monitoring host computer;
Described near-end built-up circuit, descending amplifying circuit, far-end built-up circuit electrically connect the formation down link successively; The downstream signal that descending amplifying circuit comes near-end built-up circuit transmission amplifies after the far-end built-up circuit transfers to far-end covers;
Described far-end built-up circuit, up amplifying circuit, near-end built-up circuit electrically connect the formation up link successively; Up amplifying circuit will carry out power amplification after the near-end built-up circuit transfers to the base station through the upward signal that the transmission of far-end built-up circuit comes;
Described synchronization module obtains downstream signal by a coupler, and produces synchronizing signal, this signal is transferred in the uplink and downlink link realize Synchronization Control;
Monitoring host computer is monitored the various parameters of TD-SCDMA covering system by wired or wireless mode, can automatic electric-level control control starting value be set by it;
It is characterized in that:
Also comprise digit time slot automatic electric-level control module, it is connected with described synchronization module, uplink and downlink amplifying circuit respectively, described digit time slot automatic electric-level control module receives the frame synchronization index signal of synchronization module, produces time slit instruction signal in conjunction with frame synchronization index signal and uplink and downlink time slot switching point information; Also receive the envelope detection signal that produces by the detecting circuit in the uplink and downlink amplifying circuit; Sample then according to time slit instruction signal output corresponding control information, and to each corresponding envelope detection signal in the uplink and downlink link, obtain the power samples value of each each time slot of relevant position in the uplink and downlink link; Time slit instruction signal during then according to the signal uplink and downlink, time slot power sampled value, automatic electric-level control control starting value, the decay controlling value of each time slot of corresponding each attenuator in the generation uplink and downlink link before each time slot begins; At last according to the decay controlling value, before each time slot begins, produce and send the attenuator control signal in the uplink and downlink amplifying circuit, the pad value of the attenuator of control uplink and downlink amplifying circuit, thus the gain of control uplink and downlink amplifying circuit realizes automatic electric-level control accurately.
5, TD-SCDMA covering system according to claim 4 is characterized in that:
Described digit time slot automatic electric-level control module comprises that power samples control module, power samples ADC submodule, MCU submodule, MCU Control on Communication submodule, time slit instruction signal produce submodule, the time slot pad value produces submodule and the attenuator control signal produces submodule;
The MCU submodule is connected with described monitoring host computer, in order to communicate by letter with described monitoring host computer, obtains the automatic electric-level control control starting value and the uplink and downlink time slot switching point information of uplink and downlink signal, and its output connects the input of MCU Control on Communication submodule;
MCU Control on Communication submodule also extremely produces submodule and time slot pad value generation submodule with the time slit instruction signal that its output is connected respectively with this data forwarding in order to the data that transmit by data/address bus reception MCU submodule;
Time slit instruction signal produces submodule, transmit the uplink and downlink time slot switching point information of coming in order to accept MCU Control on Communication submodule from the MCU submodule, and after the frame synchronization index signal generation time slit instruction signal in conjunction with the synchronization module generation, described time slit instruction signal is transferred to the power samples control submodule and the time slot pad value that are attached thereto respectively produces submodule;
Power samples control submodule, according to the corresponding control signal of the time slit instruction signal generation of importing to power samples ADC submodule, power controlling sampling ADC submodule carries out the time slot power sampling to each road envelope detection signal of input, and will be transferred to the time slot pad value generation submodule that is attached thereto by the power samples value that the transmission of power samples ADC submodule comes;
Power samples ADC submodule, it is connected with the uplink and downlink amplifying circuit, in order to the control of accepting described envelope detection signal and accepting power samples control submodule corresponding envelope detection signal in the uplink and downlink link is carried out power samples, then the power samples value is transferred to described power samples control submodule;
The time slot pad value produces submodule, before each time slot begins, produce the decay controlling value of each time slot of corresponding each attenuator in the uplink and downlink link in order to time slit instruction signal, each time slot power sampled value, automatic electric-level control control starting value, and transmit it to the attenuator control signal generation submodule that is attached thereto according to input;
The attenuator control signal produces submodule, it is connected with the uplink and downlink amplifying circuit, in order to according to the decay controlling value, before each time slot begins, system is produced the attenuator control signal, and in the uplink and downlink amplifying circuit of feed-in uplink and downlink link, in order to the gain of control uplink and downlink amplifying circuit.
6, TD-SCDMA covering system according to claim 5 is characterized in that: described MCU communicator module, time slit instruction signal produce submodule, the time slot pad value produces submodule and power samples control submodule is integrated in the same control chip.
7, TD-SCDMA covering system according to claim 6 is characterized in that: described control chip be among FPGA, CPLD, the EPLD any one.
8, according to any described TD-SCDMA covering system in the claim 5 to 7, it is characterized in that: described attenuator control signal can be analog signal or digital signal, decides according to concrete covering system needs.
9, according to any described TD-SCDMA covering system in the claim 5 to 7, it is characterized in that: described up amplifying circuit can be may one of make up arbitrarily in low noise amplifier, frequency selection circuit, the power amplifier.
10, according to any described TD-SCDMA covering system in the claim 5 to 7, it is characterized in that: described descending amplifying circuit can be may one of make up arbitrarily in low noise amplifier, frequency selection circuit, the power amplifier.
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| CN101222251B (en) * | 2007-11-30 | 2011-11-23 | 深圳国人通信有限公司 | Method and system for single time slot numerically controlling attenuation |
| CN101252378B (en) * | 2008-03-19 | 2012-08-22 | 南京东大宽带通信技术有限公司 | Closed loop automatic level control method and apparatus for TDD mode communicating system |
| CN107182064A (en) * | 2016-03-09 | 2017-09-19 | 上海大唐移动通信设备有限公司 | Radio frequency time slot power detection method and radio frequency time slot power detection means |
| CN110572224A (en) * | 2019-08-22 | 2019-12-13 | 三维通信股份有限公司 | Method, device, system and readable storage medium for reducing base station receiving background noise |
| CN111669134A (en) * | 2020-06-02 | 2020-09-15 | 京信通信系统（中国）有限公司 | Power amplifier power control method, system, equipment and storage medium in TDD mode |
| CN114124248A (en) * | 2021-11-29 | 2022-03-01 | 上海创远仪器技术股份有限公司 | System for realizing precise control aiming at high peak-to-average ratio signal in vector signal generator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101222251B (en) * | 2007-11-30 | 2011-11-23 | 深圳国人通信有限公司 | Method and system for single time slot numerically controlling attenuation |
| CN101252378B (en) * | 2008-03-19 | 2012-08-22 | 南京东大宽带通信技术有限公司 | Closed loop automatic level control method and apparatus for TDD mode communicating system |
| CN107182064A (en) * | 2016-03-09 | 2017-09-19 | 上海大唐移动通信设备有限公司 | Radio frequency time slot power detection method and radio frequency time slot power detection means |
| CN110572224A (en) * | 2019-08-22 | 2019-12-13 | 三维通信股份有限公司 | Method, device, system and readable storage medium for reducing base station receiving background noise |
| CN110572224B (en) * | 2019-08-22 | 2022-03-15 | 三维通信股份有限公司 | Method, device, system and readable storage medium for reducing base station receiving background noise |
| CN111669134A (en) * | 2020-06-02 | 2020-09-15 | 京信通信系统（中国）有限公司 | Power amplifier power control method, system, equipment and storage medium in TDD mode |
| CN111669134B (en) * | 2020-06-02 | 2023-10-20 | 京信网络系统股份有限公司 | Method, system, equipment and storage medium for controlling power of power amplifier under TDD system |
| CN114124248A (en) * | 2021-11-29 | 2022-03-01 | 上海创远仪器技术股份有限公司 | System for realizing precise control aiming at high peak-to-average ratio signal in vector signal generator |
| CN114253344A (en) * | 2021-12-06 | 2022-03-29 | 广州芯德通信科技股份有限公司 | Method and system for improving PCM (pulse code modulation) gap signal noise of IAD (integrated access device) |
| CN114253344B (en) * | 2021-12-06 | 2022-08-19 | 广州芯德通信科技股份有限公司 | Method and system for improving PCM (pulse code modulation) gap signal noise of IAD (inter-integrated access device) |
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