CN1905162A - Method for mfg. non-volatile memory body - Google Patents
Method for mfg. non-volatile memory body Download PDFInfo
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- CN1905162A CN1905162A CN 200510087353 CN200510087353A CN1905162A CN 1905162 A CN1905162 A CN 1905162A CN 200510087353 CN200510087353 CN 200510087353 CN 200510087353 A CN200510087353 A CN 200510087353A CN 1905162 A CN1905162 A CN 1905162A
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- volatility memory
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Abstract
The invention relates to a nonvolatile memory manufacturing method, firstly forming a first dielectric layer and a virtual gate layer in turn on a substrate; then, defining plural virtual gates on the virtual gate layer; successively, using the virtual gates as mask to form a doped region in the substrate; forming a second dielectric layer on the first dielectric layer corresponding to the doped region; removing the virtual gate layer to expose part of the first dielectric layer; and forming a conductor layer on the substrate to cover the two dielectric layers.
Description
Technical field
The invention relates to a kind of manufacture method of memory body, and particularly relevant for a kind of manufacture method of non-volatility memory.
Background technology
Memory body is as the term suggests be in order to store data or the semiconductor element of data.When the function of computer microprocessor more and more stronger, when formula that software carried out and computing are more and more huger, the demand of memory body is also just more and more higher, for the big and cheap memory body of manufacturing capacity to satisfy the trend of this demand, make the technology and the processing procedure of memory cell, become semiconductor science and technology and continued toward the actuating force of high integration challenge.
In various memory body products, has the actions such as depositing in, read or erase that to carry out repeatedly data, and the non-volatility memory of the advantage that the data that deposits in also can not disappear after outage, become PC and electronic equipment a kind of memory cell of extensively adopting.
Figure 1A to Fig. 1 E illustrate is the generalized section of the manufacturing process of known a kind of non-volatility memory element.
At first, please refer to Figure 1A, a substrate 100 is provided, be formed with channel isolating structure (not illustrating) in this substrate 100 and define active region.Then, in substrate 100, form one deck silicon oxide layer 102.Then, on silicon oxide layer 102, form one deck first polysilicon layer (poly1) 104, on first polysilicon layer 104, form one deck silicon nitride layer 106.
Afterwards, please refer to Figure 1B, form a patterned light blockage layer (not illustrating) on silicon nitride layer 106, and be the cover curtain with the patterned light blockage layer, patterned sin layer 106 is to form silicon nitride layer 106a.After removing patterned light blockage layer, serve as the cover curtain with silicon nitride layer 106a again, first polysilicon layer 104 is carried out etch process, to form the first polysilicon layer 104a.
Then, please refer to Fig. 1 C, serves as the cover curtain with silicon nitride layer 106a, forms a plurality of source/drain 108 in substrate 100.Then, in substrate 100, form one dielectric layer 110 with high density plasma enhanced chemical vapor deposition method (HDP-CVD).
Subsequently, please refer to Fig. 1 D, carry out a planarization processing procedure, to remove part dielectric layer 110 to the drift angle that exposes silicon nitride layer 106a.Then, carry out a wet etch process again, to remove part dielectric layer 110, to form dielectric layer 110a in source/drain 108 tops.Afterwards, remove silicon nitride layer 106a.
Continue it, please refer to Fig. 1 E, form second polysilicon layer (poly3) 112 in substrate 100 tops, wherein second polysilicon layer 112 and the first polysilicon layer 104a vertical interlaced are the character lines (word line) of memory cell to regard.Afterwards, more can carry out the relevant processing procedure of known non-volatility memory, known about these processing procedures by knowing this skill person, therefore repeat no more in this.
Yet, have following problem at the processing procedure of above-mentioned formation non-volatility memory element:
In the step of definition first polysilicon layer 104, often because of problems such as etch process error or control are difficult for cause residual polycrystalline silicon (residue), and make that the formed first polysilicon layer 104a is slope profile (taper profile) (arrow 113 shown in Figure 1B).Thus, when follow-up formation second polysilicon layer 112 (character line), then can produce a bridge joint (bridge) phenomenon between character line and the character line, and cause that leakage current (current leakage) reduces the reliability (reliability) of element.
In addition, the problem (arrow 114 shown in Figure 1B) that accessory substance in the etch process is residual, can cause in the processing procedure of subsequent etch dielectric layer 110, etchant forms the hole (arrow 116 shown in Fig. 1 D) that runs through silicon oxide layer 102 to 102 reactions of etch byproducts and oxide layer.Therefore, when then forming second polysilicon layer 112 (character line), can cause second polysilicon layer 112 (character line) to insert (arrow 118 shown in Fig. 1 E) in the hole, and make second polysilicon layer 112 (character line) and 100 electrical undesired connections of substrate, and then cause the element short circuit, and cause component failure, influence the product yield.
Summary of the invention
Purpose of the present invention is exactly that a kind of manufacture method of non-volatility memory is being provided, and can avoid the variety of problems that causes because of residual polycrystalline silicon, and cause the element short circuit, and then influence the product yield.
The present invention proposes a kind of manufacture method of non-volatility memory, is prior to forming first dielectric layer and virtual gate layer in the substrate in regular turn.Then, the defining virtual gate layer is to form a plurality of virtual gates.Then, serve as the cover curtain with virtual gate, in substrate, form a doped region.Afterwards, on first dielectric layer of corresponding doped region, form second dielectric layer.Continue it, remove virtual gate layer, expose the part of first dielectric layer surface.Subsequently, form a conductor layer in the substrate top, to cover second dielectric layer and first dielectric layer.
Described according to embodiments of the invention, the material of above-mentioned virtual gate layer for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.
Described according to embodiments of the invention, the first above-mentioned dielectric layer for example is a tunnel oxide.Wherein, the material of tunnel oxide for example is a silica, and its formation method for example is thermal oxidation method (thermaloxidation).
Described according to embodiments of the invention, the first above-mentioned dielectric layer for example is a composite dielectric layer.Wherein, composite dielectric layer for example is that (the formation method of its composite dielectric layer for example is chemical vapour deposition technique to silicon oxide/silicon nitride/silicon oxide for oxide-nitride-oxide, ONO) layer.
Described according to embodiments of the invention, the above-mentioned method that removes virtual gate for example is to carry out an etch process.
Described according to embodiments of the invention, the material of the second above-mentioned dielectric layer for example is a silica, and its formation method for example is high density plasma enhanced chemical vapor deposition method (HDP-CVD).
Described according to embodiments of the invention, the material of above-mentioned conductor layer for example is a polysilicon, and its formation method for example is a chemical vapour deposition technique.
Described according to embodiments of the invention, the formation method of above-mentioned doped region for example is an ionic-implantation.
The present invention utilizes to form virtual gate earlier with as known first polysilicon layer (poly1), then, after removing virtual gate, in substrate, form conductor layer, conductor layer can be inserted the position of former virtual gate, to form the first known polysilicon layer and second polysilicon layer (character line) simultaneously.Thus, can avoid producing the defectives such as hole that run through first dielectric layer, and make electrical undesired connection of conductive layer and substrate, and then cause the element problem of short-circuit.
On the other hand, owing to can have comparatively vertical profile (vertical profile) with the formed virtual gate of dielectric material, therefore do not have the known problem that causes bridge joint between the character line (bridge) because of residual polycrystalline silicon (residue), and then cause the element short circuit, influence the product yield.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A to Fig. 1 E illustrate is the cutaway view of the manufacturing process of known a kind of non-volatility memory element.
Fig. 2 A to Fig. 2 G is the cutaway view according to the manufacturing process of the non-volatility memory that the present invention illustrated.
100,200: substrate
102: silicon oxide layer
104,104a: first polysilicon layer
106,106a: silicon nitride layer
108: source/drain
110,110a, 202,208,209: dielectric layer
112: the second polysilicon layers
113,114,116,118: arrow
203: virtual gate layer
204: virtual gate
206: doped region
210: conductor layer
Embodiment
Fig. 2 A to Fig. 2 G is the generalized section according to the manufacturing process of the non-volatility memory that the present invention illustrated.
At first, please refer to Fig. 2 A, a substrate 200 is provided, be formed with channel isolating structure (not illustrating) in this substrate 200 and define active region.Then, in substrate 200, form dielectric layer 202.Wherein, dielectric layer 202 can for example be a tunnel oxide, and its material for example is a silica, and the formation method for example is thermal oxidation method (thermal oxidation).In one embodiment, dielectric layer 202 also can for example be a composite dielectric layer, and composite dielectric layer for example is that (and its formation method for example is a chemical vapour deposition technique to silicon oxide/silicon nitride/silicon oxide for oxide-nitride-oxide, ONO) layer.
Afterwards, please continue A, on dielectric layer 202, form a virtual gate layer 203 with reference to Fig. 2.Wherein, the material of virtual gate layer 203 for example is silicon nitride or other suitable dielectric materials, and its formation method for example is a chemical vapour deposition technique.
Then, please refer to Fig. 2 B, defining virtual gate layer 203 is to form a plurality of virtual gates 204.Wherein, the formation method of virtual gate 204 for example is to form patterned light blockage layer (not illustrating) on virtual gate layer 203, carries out an etch process then and forms.
Then, please refer to Fig. 2 C, serves as the cover curtain with virtual gate 204, forms doped region 206 in substrate 200, and the formation method of doped region 206 for example is to carry out an ionic-implantation.Wherein, doped region 206 is the source/drain as memory body.
Subsequently, please refer to Fig. 2 D, form dielectric layer 208 in substrate 200 tops, the material of dielectric layer 208 for example is a silica, and its formation method for example is high density plasma enhanced chemical vapor deposition method (HDP-CVD).
Then, please refer to Fig. 2 E, carry out a cmp (CMP) processing procedure, to remove part dielectric layer 208 to the drift angle that exposes virtual gate 204.
Then, please refer to Fig. 2 F, carry out an anisotropic etching processing procedure, remove part dielectric layer 208, on the dielectric layer 202 of corresponding doped region 206, to form dielectric layer 209.Then, remove virtual gate 204, expose part dielectric layer 202 surfaces.Wherein, the method that removes virtual gate 204 for example is to carry out an etch process.
Continue it, please refer to Fig. 2 G, form a conductor layer 210, cover dielectric layer 202 and dielectric layer 209 in substrate 200 tops.Wherein, the material of conductor layer 210 for example is a polysilicon, and its formation method for example is a chemical vapour deposition technique.
Afterwards, more can carry out the relevant processing procedure of known non-volatility memory, known about these processing procedures by knowing this skill person, therefore repeat no more in this.
Particularly, the present invention is used as the first known polysilicon layer with virtual gate 204 earlier.Then, after removing virtual gate 204, form conductor layer 210 in substrate 200, conductor layer 210 can be inserted the position of former virtual gate 204, to form the first known polysilicon layer and second polysilicon layer (character line) simultaneously.Describe in detail, the more known secondary polysilicon processing procedure (double polyprocess) of manufacture method of the present invention is more simple and easy, and it only need carry out a polysilicon processing procedure (single poly process), therefore can comparatively save the processing procedure cost.
On the other hand, owing to can have comparatively vertical profile (vertical profile) with the formed virtual gate 204 of dielectric material, therefore do not have the known problem that causes bridge joint between the character line (bridge) because of residual polycrystalline silicon (residue), and then cause the element short circuit, influence the product yield.
And, because manufacture method of the present invention is to carry out the polysilicon processing procedure in successive process one time, to form the first known polysilicon layer and second polysilicon layer (character line) simultaneously, therefore can not produce the defectives such as hole that run through dielectric layer 202, and make electrical undesired connection of conductive layer and substrate, and then cause the element problem of short-circuit, and cause component failure, influence the product yield.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (15)
1, a kind of manufacture method of non-volatility memory is characterized in that it comprises:
In a substrate, form one first dielectric layer;
On this first dielectric layer, form a virtual gate layer;
Define this virtual gate layer, to form most virtual gates;
With those virtual gates is the cover curtain, forms a doped region in this substrate;
In on should this first dielectric layer of doped region, forming one second dielectric layer;
Remove those virtual gates, expose this first dielectric layer surface of part; And
Form a conductor layer in this substrate top, cover this second dielectric layer and this first dielectric layer.
2, the manufacture method of non-volatility memory according to claim 1 is characterized in that the material of wherein said virtual gate layer comprises silicon nitride.
3, the manufacture method of non-volatility memory according to claim 1 is characterized in that the formation method of wherein said virtual gate layer comprises chemical vapour deposition technique.
4, the manufacture method of non-volatility memory according to claim 1 is characterized in that wherein said first dielectric layer comprises a tunnel oxide.
5, the manufacture method of non-volatility memory according to claim 4 is characterized in that the material of wherein said tunnel oxide comprises silica.
6, the manufacture method of non-volatility memory according to claim 4 is characterized in that the formation method of wherein said tunnel oxide comprises thermal oxidation method (thermal oxidation).
7, the manufacture method of non-volatility memory according to claim 1 is characterized in that wherein said first dielectric layer comprises a composite dielectric layer.
8, the manufacture method of non-volatility memory according to claim 7 is characterized in that wherein said composite dielectric layer comprises silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, ONO) layer.
9, the manufacture method of non-volatility memory according to claim 7 is characterized in that the formation method of wherein said composite dielectric layer comprises chemical vapour deposition technique.
10, the manufacture method of non-volatility memory according to claim 1, the method that it is characterized in that wherein removing those virtual gates comprises carries out an etch process.
11, the manufacture method of non-volatility memory according to claim 1 is characterized in that the material of wherein said second dielectric layer comprises silica.
12, the manufacture method of non-volatility memory according to claim 1 is characterized in that the formation method of wherein said second dielectric layer comprises high density plasma enhanced chemical vapor deposition method (HDP-CVD).
13, the manufacture method of non-volatility memory according to claim 1 is characterized in that the material of wherein said conductor layer comprises polysilicon.
14, the manufacture method of non-volatility memory according to claim 1 is characterized in that the formation method of wherein said conductor layer comprises chemical vapour deposition technique.
15, the manufacture method of non-volatility memory according to claim 1 is characterized in that the formation method of wherein said doped region comprises ionic-implantation.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100873530A CN100411150C (en) | 2005-07-28 | 2005-07-28 | Method for mfg. non-volatile memory body |
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| CNB2005100873530A CN100411150C (en) | 2005-07-28 | 2005-07-28 | Method for mfg. non-volatile memory body |
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| Publication Number | Publication Date |
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| CN1905162A true CN1905162A (en) | 2007-01-31 |
| CN100411150C CN100411150C (en) | 2008-08-13 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6461905B1 (en) * | 2002-02-22 | 2002-10-08 | Advanced Micro Devices, Inc. | Dummy gate process to reduce the Vss resistance of flash products |
| US6475863B1 (en) * | 2002-05-17 | 2002-11-05 | Advanced Micro Devices, Inc. | Method for fabricating self-aligned gate of flash memory cell |
| US6787860B1 (en) * | 2003-05-01 | 2004-09-07 | Macronix International Co., Ltd. | Apparatus and method for inhibiting dummy cell over erase |
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Granted publication date: 20080813 Termination date: 20190728 |