CN1270369C - Method of integrating storage unit data region and peripheral circuit region in space reducing technology - Google Patents
Method of integrating storage unit data region and peripheral circuit region in space reducing technology Download PDFInfo
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- CN1270369C CN1270369C CN 03121236 CN03121236A CN1270369C CN 1270369 C CN1270369 C CN 1270369C CN 03121236 CN03121236 CN 03121236 CN 03121236 A CN03121236 A CN 03121236A CN 1270369 C CN1270369 C CN 1270369C
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Abstract
The present invention relates to a method for integrating a storage unit array region and a peripheral circuit region in a space reduction technology. The method forms a cover curtain layer to cover a substrate and expose the storage unit array region before the step of forming a macromolecule layer for the second time in the space reduction technology. Furthermore, the cover curtain layer is covered on the edge region of the storage unit array region in an overlapping mode; thus, a conductor layer below the covered region of the storage unit array region by the cover curtain layer is not etched through the shadow of the cover curtain layer. Consequently, the storage unit array region and the peripheral circuit region can be really electrically connected in subsequent technologies.
Description
Technical field
The invention relates to a kind of method of in semiconductor device, dwindling memory cell arrays live width and line-spacing, and particularly relevant for the method for in the spacing reduction process, integrating memory cell arrays district and periphery circuit region.
Background technology
Requiring under the more and more higher situation of circuit integration, the design of entire circuit size of devices also is forced to advance toward the direction that size does not stop to dwindle.Yet, the live width of semiconductor device and line-spacing are subject to the critical dimension of little shadow exposure and are difficult to dwindle downwards again, therefore, the various spacings of dwindling live width and line-spacing that are relevant to are dwindled (pitch reduction) process quilt and are put forward, and utilize these a little spacings to dwindle technology, can for example be memory cell arrays with live width in the semiconductor device and line-spacing, be reduced into 1/2nd of exposure critical dimension.
Yet, in known spacing reduction process, all have only announcement how by the spacing reduction process with the live width of dwindling the conductor layer (for example being grid) in the memory cell arrays and the method for line-spacing, to how not link and disclose the conductor layer that this spacing dwindles with perimeter circuit, that is be, in relevant with memory cell arrays now spacing reduction process, there is no the memory cell arrays district electric connection that effective method can make periphery circuit region and spacing dwindle.
Summary of the invention
Therefore, purpose of the present invention is exactly that a kind of method of integrating memory cell arrays district and periphery circuit region in the spacing reduction process is being provided, when conductor layer spacing in the memory cell arrays is dwindled.The memory cell arrays district that periphery circuit region and spacing are dwindled electrically connects smoothly.
Another object of the present invention is exactly a kind of method of integrating memory cell arrays district and periphery circuit region in the spacing reduction process to be provided, can to use existing exposure technology, forms the peripheral circuit pattern of the memory cell arrays electric connection of dwindling with spacing.
The invention provides a kind of method of in the spacing reduction process, integrating memory cell arrays district and periphery circuit region, the method provides a substrate, wherein in substrate, form one first mask layer that a gate dielectric layer, a conductor layer, stop layer, a sacrifice layer and patterning in regular turn, again formation one first macromolecule layer on first mask layer.Then, be etching mask with first macromolecule layer, remove the partial sacrifice layer, stop the layer with conductor layer to exposing gate dielectric layer to form an opening, remove first mask layer and first macromolecule layer again.Then, in opening, form a dielectric layer, remove sacrifice layer again and stop layer with exposure., in substrate in form one second mask layer to expose memory cell arrays district, on second mask layer and dielectric layer, form one second macromolecule layer more thereafter.Afterwards, be etching mask with second macromolecule layer, remove the part stop the layer with conductor layer to exposing gate dielectric layer, remove second mask layer and second macromolecule layer again.After this, in substrate, form one the 3rd mask layer to define the pattern of peripheral pattern area, be etching mask with the 3rd mask layer again, remove and partly stop layer and conductor layer to exposing gate dielectric layer, most bar peripheral circuit lines to form most bar character lines and to electrically connect individually with character line in substrate remove the 3rd mask layer and dielectric layer again.
And, in above-mentioned preferred embodiment, the present invention can also only be etched in lithography technology till the surface of exposing conductor layer, is mask to stop layer more at last, once defines the peripheral circuit pattern (peripheral circuit line) of all conductor layers to define character line and concatenation character line.
Even, in above-mentioned preferred embodiment, the overlapping fringe region that is covered in the memory cell arrays district of second mask layer wherein.In addition, in above-mentioned preferred embodiment, the mode that these a little peripheral circuit lines are arranged with interleaved is connected in the two ends of these a little character lines individually.
From the above, because the present invention forms mask layer with the overlapping fringe region that is covered in memory cell arrays in the spacing reduction process, therefore can in the etch process that continues, keep the conductor layer that is capped part, can electrically connect with the character line in memory cell arrays district with the periphery circuit region pattern (peripheral circuit line) of guaranteeing follow-up formation.
And, because the mode that the pattern of periphery circuit region is arranged with interleaved is connected in the two ends of character line, therefore, in the step of the pattern that forms periphery circuit region, even use existing general exposure technology, also under the situation about can dwindle, form the periphery circuit region pattern that memory cell arrays district that live width and line-spacing therewith dwindle electrically connects smoothly at the live width and the line-spacing in memory cell arrays district.
Description of drawings
Figure 1A to Fig. 1 J illustrate is a kind of top view of integrating the manufacturing process of memory cell arrays district and periphery circuit region in the spacing reduction process of preferred embodiment of the present invention.
Fig. 2 A to Fig. 2 J illustrate is a kind of profile of integrating the manufacturing process of memory cell arrays district and periphery circuit region in the spacing reduction process of preferred embodiment of the present invention.
The drawing reference numeral explanation
100: substrate 102: gate dielectric layer
104,104a, 104b, 104c: conductor layer 114: dielectric layer
106,106a, 106b, 106c: stop layer
108,108a: sacrifice layer 110,116,122: mask layer
112,118: macromolecule layer 113,120: opening
Embodiment
Figure 1A to Fig. 1 J illustrate is a kind of top view of integrating the manufacturing process of memory cell arrays district and periphery circuit region in the spacing reduction process of preferred embodiment of the present invention, and Fig. 2 A to Fig. 2 J illustrate is a kind of profile of integrating the manufacturing process of memory cell arrays district and periphery circuit region in the spacing reduction process of preferred embodiment of the present invention.Wherein Fig. 2 A to Fig. 2 J illustrate is the structure of Figure 1A to Fig. 1 J profile along the I-I tangent line.
At first, please provide a substrate 100, wherein in substrate 100, be formed with gate dielectric layer 102, conductor layer 104 in regular turn, stop layers 106, the mask layer 110 of sacrifice layer 108 and patterning simultaneously with reference to Figure 1A and Fig. 2 A.Wherein the material of gate dielectric layer 102 for example is a silica, and conductor layer 104 for example is to be used to the grid that subsequent step forms memory cell arrays, and its material for example is the composite bed of polysilicon or polysilicon and tungsten silicide.The material that stops layer 106 for example is silica or silicon nitride, and the material of sacrifice layer 108 for example is a polysilicon, and the material of mask layer 110 for example is a photo anti-corrosion agent material.
Then, please form one deck macromolecule layer 112 on the mask layer 110 of patterning simultaneously with reference to Figure 1B and Fig. 2 B, the method that wherein forms this macromolecule layer 112 for example is a chemical vapour deposition technique, and this macromolecule layer 112 is slightly conformal in the mask layer 110 of patterning.
Then, please be simultaneously with reference to Fig. 1 C and Fig. 2 C, with macromolecule layer 112 is mask, carry out etch process to remove sacrifice layer 108 partly, to stop layer 106 and conductor layer 104, to form sacrifice layer 108a, to stop the opening 113 of a layer 106a, conductor layer 104a and strip, then macromolecule layer 112 is removed.
Then, please be simultaneously with reference to Fig. 1 D and Fig. 2 D, in opening 113, form dielectric layer 114, wherein the material of dielectric layer 114 for example is that silica, silicon nitride, organic compound thin film are formed by photo anti-corrosion agent material or bottom antireflection material etc., the method of its formation for example is the difference according to the use material, with method of spin coating or chemical vapour deposition technique and form, in opening 113, go up to form a dielectric materials layer (not icon), then remove dielectric materials layer outside the opening 113 again with formation dielectric layer 114 with sacrifice layer 108a.And wherein employed dielectric layer 114 is preferably and uses with sacrifice layer 108a, stops layer 106a and dielectric layer 104a has the material of high etching selectivity.Even sacrifice layer 108a is preferably use and stops the material that layer 106a has high etching selectivity.
Shown in Figure 1A to Fig. 1 D, the dielectric layer 114 that wherein is formed at the memory cell arrays outside has the width of broad in design, and the reason of the broad that herein dielectric layer outside the memory cell arrays 114 is designed is to make the technology of follow-up formation mask layer to have bigger nargin (being described in detail later).
Then, please be simultaneously with reference to Fig. 1 E and Fig. 2 E, remove sacrifice layer 108a to expose stop layer 106a till, the method for wherein removing sacrifice layer 108a for example use to sacrifice layer 108a with stop the etching solution that layer 106a has high etching selectivity, with wet etching sacrifice layer 108a etching is removed.
Then, please refer to Fig. 1 F and Fig. 2 F, form mask layer 116 (being not illustrated among Fig. 2 F) in substrate 100, wherein the material of mask layer 116 for example is a photo anti-corrosion agent material.And, shown in Fig. 1 F, the overlapping fringe region that is covered in memory cell arrays of this mask layer 116 (shown in Fig. 1 F comparatively thick frame line) wherein, that is be the two ends that are covered in the dielectric layer 114 of strip, and along the trend of dielectric layer 114 length directions, overlapping is covered on the dielectric layer 114 in the outside, memory cell arrays district.
Then, please be simultaneously with reference to Fig. 1 G and Fig. 2 G, form one deck macromolecule layer 118 on mask layer 116 and dielectric layer 114, the method that wherein forms this macromolecule layer 118 for example is a chemical vapour deposition technique, and this macromolecule layer 118 is slightly conformal in mask layer 116 and dielectric layer 114.
Then, please be mask with macromolecule layer 118 simultaneously with reference to Fig. 1 H and Fig. 2 H, carry out etch process with remove partly stop layer 106a and conductor layer 104a, stop the opening 120 of a layer 106b, conductor layer 104b and strip with formation.And then removal macromolecule layer 118.
Shown in Fig. 1 F to Fig. 1 H, because at the formed mask layer 116 overlapping fringe regions (that is being to comprise the predetermined two ends that form character line) that are covered in memory cell arrays of Fig. 1 F, therefore, the conductor layer 104a that can keep in the etch process of Fig. 1 G and Fig. 1 H below the mask layer 116 overlapping cover parts is not etched, and is guaranteed that the periphery circuit region of follow-up formation can electrically connect with the character line in memory cell arrays district.And, because the dielectric layer 114 that is positioned at the outside, memory cell arrays district has the width of broad, therefore, mask layer 116 can be easier to along the trend of dielectric layer 114 length directions, part covers on the dielectric layer 114 that is positioned at the outside, memory cell arrays district, can remove fully in follow-up technology to guarantee the conductive layer outside the memory cell arrays district.
Then, please in substrate 100, form the mask layer 122 (as slightly shown in the frame line of Fig. 1 I) of patterning, be connected pattern (peripheral circuit line) in order to the character line that defines this memory cell arrays district and periphery circuit region simultaneously with reference to Fig. 1 I and Fig. 2 I.Wherein the material of this mask layer 122 for example is a photo anti-corrosion agent material.
Then, please be simultaneously with reference to Fig. 1 J and Fig. 2 J, with mask layer 122 is mask, and stop a layer 106b, the conductor layer 104b that remove outside the mask layer 122 stop layer 106c and conductor layer 104c to form in substrate 100, that is are the peripheral circuit lines that forms character line and concatenation character line in substrate 100.It should be noted that, stop layer 106c pattern as can be known by mask layer 122 patterns of above-mentioned Fig. 1 I and Fig. 1 J, because the mode that the peripheral circuit line is arranged with interleaved is connected in the two ends of character line individually, therefore, in the step of the pattern that forms periphery circuit region, even use existing exposure technology, also form the periphery circuit region pattern smoothly under the situation about can dwindle at the live width and the line-spacing in memory cell arrays district.
And, in the invention described above preferred embodiment, wherein in Fig. 1 C, Fig. 2 C and Fig. 1 H, in the step of Fig. 2 H, in lithography technology, remove the conductor layer 104 (104a) of part, yet the present invention is not limited thereto, the present invention also can be in the lithography technology of Figure 1A to Fig. 1 I, only be etched to till the surface of exposing conductor layer 104, that is be conductor layer 104 not to be carried out etching, then in the step of Fig. 1 J, be mask definition stopping layer 106c till expose conductor layer 104 surfaces with mask layer 122 earlier, after removal dielectric layer 114, is that mask is to define the peripheral circuit line of character line and concatenation character line to stop layer 106c then again.
Even in above-mentioned preferred embodiment, layer 106c that stop in Fig. 1 J and Fig. 2 J do not remove, yet layer 106c that stop among Fig. 1 J and Fig. 2 J can also be removed.
In sum, the present invention has following advantage at least:
1. in preferred embodiment of the present invention, because the present invention forms before secondary macromolecule layer 118 in the spacing reduction process, form mask layer 116 with the overlapping fringe region that is covered in memory cell arrays, therefore can in the etch process that continues, keep the conductor layer 104a that is capped the part below and can electrically connect with the character line in memory cell arrays district with the periphery circuit region pattern (peripheral circuit line) of guaranteeing follow-up formation.
2. in preferred embodiment of the present invention, because periphery circuit region pattern (peripheral circuit line) is connected in the two ends of character line in the mode of interleaved, therefore, in the step of the pattern that forms periphery circuit region, even use existing exposure technology, also under the situation about can dwindle, form the periphery circuit region pattern that memory cell arrays district that live width and line-spacing therewith dwindle electrically connects smoothly at the live width and the line-spacing in memory cell arrays district.
Though the present invention with preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (16)
1. a method of integrating memory cell arrays district and periphery circuit region in the spacing reduction process is characterized in that comprising the following steps:
One substrate is provided, wherein in this substrate, forms one first cover curtain layer that a gate dielectric layer, a conductor layer, stop layer, a sacrifice layer and patterning in regular turn;
On this first mask layer, form one first macromolecule layer;
With this first macromolecule layer is etching mask, remove the part this sacrifice layer, this stop the layer with this conductor layer to exposing this gate dielectric layer to form an opening;
Remove this first mask layer and this first macromolecule layer;
In this opening, form a dielectric layer;
Remove this sacrifice layer and stop layer to expose this;
In this substrate, form one second mask layer to expose this memory cell arrays district;
On this second mask layer and this dielectric layer, form one second macromolecule layer;
With this second macromolecule layer is etching mask, remove the part this stop the layer with this conductor layer to exposing this gate dielectric layer;
Remove this second mask layer and this second macromolecule layer;
In this substrate, form one the 3rd mask layer to define the pattern of this periphery pattern area;
With the 3rd mask layer is etching mask, and this stops layer and this conductor layer to exposing this gate dielectric layer to remove part, with in this substrate, form most bar character lines and with the indivedual most bar peripheral circuit lines that electrically connect of those character lines; And
Remove the 3rd mask layer and this dielectric layer.
2, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 1 is characterized in that the overlapping fringe region that is covered in this memory cell arrays district of this second mask layer.
3, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 1 is characterized in that those peripheral circuit lines are connected in the two ends of those character lines individually in the mode of interleaved arrangement.
4, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 1 is characterized in that this sacrifice layer and this stop layer and have different etching selectivities.
5, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 4 is characterized in that this material that stops layer comprising silica or silicon nitride.
6, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 1 is characterized in that this dielectric layer and this sacrifice layer, this stops layer and this conductor layer has different etching selectivities.
7, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 6 is characterized in that the material of this dielectric layer comprises silica, silicon nitride or organic compound thin film.
8, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 1 is characterized in that this conductor layer comprises polysilicon layer or the composite bed of being made up of polysilicon and tungsten silicide.
9. a method of integrating memory cell arrays district and periphery circuit region in the spacing reduction process is characterized in that comprising the following steps:
One substrate is provided, wherein in this substrate, forms one first mask layer that a gate dielectric layer, a conductor layer, stop layer, a sacrifice layer and patterning in regular turn;
On this first mask layer, form one first macromolecule layer;
With this first macromolecule layer is etching mask, removes this sacrifice layer of part and stops layer to exposing this conductor layer to form an opening with this;
Remove this first mask layer and this first macromolecule layer;
In this opening, form a dielectric layer;
Remove this sacrifice layer and stop layer to expose this;
In this substrate, form one second mask layer to expose this memory cell arrays district;
On this second mask layer and this dielectric layer, form one second macromolecule layer;
With this second macromolecule layer is etching mask, and this stops layer to expose this conductor layer to remove part;
Remove this second mask layer and this second macromolecule layer;
In this substrate, form one the 3rd mask layer to define the pattern of this periphery pattern area;
With the 3rd mask layer is etching mask, and this stops layer to expose this conductor layer to remove part;
Remove the 3rd mask layer and this dielectric layer; And
Stopping layer with remaining this is mask, removes this conductor layer of part to expose this gate dielectric layer, with the most bar peripheral circuit lines that form most bar character lines and electrically connect individually with those character lines in this substrate.
10, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 9 is characterized in that the overlapping fringe region that is covered in this memory cell arrays district of this second mask layer.
11, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 9 is characterized in that those peripheral circuit lines are connected in the two ends of those character lines individually in the mode of interleaved arrangement.
12, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 9 is characterized in that this sacrifice layer and this stop layer and have different etching selectivities.
13, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 12 is characterized in that this material that stops layer comprising silica or silicon nitride.
14, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 9 is characterized in that this dielectric layer and this sacrifice layer, this stops layer and this conductor layer has different etching selectivities.
15, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 14 is characterized in that the material of this dielectric layer comprises silica, silicon nitride or organic compound thin film.
16, the method for integrating memory cell arrays district and periphery circuit region in the spacing reduction process as claimed in claim 9 is characterized in that this conductor layer comprises polysilicon layer or the composite bed of being made up of polysilicon and tungsten silicide.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 03121236 CN1270369C (en) | 2003-03-28 | 2003-03-28 | Method of integrating storage unit data region and peripheral circuit region in space reducing technology |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 03121236 CN1270369C (en) | 2003-03-28 | 2003-03-28 | Method of integrating storage unit data region and peripheral circuit region in space reducing technology |
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| CN1534757A CN1534757A (en) | 2004-10-06 |
| CN1270369C true CN1270369C (en) | 2006-08-16 |
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| CN100426466C (en) * | 2006-02-24 | 2008-10-15 | 晶豪科技股份有限公司 | Method for forming flash unit array with reduced word-linepitch |
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Granted publication date: 20060816 Termination date: 20210328 |