CN100426466C - Method for forming flash unit array with reduced word-linepitch - Google Patents
Method for forming flash unit array with reduced word-linepitch Download PDFInfo
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- CN100426466C CN100426466C CNB2006100580074A CN200610058007A CN100426466C CN 100426466 C CN100426466 C CN 100426466C CN B2006100580074 A CNB2006100580074 A CN B2006100580074A CN 200610058007 A CN200610058007 A CN 200610058007A CN 100426466 C CN100426466 C CN 100426466C
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Abstract
This invention relates to a method for forming NAND flash memory devices including: forming a polysilicon layer of a control grating and forming a mask layer on it including multiple distant word line mask patterns for bounding flash memory devices, in which, the distance between word lines is less than the minimum character dimension imaged by an etching technology used in forming at least a part of patterns of the mask layer and the control grating polysilicon layer is etched via the mask layer.
Description
Technical field
The present invention relates to a kind of flash memory device and makes the method for described device.
Background technology
NAND (with non-) type EEPROM (Electrically Erasable Read Only Memory) or flash memory have been developed being used for solid-state a large amount of storage application of portable music player, mobile phone, digital camera etc., and it has been considered to the substitute of hard disk drive (HDD).Therefore, wish that these devices have bigger capacity, lower cost and are used for miniaturization, increase the cell size of dwindling of processing speed.
Usually design NAND apparatus structure makes: (1) each memory cell utilizes a transistor with floating grid and control grid; (2) be arranged at suprabasil memory cell array and providing single contact hole (contact) between the bit line accordingly.Therefore, as comparing,, dwindled the occupied area of memory cell, and can improve integration density although unit interval is limited by selected photoetching (photolithography) technology usually with traditional EEPROM.
United States Patent (USP) 5,050, No. 125 (hereinafter to be referred as ' 125 patents) have disclosed a kind of nonvolatile semiconductor memory, and wherein each bit line comprises a string flash memory cell array (shown in the cross-sectional view of Fig. 4 of ' 125 patents).Cell size or area are defined by the required overlapping area of floating grid and control grid.The cell size of each unit of ' 125 patents can not narrow down to about 4F
2-5F
2Below, wherein " F " is the minimum dimension of optical patterning, minimum feature size (feature size) or live width that photoetching (photolithography) technology of using in can the manufacturing process by ' 125 patents obtains.Minimum feature size is about 90nm at present.The minimum widith of conclusion hypothesis floating grid is about 1F, and the minimum widith at the interval in the floating grid array between the adjacent floating grid also is about 1F, the minimum widith of controlling grid simultaneously is about 1F, and the minimum interval between the adjacent control grid is about 1F, mean that each unit occupies minimum value 2F at least at directions X (towards the horizontal direction of the cross-sectional view of the accompanying drawing 4 of ' 125 patents), and occupy minimum value 2F at least to 2.5F in Y direction (with respect to another two-dimensional directional of the described horizontal direction of the accompanying drawing 4 of ' 125 patents).
The United States Patent (USP) of Haspeslagh has proposed a kind of device with the word line pitch of dwindling 6,580, No. 120, but has utilized complicated many groups word line to form technology.
Therefore, wish to utilize the integration density that can easily integrated technology increases flash array.
Summary of the invention
A kind of method of the NAND of formation type flash memory device comprises: form the control gate polysilicon layer in substrate; On described control gate polysilicon layer, form mask layer, described mask layer comprises the mask pattern of several word lines at interval that define flash memory device, described word line each interval one segment distance X and this distance X are less than minimum feature size F, and described minimum feature size can be by the photoetching process imaging of the selection that is used to form the described mask layer pattern of at least a portion; With by mask layer etching control gate polysilicon layer.Wherein, described mask layer forms step and comprises following steps: form ground floor on described control gate polysilicon layer, and use the described ground floor of described photoetching process patterning to form first group of mask part at interval, described first group of mask at interval partly defines first group of word line at interval, and the distance of F+2X at interval between adjacent described first group of mask part at interval; On the sidewall edge of described first group of mask part at interval, form clearance wall; Form the second layer between described clearance wall, the described second layer defines second group of word line at interval; With remove described clearance wall, form the described mask pattern define described several word lines at interval whereby.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is a part of circuit diagram with flash memory of several nand memory unit.
Fig. 2 is the cross-sectional view of the unit strings of an exemplary memory device, and it demonstrates word line spacer.
Fig. 2 is the cross-sectional view of the unit strings of an exemplary memory device, and it demonstrates word line spacer.
Fig. 3 A～3F illustrates the exemplary method of the structure of a shop drawings 2.
The step of SONOS memory unit is made in Fig. 4 A～4D explanation one.
The main element description of symbols
BL0, BL1: bit line
WL0, WL1, WL2 ..., WLn: word line
SSL, GSL: selection wire
M
Nm: memory cell
SL0, SL1, GSL0, GSL1: select transistor
10: substrate
12: three well areas
14: injection zone
16: gate dielectric
18: memory cell
20a, 20b: select transistor
22,122: floating grid
24,32,34,124: insulating barrier
26,126: the control grid
28,128: silicide layer
30: connector
36: conductive bit
38: interlayer hole
130,130 ', 134: oxide mask
The 132:SiN layer
132 ': clearance wall
The 200:ONO layer
202,206: insulating barrier
204: store layer
F, X: size
Embodiment
With reference to Fig. 1, be depicted as Electrically Erasable Read Only Memory (EEPROM), comprise the memory cell array that is formed on the chip base.To recognize that as the person of ordinary skill in the field Fig. 1 is the circuit diagram of the part of a nand flash memory array.For example all not expressions of the various elements of row and column decoder, sensing circuit and other control circuit, unclear to avoid that announcement of the present invention is thickened.Yet these assemblies are that the person of ordinary skill in the field is known.
Memory array comprises that several are connected to memory cell M
NmAnd parallel bit line BL0, BL1 ..., BLm, the columns of cell position in " n " expression memory array wherein, and " m " represents its line number.Parallel word line WL0, WL1, WL2 ..., WLn insulation is formed in the substrate, so that for being formed at the flash cell M on each cell position
NmForm the control grid.Select transistor SL0, SL1 etc. and GSL0, GSL1 etc. to be formed at each end of bit line BL.
One example memory array is divided into lots of memory " block ".Each block has some " pages or leaves ".One page has lots of memory " unit ".For example, the memory of 1Gb has 1024 blocks, and a block has 64 pages.Each page or leaf has 2K byte (being the 16K position).One word line contains one page or multipage.Each block provides a unit strings or two unit strings on bit line direction.A unit strings has 16,32 or 64.For example under the situation of SONOS memory cell discussed below, a unit stores a position, or stores two positions.
In one embodiment, programme, wipe as follows with the read operation condition:
| Wipe | Programming | Read | |
| The WL that selects | 0V | 20V | 0V |
| Unselected WL | 0V | 10V | 4.5V |
| SSL | Float | VCC | 4.5V |
| GSL | Float | 0V | 4.5V |
| BL (to 0 programming) | Float | 0V | N/A |
| BL (to 1 programming) | Float | VCC | N/A |
| Body (bulk) | 20V | 0V | N/A |
In this program/erase method, Fowler-Nordheim (FN) is worn tunnel be used for the programming of NMOS nand flash memory cell and wipe.During programming, a higher positive voltage is put on the word line of unit of selection.Voltage in one is applied on the unselected word line to open these unit.Earthed voltage or 0V are applied to bit line writing data " 0 ", and apply VCC to write data " 1 ".0V is sent to the passage of the unit of selection, carries out FN and wear tunnel so that electronics is injected into floating grid from passage.When data were " 1 ", word line voltage coupled together passage, and existed insignificant FN to wear the tunnel electric current, so the unit is not programmed.For wiping,, and will select all word line ground connection in the block with the P type trap of the described unit of high voltage bias.Electronics is tunnelled to the substrate of P type trap from floating grid FN.
Fig. 2 is the side cross-sectional view of unit strings.Described unit strings comprises selects transistor 20a, 20b, and wherein several NMOS floating grid flash cells transistors 18 are formed at and select between transistor 20a, the 20b.Although select transistor 20a, 20b to be shown as double-gated transistor, also can use single gate transistor as shown in Figure 1.
In one embodiment, substrate 10 comprises the doped silicon based end of p type, and the doped silicon based end of p type has triple-well (triple well) zone 12 that is formed in the cell array region wherein.Described triple-well comprises the n type trap around p type trap.For example, alternate embodiment can be utilized substrate and the alternative trap setting that the n type mixes.Although this paper is described in conjunction with the NMOS flash cell, described memory cell also can comprise and is formed at the suprabasil PMOS of p type unit.Gate dielectric 16 heat grow in the substrate 10, and preferably comprise and form thickness about 70～110
Between SiO
2The source/drain injection zone preferably is a N+ injection zone 14, and it is formed between the unit 18, and is formed between unit 18 and selection transistor 20a, the 20b.In one embodiment, N+ injection zone 14 comprises concentration and is about 1 * 10
18To 5 * 10
19Atoms/cm
3Arsenic or the admixture of phosphorus.
Each unit 18 comprises the conductive floating gate utmost point 22 that is formed on the gate dielectric 16, preferably comprises to have thickness about 300～1000
Between polysilicon layer, and more preferably about 500
Polysilicon layer.Dielectric layer 24 is formed on the floating grid 22 and comprises thermal oxide layer, for example forms thickness about 110～140
SiO
2, or have about 110～140
Between ONO (oxide/nitride/oxide) layer of effective oxide thickness.Can use the described ONO layer of LPCVD (low-pressure chemical vapor deposition) process deposits, it has from SiH
2CL
2/ O
2Gas aggradation about 20
The top oxide layer of thickness has from SiH
2CL
2/ O
2Gas aggradation about 40
The bottom oxidization layer of thickness, and have from SiH
2CL
2/ N
2Gas aggradation about 80
The SiN layer of thickness.Control grid 26 forms from the shared word line of some parallel units strings, and control grid 26 is formed on the dielectric layer 24, and preferably comprises and have about 700～1000
Between the polysilicon layer 28 of thickness.Silicide layer 28 preferably comprises tungsten (W) silicide layer, can be formed at according to circumstances on control grid/word line 26.
The person of ordinary skill in the field will be apparent, when control grid 26 and silicide layer 28 (when it exists) form when crossing the word line of some unit strings as shown in fig. 1, the floating grid 22 of each unit and dielectric layer 24 are centered on by insulating barrier, and this insulating barrier is separated from one another and separate with the unit of adjacent unit strings with the unit in the individual elements string.
As shown in Figure 2, each transistor unit 18 has passage length F, its by the photoetching process that is used to form the memory array pattern can imaging minimum dimension define.Each selects transistor 20a and 20b preferably to have length 2F (to avoid breakdown problem, to minimize source electrode to the leakage current that drains etc.), and with separately connector 30 spacing distance F.Each connector has spacing 2F.Importantly, each floating gate cell 18 and adjacent floating gate cell 18 be one section distance less than " F " " X " at interval, and with adjacent selection transistor 20 (for terminal units 18) this distance at interval.Total unit strings length equals 8F+mF+ (m+1) X, and wherein " m " is the sum of unit in the unit strings, is generally 16,32 or 64.In one embodiment, X equals 0.03 μ m and F equals 0.09 μ m and has 16 unit, so total unit strings length only is 24F+ (17/3) F=29.7F.As in the prior art, if X equals F, so total unit strings length will be 41F.In addition, suppose that again X equals 1/3F, described cell size is about (F+X) 2F (or about (2.66F
2)) but not 4-5F
2
The exemplary method of word line structure of the tight spacing of a kind of Fig. 2 of formation has been described with reference to Fig. 3 A～3F.Fig. 3 A～3F explanation is used to create leading portion (front-end-of-line, FEOL) processing step of memory construction.Here do not have the processing step that is used to form the required intraconnections circuit of addressing individual memory cell is discussed, promptly form back segment (back-end-of-line, BEOL) technology such as contact hole, interlayer hole, metal wire and corresponding insulation layer.
With reference to Fig. 3 A, at first on gate dielectric 16, be formed for forming the transistorized material stacks of individual memory cell.Specifically, floating grid polysilicon layer 122 is deposited as thickness about 300～1000
Between.Then, on polysilicon layer 122, form ONO dielectric layer 124.Then, will control gate polysilicon layer 126 and be deposited as thickness about 700～1000
Between.At last, deposition or formation tungsten silicide layer 128 make its thickness be about 300 on control gate polysilicon layer 126
With reference to Fig. 3 B, deposit first oxide layer or it is formed at the silicide memory cell stack (promptly, layer 122,124,126,128) on, and with its patterning be etched with to form and be spaced apart to define first group of first group of oxide mask 130 of word line and memory cell at interval.In one embodiment, the thickness of oxide mask 130 is about 900～1500
Between, and more preferably be about 1000
Oxide mask 130 comes patterning and etched oxide layer to form by the photoresist mask that uses the photoetching process imaging, and wherein " F " is imageable minimum dimension.Each mask 130 has width F.Then, SiN layer 132 is deposited on the described structure, promptly is deposited on oxide mask 130 and the silicide layer 128.For example SiN layer 132 is deposited as thickness less than F, and is about 300 in one embodiment by low-pressure chemical vapor deposition (LPCVD) technology
In an embodiment, oxide mask 130 district's each intervals one segment distance F+2X, wherein X is the distance between the word line shown in Fig. 2.Described distance is defined by photoetching process really, and it can be defined as characteristic size little of F.
With reference to Fig. 3 C, remove the part of SiN layer 132 and keep SiN side wall spacer 132 on oxide mask 130 sidewalls '.End-point detection can be used for monitoring described etch process.In an one exemplary embodiment, can use Ar/CF with one
4The anisotropic dry etch technology of reacting gas is used for etching SiN layer 132.When detecting oxide layer 130, stop described etch process.Because described oxide thickness is in the SiN that is formed at therebetween, so in case detect described oxide then the SiN layer 132 of an adjacent described oxide part residue part only just.SiN clearance wall 132 ' the have thickness that equals " X ", its be between word line between every, and identical with layers 132 deposit thickness approximately.
With reference to Fig. 3 D, then the second oxide layer (not shown) is deposited on fill on the structure of Fig. 3 C clearance wall 132 ' between opening at interval, and it is eat-back to keep second group of spacer oxide mask 134.Oxide mask 130 exists, but be assigned therein as 130 ', because by the second oxide layer exposed gap wall 132 ' during its can be by etching a little.Each oxide part 130 ', 134 have the width that equals F, and equal the clearance wall 132 of X ' spaced apart with adjacent oxide part by width, wherein X is less than F.Layer 130 ' and the 134 common oxide mask that form, to be used to form word line and memory cell at interval.Although only shown 11 oxide mask parts, should be appreciated that to provide 16,32 or 64 parts to be used to form word line number in the unit strings, and can provide extra oxide partly to be used to form to select the transistor (not shown).
In alternate embodiment, mask 130,134 is formed by SiN, and layer 132 (and therefore clearance wall 132 ') is formed by oxide.
With reference to Fig. 3 E, remove SiN clearance wall 132 ', and the oxide mask layer of Fig. 3 D is used for etching penetrated bed 122,124,126 and 128, to form the interval memory cell 18 of Fig. 2, it has width F and each interval one segment distance X.Can Ar/CF will be used
4The dry etching process of reaction solution be used to remove SiN clearance wall 132 '.Can Cl will be used
2The dry etching process of/HBr solution is used for etching control gate polysilicon layer 126, and identical solution can be used for etching silicide layer 128.Can CHF will be used
3/ CHF
4The dry etching process of/He solution is used for etching ONO dielectric layer 124.At last, can Cl will be used
2The dry etching process of/HBr solution is used for etching floating grid polysilicon layer 122.
Shown in Fig. 3 F, as removing mask part 130 ' and 134 with etch process, and injection zone 14 is formed at adjacent and individual memory cell 18 betwixt in the substrate 10.
Also can will substitute the memory cell array that program/erase method is used for Fig. 1, described method utilizes hot hole to inject to remove stored electronics during programming by BTBT (the energy interband is worn tunnel).Wear tunnel and occur in the crosspoint that source/drain (S/D) connects face and wears the tunnel oxide.N+S/D is connect the face reverse bias to a certain degree to substrate, make soft breakdown or Zener (Zener) puncture take place.When electronics in S/D and crosspoint when valence band is tunnelled to conduction band, described pn connects mask electric current.The hole results from the valence band, and floating grid attracts the hole by apply negative voltage on the control grid.Negative voltage on the described control grid has also strengthened the BTBT electric current.The unit of institute's access if do not programme, so with 0V bias voltage bit line, and reverse bias S/D does not connect face.There is not BTBT to wear the tunnel electric current with this understanding.Carry out and wipe by making all unit of selecting in the block have higher critical value.Between erasing period, electronics is worn tunnel by FN and is tunnelled to floating grid from passage.Summed up programming in the following form, wiped and reading conditions.
| Wipe | Programming | Read | |
| The WL that selects | 20V | -5V | 0V |
| Unselected WL | 20V | 10V | 4.5V |
| SSL | VCC | 10V | 4.5V |
| GSL | 0V | Float | 4.5V |
| BL (to 0 programming) | 0V | 7V | N/A |
| BL (to 1 programming) | 0V | 0V | N/A |
| Body | 0V | 0V | N/A |
Hot hole injects to produce and is absorbed in the hole of tunnel oxide, and can reduce the wear properties of programming-wipe.The cavity type trap is positioned near the drain junction edge, and the channel hot electron that its influence is used to programme is injected.Existing cavity type trap will reduce near the electric field the drain electrode, and make that hot electron efficient is relatively poor.Yet because describedly be erased at the whole tunnel oxide areas of wearing and wear tunnel by FN and finish, therefore, the influence of this mechanism is lower in the programmed method proposed in the above.Although this mechanism can cause interference in the NOR flash memory, it can not cause interference in nand flash memory.Unselected word line has high voltage so that bit-line voltage passes through.Unit on the unselected word line does not have BTBT to be disturbed.Unselected block also has the transistor of selection to protect described unit.Described bit-line voltage can not be sent to described unit.For guaranteeing that S/D connects face by reverse bias, so S/D needs positive bias.Described bias voltage is from bit line.Suppose for example to select WL2 and programmed in the unit.WL0 and WL1 are unselected word lines between word line of selecting and bit line.Move WL0, WL1 and SSL to 10V.WL2 is set at-5V.7V bias voltage on the bit line will pass through to the S/D zone between WL1 and the WL2.Described S/D zone will have BTBT and wear the tunnel electric current.The hole is attracted to the floating grid of this unit through the WL2 of back bias voltage.Because WL2 is lower than the Vth of erase status by back bias voltage and bias voltage, therefore described unit is closed.Therefore, described 7V bias voltage will not pass through to WL3 and other word line.
The technology that Fig. 4 A～4D describes in conjunction with Fig. 3 A～3F more than illustrating, it is applicable to for example United States Patent (USP) the 6th of Haspeslagh, the formation of the SONOS described in 580, No. 120 (silicon/ONO/ silicon) memory cell, described patent are incorporated herein by reference in full.In Fig. 4 A～4D, refer to similar structure with similar elements symbol among Fig. 3 A～3F.
As shown in Fig. 4 A, ONO layer 200 is formed in the substrate 10.ONO layer 200 preferably has effective oxide thickness, and it is about 110～140
Between.Layer 200 comprises first insulating barrier 202, stores layer 204 and second insulating barrier 206.Can use the described ONO layer of LPCVD (low-pressure chemical vapor deposition) process deposits, it has from SiH
2CL
2/ O
2Gas aggradation about 20
The top oxide layer 206 of thickness has from SiH
2CL
2/ O
2Gas aggradation about 40
The bottom oxidization layer 202 of thickness, and have from SiH
2CL
2/ N
2Gas aggradation about 80
The SiN of thickness stores layer 204.
Residue technology is with above described substantially the same in conjunction with Fig. 3 A～3F.To control gate polysilicon layer 126 is formed on the layer 200.Form silicide layer 128 according to circumstances, form first group of oxide mask 130 and SiN layer 132 at interval afterwards.
With reference to Fig. 4 B, etching SiN layer 132 with form SiN clearance wall 132 '.In Fig. 4 C, deposition and etching second oxide layer with expose SiN clearance wall 132 ', stay second group of oxide mask 134 at interval.As shown in Fig. 4 D, remove described SiN clearance wall 132 ', and then described mask set is used for etching penetrates silicide layer 128 and top polysilicon layer 126.
In an embodiment, Fig. 4 D represents final cellular construction, although shown mask part 130 ' and 134 be removed.In alternate embodiment, 10 continue etch process from ONO layer 200 to substrate.In this alternate embodiment, form injection zone (as shown in above Fig. 3 F) and FN is worn tunnel and be used to carry out program/erase.Shown in the following form and be used to inject program/erase/reading conditions of embodiment to be used for the NMOS unit.
| Wipe | Programming | Read | |
| The WL that selects | |
12～15V | 0V |
| Unselected WL | 0V | 6～9V | 4.5V |
| SSL | Float | 6～9V | 4.5V |
| GSL | Float | 0V | 4.5V |
| BL (to 0 programming) | Float | 0V | N/A |
| BL (to 1 programming) | Float | 6～9V | N/ |
| Body | |||
| 12～15V | 0V | N/A |
If there is no injection zone injects (source side injection) with source side so and is used to programme, and FN is worn tunnel is used to wipe.In No. the 6th, 580,120, the United States Patent (USP) that all is incorporated herein by reference described program/erase method has been described.The one exemplary condition that reads has also been described in ' 120 patents.
In sum, propose the method that a kind of formation has the word line at the interval that dwindles and forms the unit in the present invention, the method has preferable integrated technology.The unit interval that dwindles improves integration density, whereby reduction means size and/or capacity.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; when can doing a little change and improvement, so the present invention's protection range is as the criterion when looking the claim person of defining.
Claims (17)
1. method that forms NAND type flash memory device is characterized in that comprising following steps:
In substrate, form the control gate polysilicon layer;
On described control gate polysilicon layer, form mask layer, wherein said mask layer comprises the mask pattern of several word lines at interval that define described NAND type flash memory device, described word line each interval certain distance X and described distance X are less than minimum feature size F, and described minimum feature size F is by the photoetching process imaging of the selection that is used to form the described mask pattern of at least a portion; With
By the described control gate polysilicon layer of described mask layer etching;
Wherein, described mask layer formation step comprises following steps:
On described control gate polysilicon layer, form ground floor, and use the described ground floor of described photoetching process patterning to form first group of mask part at interval, described first group of mask at interval partly defines first group of word line at interval, and the distance of F+2X at interval between adjacent described first group of mask part at interval;
On the sidewall edge of described first group of mask part at interval, form clearance wall;
Form the second layer between described clearance wall, the described second layer defines second group of word line at interval; With
Remove described clearance wall, form the described mask pattern that defines described several word lines at interval whereby.
2. the method for formation according to claim 1 NAND type flash memory device is characterized in that described clearance wall is that silicon nitride and described first and second layers are oxide, or described first and second layers is oxide for silicon nitride and described clearance wall.
3. the method for formation NAND type flash memory device according to claim 2 is characterized in that described clearance wall forms step and comprises following steps:
Clearance wall is deposited upon on the described ground floor and described first group of mask part at interval between; With
From the described gap of etching parietal layer between described ground floor and the described first group of mask part at interval to form described clearance wall.
4. the method for formation NAND type flash memory device according to claim 1 is characterized in that the described second layer forms step and comprises following steps:
The described second layer is deposited in the described substrate, comprises on described ground floor and the described clearance wall; With
The described second layer of etching is to expose described clearance wall.
5. the method for formation NAND type flash memory device according to claim 4 is characterized in that described ground floor has 1000
Thickness, and described clearance wall has 300
Thickness.
6. the method for formation according to claim 1 NAND type flash memory device is characterized in that also being included in the step of formation injection zone in the described substrate between the word line at described interval described etching step after.
7. the method for formation NAND type flash memory device according to claim 1 is characterized in that described control gate polysilicon layer is formed on the oxide/nitride/oxide.
8. the method for formation NAND type flash memory device according to claim 7 is characterized in that described oxide/nitride/oxide has 110～140
Between effective oxide thickness.
9. the method for formation NAND type flash memory device according to claim 1 is characterized in that also being included in the step that forms silicide layer on the described control gate polysilicon layer.
10. the method for formation NAND type flash memory device according to claim 1 is characterized in that also comprising following steps:
Form the floating grid polysilicon layer on the active region in described substrate; With
Form dielectric layer on described floating grid polysilicon layer, wherein said etching step comprises the step of described floating grid polysilicon layer of etching and described dielectric layer.
11. the method for formation NAND type flash memory device according to claim 1 is characterized in that also comprising following steps:
In described substrate, form first insulating barrier;
On described first insulating barrier, form and store layer;
On described storage layer, form second insulating barrier, wherein on described second insulating barrier, form described control gate polysilicon layer.
12. the method for formation NAND type flash memory device according to claim 1 is characterized in that described mask layer is an oxide.
13. a method that forms NAND type flash memory device is characterized in that comprising following steps:
In substrate, form dielectric layer;
On described dielectric layer, form polysilicon control grid utmost point layer;
Deposition first mask layer on described polysilicon control grid utmost point layer;
Described first mask layer of etching partly defines first group of word line at interval to form first group of mask part and described first group of mask at interval at interval, each mask have partly that certain width and described width depend on that minimum feature size by the photoetching process imaging of selecting, adjacent mask partly keep at a certain distance away and described distance greater than described minimum feature size and less than three times of described minimum feature size;
On the sidewall of described first group of mask part at interval, form clearance wall;
Between described clearance wall, form second group of mask part and described second group of mask at interval at interval and partly define second group of word line at interval;
Remove described clearance wall, form described first group of mask part at interval with described second group at interval mask part alternate intervals and spacing distance less than the mask pattern of described minimum feature size; With
By the described polysilicon control grid utmost point of described mask pattern etching layer.
14. the method for formation NAND type flash memory device according to claim 13 is characterized in that the formation step of described clearance wall and described second group of mask part at interval comprises following steps:
On described first group of mask part at interval, form sacrifice layer;
The described sacrifice layer of etching is to form described clearance wall on the sidewall of described first group of mask part at interval;
Described first group at interval the mask part and clearance wall on formation mask material layer;
The described mask material layer of etching is to expose described first group of mask part at interval, and the part residue of wherein said mask material layer is to form described second group of mask part at interval.
15. the method for formation NAND type flash memory device according to claim 13 is characterized in that described first group of mask at interval partly is oxide or silicon nitride, described second group of mask at interval partly is oxide or silicon nitride.
16. the method for formation NAND type flash memory device according to claim 13 is characterized in that described dielectric layer is an oxide/nitride/oxide.
17. the method for formation NAND type flash memory device according to claim 16, it is characterized in that described dielectric layer is formed on the floating grid polysilicon layer, then described etching step also comprises by the described first and second groups of partially-etched described dielectric layer of mask and floating grid polysilicon layers at interval.
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| CNB2006100580074A CN100426466C (en) | 2006-02-24 | 2006-02-24 | Method for forming flash unit array with reduced word-linepitch |
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| CNB2006100580074A CN100426466C (en) | 2006-02-24 | 2006-02-24 | Method for forming flash unit array with reduced word-linepitch |
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