CN1881839A - Multi-channel parameter unloading method and device for wireless communication system physical layer - Google Patents
Multi-channel parameter unloading method and device for wireless communication system physical layer Download PDFInfo
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Abstract
The invention relates to a multi-channel parameter loading method of the physical layer of wireless communication system, which comprises: storing the channel parameter sent from the digit signal processing unit DSP in the first memory; detecting the setting complete signal sent from DSP, according to which, setting the setting complete mark of channel parameter, to judge if the setting complete mark is effective and judge if it is at the frame edge parameter effect point; if it meets said two conditions, loading the channel parameter of first memory to the second memory; or else feeding back the step b; according to the channel number, outputting the channel parameter relative to the channel of second memory. The invention also discloses a multi-channel parameter loading device, which comprises: a channel parameter read/write control unit, a channel parameter first memory unit, a channel parameter setting complete control unit, a channel parameter loading control unit, a channel parameter second memory unit, and a channel parameter output control unit.
Description
Technical field
The present invention relates to the physical-layer techniques of wireless communication system, be meant a kind of multi-channel parameter unloading method and device of wireless communication system physical layer especially.
Background technology
Wireless communication system, as GSM, CDMA, WCDMA, CDMA2000, the physical layer of systems such as TD-SCDMA is all supported a plurality of channels, and the channel parameter of oneself is all arranged for each channel.Is example at this with the WCDMA system, specifically introduces storage of physical layer multi-channel parameter and existing multi-channel parameter and read method.
In the WCDMA system, high level data is transferred to after the physical layer, is mapped in the radio frames of physical channel.The message transmission rate of physical channel, scrambling mode, channel content are all different, and are that unit is distinguished with the radio frames.The physical channel of WCDMA is divided into 3-tier architecture in time: superframe, radio frames, time slot.A superframe schedules to last 720ms, comprises 72 radio frames, and the long 10ms of wireless frame period comprises 15 isometric time slots, the corresponding 2560chip of time slot.Frame boundaries is by system frame number SFN definition, and promptly a frame SFN of a superframe is 0 to 72 delivery values, and its tail frame SFN is 71 to 72 delivery values.
The WCDMA system is divided into uplink physical channel and downlink physical channel according to the direction difference of physical channel.Be example with the downlink physical channel below, introduce the frame timing relationship.
Downlink physical channel mainly comprises downlink dedicated physical channels (DPCH), Common Pilot Channel (CPICH), Common Control Physical Channel (CCPCH), synchronizing channel (SCH), AICH Acquisition Indication Channel (AICH) and Page Indication Channel (PICH) etc.In 3GPP TS 25.211 agreements, the timing relationship between above-mentioned each physical channel has been done following description.
The SFN of a sub-district goes up transmission at Primary Common Control Physical Channel (P-CCPCH), and system is the timing reference of P-CCPCH channel as all physical channels.Down channel is directly as reference, and up channel is indirectly as reference, and the transmission time of up link is the Time Calculation that receives down physical channel according to it.Fig. 1 has described the frame timing relationship of down physical channel, and the timing relationship of each interchannel is described below:
1) primary synchronization channel (P-SCH), auxiliary synchronization channel (S-SCH), Primary Common Pilot Channel (P-CPICH), secondary common pilot channel (S-CPICH), P-CCPCH has identical frame regularly with downlink physical shared channel (PDSCH).
2) to auxilliary Common Control Channel (S-CCPCH), different channels has different time delays, and they are the integral multiple of 256chips with the skew of the frame timing of P-CCPCH, that is, and and τ
S-CCPCH, k=T
k* 256chip, T
k∈ 0,1 ..., 149}.
3) timing of PICH is with respect to corresponding S-CCPCH frame timing advance τ
PICH, τ
PICH=7680chips.
4) different DPCH have different timing, and the skew regularly of the frame of they and P-CCPCH is the integral multiple of 256chips, that is, and and τ
DPCH, n=T
n* 256chip, T
n∈ 0,1 ..., 149}.
5) the access slot # 0 of AICH begins from the frame head of the P-CCPCH of (SFN modulo 2)=0.
6) the initial alignment of frame of the initial and P-CCPCH of the subframe # 0 of high speed descending sharing channel (HS-SCCH).
Each physical channel all has the parameter of oneself, and these parameters are disposed by high level, can be divided into several class channel parameters, the moment point difference that comes into force of each class channel parameter.Channel parameter within one frame is normally indeclinable, and the variation of channel parameter is to switch frame by frame.Each channel parameter needs buffer memory, and reads channel parameter when system needs, that is to say the channel parameter treatment mechanism that system will have a cover to finish the channel parameter buffer memory and read.Two kinds of technical schemes are arranged at present, and a kind of is the channel parameter treatment technology that adopts the level cache mode, and another kind is the channel parameter treatment technology that adopts the ping-pong buffer mode.
Figure 2 shows that the structure chart of the channel parameter processing of adopting the level cache mode, comprise channel parameter read-write control unit 101, channel parameter level cache unit 102 and channel parameter output control unit 103, based on the channel parameter buffer memory of this structure with to read process as follows:
Channel parameter read-write control unit 101 enables the different addresses distributed with the channel parameter of giving different channels according to the read/write from each channel parameter of DSP, finish the work decoding that is used for channel parameter level cache unit 102 read/write address, and, the channel parameter that DSP issues is deposited channel parameter level cache unit according to the address information of deciphering.The channel parameter of determining according to dsp software issues the time, and the reading of channel parameter output control unit 103 decoding channel parameter buffer memorys read channel parameter from channel parameter level cache unit 102 in the address, and boundary outputs in the modulation module coming into force.Wherein, channel parameter level cache unit 102 is made up of the RAM and the register of all size.
Adopt in the channel parameter processing scheme of level cache, guarantee that by dsp software channel parameter issues the accurate of time point, therefore requires than higher dsp software; Because the number of channel that wireless communication system physical layer is supported is many, such as in the WCDMA system, supporting 128 channels so DSP amount of calculation height; And because the frame of each channel is regularly also different, the actual also difference that comes into force constantly of channel parameter, therefore the time precision to dsp software requires high.This technical scheme requires the time precision height to DSP, and amount of calculation is big, is difficult to realize.
Figure 3 shows that the structure chart of the channel parameter processing of adopting the ping-pong buffer mode.This scheme has mainly adopted read/write table tennis switching mark, and the read/write of channel parameter will be by the control of table tennis sign.In conjunction with Fig. 3, specifically describe as follows:
Channel parameter read-write control unit 201 is deciphered out the read/write address of channel parameter according to the different buffer address of the channel parameter of the different channels that is distributed by DSP.Write the table tennis switching mark according to what write respective channels parameter in the table tennis switching mark registers group 202, channel parameter is write table tennis buffer memory or pang buffer memory 203, wherein buffer memory is RAM or register, and write whenever that buffer memory then switches the respective channel parameter write the table tennis sign.
After channel parameter write table tennis buffer memory or pang buffer memory 203, the channel parameter configuration was finished control unit 205 and is finished information according to the configuration that DSP issues, and will read the upset of table tennis sign in the switching mark register 206 of reading to rattle.
Channel parameter output control unit 204 is deciphered the address of reading of table tennis buffer memorys or pang buffer memory 203, and at a channel parameter place of coming into force, according to reading the table tennis sign from respective channel parameter in the switching mark registers group 206 of reading to rattle, channel parameter is read in table tennis buffer memory or pang buffer memory 203, exported to modulation module.
Adopt in the channel parameter processing scheme of ping-pong buffer mode, need reading the table tennis sign and writing the table tennis sign of two cover table tennis switching mark register maintenance channel parameters for each channel parameter, because channel is many, register is also many, so register maintenance cost height, implement also complexity, increased the complexity of circuit.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of multi-channel parameter unloading method,, can read channel parameter in the correct moment with the assurance modulation module by to buffer memory and the control of reading channel parameter.
Another object of the present invention is to provide a kind of multi-channel parameter unloading device, can finish the channel parameter unloading and to issue.
According to first above-mentioned purpose, the invention provides a kind of multi-channel parameter unloading method of wireless communication system physical layer, it is characterized in that, comprising:
A) channel parameter that digital signal processing unit DSP is issued is stored in the level cache;
B) detect the configuration that DSP issues and finish signal, finish the configuration complement mark that signal is provided with channel parameter according to configuration, whether the configuration complement mark of judging channel parameter is effective, and judge whether to come into force a little in the frame boundaries parameter, if both all satisfy above-mentioned condition, then the channel parameter in the level cache is dumped in the L2 cache; Otherwise return step b;
C) according to this channel channel parameter corresponding in the channel number output L2 cache.
Wherein, the step that the described judgment frame boundary parameter of b comes into force a little comprises that frame timing slip parameter and the benchmark timing ga(u)ge numerical value that is produced by modulation module with channel subtract each other, if the result who subtracts each other is 0, then is judged to be the frame boundaries parameter and comes into force a little.
Wherein, described step b further comprises, judges that the channel parameter unloading is to come into force synchronously or asynchronous coming into force, if come into force synchronously, then at the frame boundaries unloading channel parameter of the system-frame of appointment, if asynchronous coming into force, then the frame boundaries unloading channel parameter of the next frame after present frame.
Wherein, described step c comprises, each channel number that modulation module is exported successively is as channel polling number, according to the channel parameter in the channel polling poll output L2 cache.
Wherein, the described unloading channel parameter of step b is the parameter of a channel of unloading in a clock cycle.
Wherein, the described delivery channel parameter of step c is the parameter of a channel of output in a clock cycle.
Wherein, step b further comprises, after the channel parameter in the level cache dumps in the L2 cache, removes the configuration complement mark of channel parameter.
According to another above-mentioned purpose, the invention provides a kind of multi-channel parameter unloading device of wireless communication system physical layer, comprise that decoding is from the read/write address of DSP and the channel parameter that DSP issues is stored to the channel parameter read-write control unit of channel parameter level cache unit, with, store the described channel parameter level cache unit of the channel parameter that DSP issues, with, control unit is finished in the channel parameter configuration of configurating channel parameter configuration complement mark, and the channel parameter output control unit of delivery channel parameter, it is characterized in that, this device also comprises: channel parameter unloading control unit and channel parameter L2 cache unit, wherein
The frame boundaries that channel parameter unloading control unit calculates according to this unit comes into force a little and disposes the configuration complement mark of finishing control unit from channel parameter, and the channel parameter that will read in the channel parameter level cache unit dumps to channel parameter L2 cache unit;
The channel parameter output control unit reads the channel parameter of this channel according to channel number in channel parameter L2 cache unit, and exports.
Wherein, the channel parameter configuration is finished control unit and is comprised: the configuration completion status register of address decoding circuitry, detection rising edge circuit and stored configuration complement mark, wherein:
Address decoding circuitry decoding is from the address of the configuration completion status flag register of DSP, signal is finished in the configuration that detection rising edge electric circuit inspection DSP issues, configuration complement mark according to testing result configurating channel parameter, and the address of the register that obtains according to decoding, be stored in the configuration completion status register.
Wherein, channel parameter level cache unit comprises with channel parameter L2 cache unit: have different memory spaces RAM and registers group.
Wherein, the channel parameter output control unit comprises: channel number decoding unit and data strobe merge cells, wherein:
Channel parameter L2 cache unit and data strobe merge cells are exported in the address of reading that the channel number decoding unit is deciphered this channel institute respective channels parameter according to channel number, and delivery channel parameter L2 cache unit read enable;
The data strobe merge cells is according to the address of reading of channel number decoding unit output, channel parameter in the gating delivery channel parameter L2 cache unit in the registers group, and with RAM from channel parameter L2 cache unit in the channel parameter read merge, by the different parameters holding wire that the heterogeneity by channel parameter distributes, export to modulation module.
Wherein, described channel parameter unloading control unit also comprises, after the channel parameter that reads in the channel parameter level cache unit dumps to channel parameter L2 cache unit, finish the control unit output signal to the channel parameter configuration, dispose the configuration complement mark of finishing in the control unit to upgrade channel parameter.
Wherein, in described detection rising edge circuit and the configuration completion status registers group number of register the number with channel is identical respectively.
The present invention adopts the I and II caching method to realize the storage of multi-channel parameter, because in the buffer memory of the second level, control by unloading, come into force at channel parameter and some channel parameter to be dumped to the L2 cache from level cache, guaranteed that coming into force of channel parameter a little satisfy the requirement of 3GPP agreement regulation, guaranteed that modulation module can in time obtain effective channel parameter.The present invention also supports the asynchronous two kinds of patterns that come into force and come into force synchronously, has improved channel parameter configuration flexibility and controllability.The processing of channel parameter of the present invention is the mode with the channel repeating query, has therefore saved hardware and logical resource.The present invention has guaranteed that by the mode of L2 cache channel parameter issues accuracy constantly, is different from prior art, does not need issuing constantly of control channel parameter with DSP, has reduced the workload of DSP, realizes simple.The present invention does not need read-write table tennis flag register yet, compares with ping-pong buffer, and circuit is simple, realizes simple.
Description of drawings
Fig. 1 is the frame timing of down physical channel and the timing relation figure of access slot;
Fig. 2 is that the channel parameter of available technology adopting level cache mode is handled structure chart;
Fig. 3 is that the channel parameter of available technology adopting ping-pong buffer mode is handled structure chart;
Fig. 4 is a multi-channel parameter unloading equipments overall structure block diagram of the present invention;
Fig. 5 is the realization block diagram of channel parameter read-write control unit of the present invention;
Fig. 6 finishes the realization block diagram of control unit for channel parameter configuration of the present invention;
Fig. 7 is a channel parameter unloading control flow chart of the present invention;
Fig. 8 is that the present invention is with unloading of channel repeating query mode and the sequential chart that issues channel parameter;
Fig. 9 is the realization block diagram of channel parameter output control unit of the present invention.
Embodiment
The present invention is further detailed explanation below in conjunction with drawings and the specific embodiments.
The structure chart of multi-channel parameter unloading device provided by the invention as shown in Figure 4, this device mainly comprises: control unit 303, channel parameter unloading control unit 304, channel parameter L2 cache unit 305, channel parameter output control unit 306 are finished in channel parameter read-write control unit 301, channel parameter level cache unit 302, channel parameter configuration.The function of introducing each unit in detail is as follows:
Channel parameter read-write control unit 301, the read/write address of the channel parameter that decoding DSP distributes.
Channel parameter level cache unit 302, the channel parameter with DSP issues carries out level cache according to above-mentioned decoding address.This element is made up of the RAM or the register of all size according to the classification of channel parameter.
Channel parameter unloading control unit 304, the frame boundaries channel parameter of judging each channel comes into force a little, detect the channel parameter configuration and finish the channel parameter configuration complement mark of control unit 303 outputs, when this configuration complement mark is 1, respectively delivery channel parameter level cache unit read enable to enable with writing of channel parameter L2 cache unit, channel parameter come into force a little on, the channel parameter that reads in level cache dumps to the L2 cache, simultaneously channel parameter is disposed complement mark clear 0.
Channel parameter output control unit 306, the channel rotary number of decoding modulation module output is read channel rotary number channel parameter corresponding in L2 cache, export to modulation module and use.
Wherein, channel parameter L2 cache unit 305 is made up of the RAM or the register of all size according to the classification of channel parameter.
As shown in Figure 6, the channel parameter configuration is finished control unit 303 and is comprised address decoding circuitry 401, distinguishes corresponding detection rising edge circuit 402 and the configuration completion status registers group 403 corresponding respectively with each channel with each channel, wherein,
Address decoding circuitry 401 writes corresponding configuration completion status register according to the write address that disposes the completion status register from the address information decoding channel parameter of DSP with the configuration complement mark with each channel parameter; Because the inner ASIC specified configuration of application-specific integrated circuit (ASIC) logic is finished signal and will be write 0 earlier and write 1 again,, detect rising edge circuit 402 and detect the channel parameter configuration that DSP issue and finishes signal so need to detect the rising edge circuit; Detect the rising edge that signal is finished in configuration when detecting rising edge circuit 402, ASIC inside will put 1 to the configuration completion status register of memory channel parameter configuration complement mark.
Because after one group of channel parameter configuration of each channel is finished, all can have by the configuration of DSP configuration and finish signal, the number of register is identical with the channel number in therefore detecting rising edge circuit 402 and disposing completion status registers group 403.
As shown in Figure 9, channel parameter output control unit 306 is made up of two parts:
Channel number decoding unit 501, according to channel rotary number from modulation module, decipher out the specific address of the pairing channel parameter of channel rotary number in channel parameter L2 cache unit 305, then RAM is read the address and export RAM to, registers group is read the address export data strobe merge cells 502 to, and output is read enable signal to channel parameter L2 cache unit 502;
Data strobe merge cells 502, read channel parameter in the address strobe output register group according to the registers group of channel number decoding unit 501 output, and with RAM in after the channel parameter read merges, character according to channel parameter, distribute different parameter signal lines, by this parameter signal line, export to modulation module.
The general thought of multi-channel parameter unloading method provided by the invention is: at first the channel parameter that DSP is issued carries out level cache, after judging that channel parameter configuration complement mark effectively, come into force a little at channel parameter, these channel parameters are dumped in the buffer memory of the second level, according to channel rotary number, export to modulation module then in the mode of channel repeating query from modulation module.The inventive method is described in detail as follows:
Steps A: the channel parameter that DSP is issued carries out level cache, and in conjunction with shown in Figure 5, it is as follows to describe its process in detail:
Steps A 1: provided by DSP that channel parameter read-write enables, read/write address, the write address of 301 couples of DSP of parameter reading and writing control unit is deciphered;
Steps A 2: the write address that distributes according to DSP, the channel parameter that DSP is issued is cached to the RAM or the register of corresponding address in the channel parameter level cache unit 302;
Steps A 3: the above-mentioned address that writes channel parameter of channel parameter read-write control unit 301 decodings, the data in this address of DSP retaking of a year or grade, whether the acknowledgement channel parameter correctly writes;
Steps A 4: when channel parameter was cached to level cache, DSP delivery channel parameter configuration was finished signal to channel parameter configuration and is finished control unit.
Step B: by channel parameter unloading control, come into force a little, channel parameter is dumped to L2 cache at channel parameter.
Wherein the channel parameter of each channel L2 cache address of depositing is allocated in advance, makes when modulation module needs the channel parameter of a certain channel, just can take out from corresponding address according to channel number.
Be the time point that makes things convenient for the control channel parameter to come into force, channel parameter unloading mode of the present invention can be supported to come into force synchronously and the asynchronous two kinds of patterns that come into force, and specifically adopts which kind of pattern to dispose by system is high-rise.What is called comes into force synchronously and is meant: the channel parameter that DSP issues is to come into force at the frame boundaries place of the system frame number SFN of appointment, therefore when supporting to come into force synchronously, when judging that by channel parameter unloading control unit 304 channel parameter that DSP issue is the channel parameter of current SFN, the unloading channel parameter.So-called asynchronous coming into force is meant: the channel parameter that DSP issues directly comes into force at the next frame head of the present frame at this channel parameter place, need not wait for current SFN, therefore when supporting asynchronous coming into force, the channel parameter that DSP issues carries out unloading at the next frame head of present frame.Below in conjunction with Fig. 7, describe the flow process of channel parameter unloading control in detail:
Step B1: the frame timing slip parameter X of read channel parameter place channel in the level cache, to describe in this parameter X such as the background technology, the frame head of each channel is difference with different frame timing slips, and this is disposed to channel parameter by DSP.The modulation module of each channel produces benchmark timing ga(u)ge numerical value Y by frame count.Frame timing slip parameter X and benchmark timing ga(u)ge numerical value Y are subtracted each other, give next step B2 subtracting each other the result;
Step B2:, judge whether it is frame boundaries:, return step B1 when the result 0 the time, shows the frame boundaries that is not this channel parameter place frame for non-according to the above-mentioned result that subtracts each other; When the result is 0, show it is the frame boundaries of this channel parameter place frame, continue execution in step B3;
Step B3: at the frame boundaries place, judge whether the configuration complement mark of this channel parameter is 1, if be 0, the channel parameter of expression present frame not configuration is finished, and needs to rejudge to the frame boundaries of next frame, returns step B1; If be 1, show that the channel parameter configuration of present frame is finished, but need also to judge whether current channel parameter is to come into force synchronously, therefore continue execution in step B4;
Configuration complement mark in this step is to finish control unit 303 by the channel parameter configuration to finish, dispose certain specific register by DSP to come the stored configuration complement mark because be, so earlier write address is deciphered, signal is finished in the configuration that detects then in the steps A 4, finish the rising edge of signal when detecting configuration, configuration completion status register puts 1.
Step B4: judge whether channel parameter is to come into force synchronously: if not coming into force synchronously, show it is asynchronous coming into force, at next frame head execution in step B6 of this channel parameter place frame; If come into force synchronously, then continue execution in step B5;
Step B5: judge whether the present frame border is the system-frame border SFN that current appointment comes into force: if, execution in step B6; If not, then return step B1, arrive next frame again and repeat above-mentioned steps;
Step B6: channel parameter dumps to L2 cache from level cache, and channel parameter configuration complement mark clear 0.
The unloading control flow of above-mentioned channel parameter is the flow process corresponding to each channel, is to carry out in the mode of channel repeating query for all channels, and promptly each clock cycle is handled channel, a samsara successively.
Step C: according to channel rotary number,, channel parameter in the L2 cache is exported to modulation module, specifically describe as follows in the mode of channel repeating query from modulation module:
Step C1: modulation module sends to channel parameter output control unit 306 with the channel rotary number, and the unit is decoded into the address of reading of L2 cache to channel number thus;
Step C2: according to the above-mentioned address of reading, the channel parameter of channel parameter of reading from RAM and gating output from registers group merges, and according to the type of channel parameter, is divided into different data signal lines, is handed down to modulation module.
In the above-mentioned steps, also be channel parameter to be read in L2 cache, and be handed down to modulation module in the mode of channel repeating query.
Figure 8 shows that with channel parameter unloading of channel repeating query mode and the sequential chart that issues.The mode of channel repeating query is meant: for unloading or processing capacity such as issue, each clock cycle is only handled the channel parameter of a channel, and the channel parameter of all channels is to handle with serial mode.Do not adopt the channel repeating query, for unloading or processing capacity such as issue, each clock cycle is handled the channel parameter of all channels.Therefore, adopting the mode of channel repeating query just is the equal of time division multiplexing, for a processing function unit, only needs a processing unit.Therefore save the number of the gate circuit in the hardware realization, save logical resource.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1, a kind of multi-channel parameter unloading method of wireless communication system physical layer is characterized in that, comprising:
A) channel parameter that digital signal processing unit DSP is issued is stored in the level cache;
B) detect the configuration that DSP issues and finish signal, finish the configuration complement mark that signal is provided with channel parameter according to configuration, whether the configuration complement mark of judging channel parameter is effective, and judge whether to come into force a little in the frame boundaries parameter, if both all satisfy above-mentioned condition, then the channel parameter in the level cache is dumped in the L2 cache; Otherwise return step b;
C) according to this channel channel parameter corresponding in the channel number output L2 cache.
2, method according to claim 1 is characterized in that, the step that the described judgment frame boundary parameter of b comes into force a little comprises, frame timing slip parameter and the benchmark timing ga(u)ge numerical value that produces by modulation module with channel, subtract each other,, then be judged to be the frame boundaries parameter and come into force a little if the result who subtracts each other is 0.
3, method according to claim 1 and 2, it is characterized in that, described step b further comprises, judge that the channel parameter unloading is to come into force synchronously or asynchronous coming into force, if come into force synchronously, then at the frame boundaries unloading channel parameter of the system-frame of appointment, if asynchronous coming into force, then the frame boundaries unloading channel parameter of the next frame after present frame.
4, method according to claim 1 is characterized in that, described step c comprises, each channel number that modulation module is exported successively is as channel polling number, according to the channel parameter in the channel polling poll output L2 cache.
5, method according to claim 1 is characterized in that, the described unloading channel parameter of step b is the parameter of a channel of unloading in a clock cycle.
6, method according to claim 1 is characterized in that, the described delivery channel parameter of step c is the parameter of a channel of output in a clock cycle.
7, method according to claim 1 is characterized in that, step b further comprises, after the channel parameter in the level cache dumps in the L2 cache, removes the configuration complement mark of channel parameter.
8, a kind of multi-channel parameter unloading device of wireless communication system physical layer, comprise that decoding is from the read/write address of DSP and the channel parameter that DSP issues is stored to the channel parameter read-write control unit of channel parameter level cache unit, with, store the described channel parameter level cache unit of the channel parameter that DSP issues, with, control unit is finished in the channel parameter configuration of configurating channel parameter configuration complement mark, and the channel parameter output control unit of delivery channel parameter, it is characterized in that, this device also comprises: channel parameter unloading control unit and channel parameter L2 cache unit, wherein
The frame boundaries that channel parameter unloading control unit calculates according to this unit comes into force a little and disposes the configuration complement mark of finishing control unit from channel parameter, and the channel parameter that will read in the channel parameter level cache unit dumps to channel parameter L2 cache unit;
The channel parameter output control unit reads the channel parameter of this channel according to channel number in channel parameter L2 cache unit, and exports.
9, device according to claim 8 is characterized in that, the channel parameter configuration is finished control unit and comprised: the configuration completion status register of address decoding circuitry, detection rising edge circuit and stored configuration complement mark, wherein:
Address decoding circuitry decoding is from the address of the configuration completion status flag register of DSP, signal is finished in the configuration that detection rising edge electric circuit inspection DSP issues, configuration complement mark according to testing result configurating channel parameter, and the address of the register that obtains according to decoding, be stored in the configuration completion status register.
10, device according to claim 8 is characterized in that, channel parameter level cache unit comprises with channel parameter L2 cache unit: have different memory spaces RAM and registers group.
11, device according to claim 10 is characterized in that, the channel parameter output control unit comprises: channel number decoding unit and data strobe merge cells, wherein:
Channel parameter L2 cache unit and data strobe merge cells are exported in the address of reading that the channel number decoding unit is deciphered this channel institute respective channels parameter according to channel number, and delivery channel parameter L2 cache unit read enable;
The data strobe merge cells is according to the address of reading of channel number decoding unit output, channel parameter in the gating delivery channel parameter L2 cache unit in the registers group, and with RAM from channel parameter L2 cache unit in the channel parameter read merge, by the different parameters holding wire that the heterogeneity by channel parameter distributes, export to modulation module.
12, device according to claim 9, it is characterized in that, described channel parameter unloading control unit also comprises, after the channel parameter that reads in the channel parameter level cache unit dumps to channel parameter L2 cache unit, finish the control unit output signal to the channel parameter configuration, dispose the configuration complement mark of finishing in the control unit to upgrade channel parameter.
13, device according to claim 9 is characterized in that, the number with channel is identical respectively for the number of register in described detection rising edge circuit and the configuration completion status registers group.
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|---|---|---|---|---|
| CN102356587A (en) * | 2009-03-20 | 2012-02-15 | 三菱电机研发中心欧洲有限公司 | Method and a device for determining a shifting parameter to be used by a telecommunication device for transferring symbols |
| CN102356587B (en) * | 2009-03-20 | 2014-12-17 | 三菱电机研发中心欧洲有限公司 | Method and a device for determining a shifting parameter to be used by a telecommunication device for transferring symbols |
| CN104184542A (en) * | 2013-05-23 | 2014-12-03 | 重庆重邮信科通信技术有限公司 | Uplink control method, system and terminal |
| CN104184542B (en) * | 2013-05-23 | 2019-02-12 | 锐迪科（重庆）微电子科技有限公司 | Up-link control method, system and terminal |
| CN114095516A (en) * | 2020-08-04 | 2022-02-25 | 广州海格通信集团股份有限公司 | Cross-layer interaction method and device, computer equipment and storage medium |
| CN114095516B (en) * | 2020-08-04 | 2023-12-12 | 广州海格通信集团股份有限公司 | Cross-layer interaction method, device, computer equipment and storage medium |
| CN112698321A (en) * | 2020-12-11 | 2021-04-23 | 上海无线电设备研究所 | Digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment |
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| CN100578968C (en) | 2010-01-06 |
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