CN112698321A - Digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment - Google Patents
Digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment Download PDFInfo
- Publication number
- CN112698321A CN112698321A CN202011460814.5A CN202011460814A CN112698321A CN 112698321 A CN112698321 A CN 112698321A CN 202011460814 A CN202011460814 A CN 202011460814A CN 112698321 A CN112698321 A CN 112698321A
- Authority
- CN
- China
- Prior art keywords
- fpga
- dsp
- frequency
- signal
- phase increment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
- G01S13/50—Systems of measurement based on relative movement of target
- G01S13/58—Velocity or trajectory determination systems; Sense-of-movement determination systems
Landscapes
- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention relates to a digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment, comprising the following steps: s1, carrying out staggered repetition frequency processing by the DSP and the FPGA by using the single pulse signal, and solving the speed blur of the high-speed moving target to obtain the real speed of the target; s2, calculating the Doppler frequency to be compensated by the DSP; s3, calculating a phase increment in real time by the DSP; s4, transmitting the updated phase increment to an internal RAM of the FPGA through an external memory interface of the DSP; s5, the FPGA reads the updated phase increment according to the signal processing completion mark of the frame; s6, calling a DDS IP core in the FPGA to synthesize a signal with required frequency; and S7, mixing the echo signal after Doppler compensation with the signal generated by the DDS IP core by the FPGA, and filtering to obtain a low-frequency baseband signal after digital down-conversion and Doppler compensation. The invention has the advantages of small calculated amount, easy realization of equipment, strong real-time property and easy maintenance and expansion.
Description
Technical Field
The invention relates to a digital down-conversion and Doppler compensation method, in particular to a digital down-conversion and Doppler compensation method for realizing adjustable phase increment by utilizing DSP and FPGA for cooperative processing, which can be applied to the field of radar signal processing in the aerospace field.
Background
As a key technology of intermediate frequency signal processing, digital down conversion can reduce the rate of a sampled signal while preserving the characteristics of the original signal. In order to solve the contradiction between the radar resolution and the action distance, the intermediate frequency signal needs to be subjected to pulse compression after being subjected to digital down-conversion. The bi-phase encoded signal has good autocorrelation properties but is sensitive to the doppler frequency of moving objects. When the target moving speed is high, the pulse compression effect is rapidly deteriorated, so that the effective compensation of the Doppler frequency shift has important significance for processing the two-phase encoding radar signals. With the development of the intermediate frequency signal processing technology and the improvement of the performance of the programmable hardware FPGA, the demand for quickly realizing the digital down conversion and the doppler compensation is increasingly urgent.
The input of the digital down-conversion and Doppler compensation processing is an intermediate frequency signal with a high speed, the input data volume is large, and the realization of the intermediate frequency signal is generally based on an FPGA chip. In recent years, with the development of signal processing technology, related researchers have proposed many methods for digital down-conversion and doppler compensation.
In a method and a system for realizing ultra-high-speed digital orthogonal down-conversion and decimation filtering in FPGA (patent application number: 201610227770.9; patent publication number: CN105915241A), two groups of ADC (analog-to-digital conversion) data signals and one group of ADC clock signals are subjected to cross-time domain synchronization processing, and the two groups of synchronized ADC data signals are respectively multiplied by four digital local oscillator signals output by a local numerically-controlled oscillator through four multipliers to complete the frequency shifting function of a digital domain.
In the patent of a method for realizing random extraction digital down-conversion based on the same FPGA multiplier resource (patent application number: CN 201210590839.6; patent publication number: CN103078592A), a shift register is utilized to change the data sequence, two paths of data with one time data rate are converted into one path of data with two times data rate, pre-processing is carried out according to the principle of coefficient symmetry, and multipliers are multiplexed under the conditions of different extraction rates to realize random extraction digital down-conversion.
In a patent ' FPGA data processing system and method for high-speed parallel down-conversion in vector signal analysis ' (patent application number: CN 201810574092.2; patent publication number: CN108762154A '), input intermediate-frequency signals are subjected to multi-path parallel data acquisition by means of analog front-end equipment, parallel data are received by the FPGA, and down-conversion of the multi-path high-speed parallel signals is completed by adopting a multi-path parallel cross frequency mixing method.
In the document "design and FPGA implementation of digital down conversion DDC" (published in "chinese integrated circuit", No.1, 2017), various filter designs of digital down conversion are introduced in detail, including a CIC filter, a HB filter, and a FIR filter, and verilog HDL programs are written to implement each module.
In the literature "design and implementation of digital down-conversion and pulse compression system" (published in "radar science and technology", No.2, 2010), digital down-conversion and pulse compression processing of variable points of 8K points or 2K points on actually acquired intermediate frequency Chirp signals is implemented on a single-chip FPGA.
In document "research on doppler characteristics and compensation algorithms of two-phase coded signals" (published in "electronic technology", No.9, 2013), a two-phase coding doppler compensation method based on MTD is proposed, which performs DFT on data of the same distance unit, then performs corresponding phase compensation on the signals in each doppler channel of the frequency domain, and then performs a pulse pressure modulo operation on each pulse.
As is known from the above patents and documents, no digital down-conversion method is currently available for converting an intermediate frequency signal into a low frequency signal with a varying frequency. The existing doppler compensation method needs to correct each data in the complex matrix, and the calculation amount is large.
Based on the above, the invention provides a digital down-conversion and Doppler compensation method based on the adjustable phase increment of the DSP and the FPGA, which realizes the digital down-conversion and Doppler compensation of the adjustable phase increment through the cooperative processing of the DSP and the FPGA, has strong real-time performance, and is easy to maintain and expand.
Disclosure of Invention
The invention aims to provide a digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment, which has the advantages of small calculated amount, easy realization of equipment, strong real-time property and easy maintenance and expansion.
In order to achieve the above object, the present invention provides a digital down-conversion and doppler compensation method based on adjustable phase increment of DSP and FPGA, comprising the following steps:
s1, carrying out staggered repetition frequency processing by the DSP and the FPGA by using the single pulse signal, and solving the speed blur of the high-speed moving target to obtain the real speed of the target;
s2, the DSP calculates the Doppler frequency to be compensated according to the real speed of the target, and the Doppler compensation is carried out on the echo signal reflected by the target after the radar is transmitted;
s3, calculating a phase increment in real time by the DSP;
s4, transmitting the phase increment updated in the S3 to an internal RAM of the FPGA through an external memory interface of the DSP;
s5, the FPGA reads the updated phase increment from the internal RAM according to the signal processing completion flag of the frame;
s6, calling a DDS IP core in the FPGA, inputting a reference clock and an updated phase increment to the DDS IP core, and synthesizing a signal with required frequency;
s7, the FPGA mixes the echo signal after Doppler compensation with the signal generated by the DDS IP core, shifts the echo signal frequency spectrum to a low-frequency baseband position, and performs filtering processing; and the DSP and the FPGA cooperatively work to obtain the low-frequency baseband signal after digital down-conversion and Doppler compensation in real time.
In S2, the DSP calculates the compensated Doppler frequency f in real time according to the real speed of the targetdReal-time Doppler compensation is carried out on echo signals which are transmitted by a radar and then reflected by a target; the method specifically comprises the following steps:
fd＝2×v_real/λ
wherein v _ real is the real speed of the target; λ is the wavelength of the echo signal.
In S3, according to the output frequency of the DDS IP output signal that needs to be achieved at present, a corresponding frequency control word, i.e., a phase increment K, is calculated in real time; the method specifically comprises the following steps:
wherein clk is the reference clock frequency of DDS IP; n is the bit width of the phase data; foutThe output frequency of the DDS IP output signal which is required to be reached currently.
The step S5 specifically includes the following steps:
s51, setting a signal processing completion flag of the frame in the FPGA;
s52, the FPGA judges whether the signal processing of the frame is finished; if so, the signal processing of the current frame finishes the sign turnover; if not, the signal processing completion flag of the frame is kept unchanged;
and S53, the FPGA selects the phase increment according to the signal processing completion flag of the frame.
In S53, the specific steps are: when the signal processing of the frame is finished and the mark is turned over, the FPGA reads the updated phase increment from the internal RAM and uses the phase increment; and when the signal processing completion mark of the frame is kept unchanged, the FPGA continues to use the current phase increment.
The step S6 specifically includes the following steps:
s61, setting parameters of a system clock, a channel number, a spurious-free dynamic range and a frequency resolution of the DDS IP core;
and S62, inputting a reference clock and an updated phase increment to the DDS IP core, so that the DDS IP core takes the reference clock as a reference, performs controllable interval sampling on the phase, and synthesizes sine and cosine signals with required frequency.
The step S7 specifically includes the following steps:
s71, mixing: performing ADC discretization sampling on the echo signal subjected to Doppler compensation to obtain an intermediate frequency signal; calling a multiplier, multiplying the intermediate frequency signal by a sine and cosine signal generated by a DDS IP core, and moving the frequency spectrum of the echo signal to a low-frequency baseband position;
s72, filtering: and filtering harmonic components generated in the mixing processing process through an FIR filter to obtain a low-frequency baseband signal containing target information.
In summary, compared with the prior art, the digital down-conversion and doppler compensation method based on the adjustable phase increment of the DSP and the FPGA provided by the present invention has the following advantages and beneficial effects:
1. according to the invention, each data in the complex matrix obtained by FPGA processing does not need to be corrected one by one, so that the overall calculation amount is small;
2. the invention calls the DDS IP core in the FPGA, does not need special DDS chips and other devices, has lower requirement on hardware equipment and is easy to realize;
3. the invention realizes real-time variable numerical control frequency synthesis and Doppler compensation by calling a DDS IP core and a small number of multipliers;
4. the invention realizes the combined processing of digital down-conversion and Doppler compensation by adjusting the phase increment, and has flexible operation;
5. the invention does not need to construct a sine signal lookup table through an amplitude/phase conversion circuit, occupies less internal memory and has wider application range;
6. the invention realizes the quick update of the phase increment by means of the strong computing power of the DSP chip and has strong real-time performance.
Drawings
FIG. 1 is a flow chart of a digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment in the present invention;
FIG. 2 is a schematic diagram of the connection relationship between the DSP and the FPGA in the present invention;
fig. 3 is a schematic diagram of a call process of a DDS IP core in the present invention.
Detailed Description
The technical contents, construction features, achieved objects and effects of the present invention will be described in detail by preferred embodiments with reference to fig. 1 to 3.
As shown in fig. 1, the digital down-conversion and doppler compensation method based on adjustable phase increment of DSP and FPGA provided by the present invention includes the following steps:
s1, performing staggered repetition frequency processing by using a single pulse signal through a DSP (digital signal processing) and an FPGA (field programmable gate array), and solving the speed ambiguity of the high-speed moving target to obtain the real speed of the target;
s2, the DSP calculates the Doppler frequency to be compensated according to the real speed of the target, and the Doppler compensation is carried out on the echo signal reflected by the target after the radar is transmitted;
s3, calculating a phase increment in real time by the DSP;
s4, transmitting the phase increment updated in S3 to an internal RAM (random access Memory) of the FPGA through an EMIF (External Memory Interface) of the DSP;
s5, the FPGA reads the updated phase increment from the internal RAM according to the signal processing completion flag of the frame;
s6, calling a DDS IP core arranged on the FPGA, inputting a reference clock and an updated phase increment to the DDS IP core, and synthesizing a signal with required frequency;
s7, the FPGA mixes the echo signal after Doppler compensation with the signal generated by the DDS IP core, shifts the echo signal frequency spectrum to a low-frequency baseband position, and performs filtering processing; and the DSP and the FPGA cooperatively work to obtain the low-frequency baseband signal after digital down-conversion and Doppler compensation in real time.
In S1, since the doppler frequency of the high-speed moving object tends to exceed a single PRF (pulse repetition frequency), the doppler spectrum is folded in the repetition frequency range, i.e., the speed is blurred. Under the condition, based on the sun theorem, the DSP and the FPGA utilize a single pulse signal to carry out staggered repetition frequency processing, a residual error table look-up method is adopted to solve the speed ambiguity of the high-speed moving target, and the real speed of the target is calculated.
In the embodiment, a target simulator is used for providing 20MHz intermediate frequency signals for a signal processing board where the DSP and the FPGA are located; setting the target speed to be 50 m/s; setting the radar frequency to be 10 GHz; the 3 repetition frequencies are set to prf 1-387 Hz, prf 2-499 Hz, and prf 3-517 Hz, respectively. According to the method in the S1, the DSP and the FPGA use the single pulse signal to carry out the stagger repetition frequency processing, the residual error table lookup method is adopted to solve the speed blur of the high-speed moving target, and then the real speed of the target is calculated to be 50 m/S.
The two-phase coded signal is sensitive to the Doppler frequency of a moving target, and is more obvious particularly when the target speed is higher. In order to avoid the mismatch between the received signal and the original matched filter, in S2, the doppler compensation is performed on the echo signal. Specifically, the method comprises the following steps:
setting a radar emission signal s (t) as:
s(t)＝u(t)exp[j2πfct]
wherein u (t) is a complex envelope signal; f. ofcIs the carrier frequency; t is the current time;
radar emission signal s (t) echo signal r reflected by target0(t) is:
wherein δ is an attenuation factor; f. ofdIs the doppler frequency of the target;
is a constant representing the phase shift produced by the target reflection;
for echo signal r0(t) performing down-conversion treatment to obtain a signal r (t) as follows:
wherein f isdIs the doppler frequency of the target; display deviceThe amplitude of the signal r (t) is then doppler frequency modulated.
According to the above, in step S2, the compensation doppler frequency f needs to be calculated in real time according to the real velocity of the target by using the fast processing capability of the DSPdThe real-time Doppler compensation is carried out on echo signals reflected by a target after radar transmission, and the real-time Doppler compensation method specifically comprises the following steps:
fd＝2×v_real/λ
wherein v _ real is the real speed of the target; λ is the wavelength of the echo signal.
In this embodiment, v _ real is 50 m/s; λ is 0.03m according to the radar frequency f ═ 10 GHz; the compensated Doppler frequency f is thus calculateddIs 3333 Hz.
When a traditional DDS chip is used for designing a signal generator, a phase accumulator, a sine ROM amplitude lookup table, a DAC (digital-to-analog converter), a LPF (low pass filter) and the like are required to be matched with the signal generator, the structure is complex, and the universality of the module is poor. With the improvement of the hardware level of the programmable logic device FPGA and the continuous development of the direct frequency synthesis technology, a DDS IP core (signal generator intellectual property core) has been developed on the FPGA platform. After numerical control frequency synthesis, the output frequency F of the output signal of the DDS IP coreoutComprises the following steps:
wherein K is a frequency control word; clk is the reference clock frequency of the DDS IP core; n is the phase data bit width in the phase accumulator.
Thus, for a single channel in the DDS IP core, its frequency control word is:
it can be seen that the output frequency of the DDS IP core depends on the frequency control word. Therefore, in step S3 of the present invention, the compensation Doppler frequency f can be obtained according to the fast calculation advantage of the DSPdAnd aWord down conversion frequency fcUpdating the output frequency F of the output signal of the desired DDS IP coreoutAnd F isout＝fc+fdAnd calculates the corresponding frequency control word K, i.e. the phase increment, in real time.
In this embodiment, the reference clock frequency of the DDS IP core is set to clk equal to 50MHz, the bit width of the phase data in the phase accumulator is set to N equal to 16, and after the synthesis according to the numerical control frequency, it is desirable to make the output frequency F of the output signal of the DDS IP core equal to 16out20.0033MHz, so the DSP calculates a phase increment of
The DSP has strong EMIF and can access various external memories such as SRAM, ROM and FLASH. Therefore, in S4, the updated phase increment obtained in S3 can be quickly transferred to the internal RAM of the FPGA by the EMIF of the DSP. As shown in fig. 2, taking an FPGA with model number JFM4VSX55RT and a DSP with model number SMJ320C6415 as examples, to access the internal RAM of the FPGA by the DSP, pins of the DSP required for EMIF communication are interfaced with corresponding pins of the FPGA.
In this embodiment, the phase of the update can be increased by EMIF of the DSP
And quickly transmitting to an internal RAM of the FPGA.
The step S5 specifically includes the following steps:
s51, setting a signal processing completion flag of the frame in the FPGA;
s52, the FPGA judges whether the signal processing of the frame is finished; if so, the signal processing of the current frame finishes the sign turnover; if not, the signal processing completion flag of the frame is kept unchanged;
s53, the FPGA selects a phase increment according to the signal processing completion flag of the frame; when the signal processing of the frame is finished and the mark is turned over, the FPGA reads the phase increment updated by the DSP from the internal RAM and uses the phase increment; when the signal processing completion flag of the current frame remains unchanged (not flipped), the FPGA continues to use the current phase increment (i.e., the FPGA does not read the phase increment updated by the DSP from the internal RAM).
In this embodiment, in S52, the pulse accumulation number is set to m, and a single pulse samples n points. After the FPGA finishes processing m pulses of the current frame, the signal processing of the current frame is considered to be finished, and the signal processing finishing mark of the current frame is turned over; when the FPGA does not finish processing m pulses of the current frame, the signal processing of the current frame is considered to be not finished, and the signal processing finishing mark of the current frame is kept unchanged. In the present invention, only after the signal processing of the present frame is completed, the relevant parameters of the signal processing, including of course the phase increment, can be modified.
In this embodiment, in S53, when the flag indicating that the signal processing of the current frame is completed is turned over, the FPGA reads the phase increment updated by the DSP from the internal RAM
And used.
The step S6 specifically includes the following steps:
s61, setting parameters such as a system clock, a channel number, a spurious-free dynamic range, a frequency resolution and the like of the DDS IP core; the DDS IP core can carry out numerical control frequency synthesis according to the requirement;
s62, as shown in fig. 3, a reference clock and an updated phase increment are input to the DDS IP core, so that the DDS IP core takes the reference clock as a reference, performs controllable interval sampling on the phase, and synthesizes a sine and cosine signal with a desired frequency.
In this embodiment, the system clock of the DDS IP core is set to 50MHz, the number of channels is 1, the spurious free dynamic range is 91, and the frequency resolution is 461.4258. Inputting a 50MHz reference clock and updated phase increment to a DDS IP core
And taking the reference clock as a reference, carrying out controllable interval sampling on the phase by using the DDS IP core, and synthesizing sine and cosine signals with required frequency of 20.0033 MHz.
The step S7 specifically includes the following steps:
s71, mixing: performing discretization sampling on the echo signal subjected to Doppler compensation by an ADC (analog-to-digital converter) to obtain an intermediate frequency signal; calling a multiplier, multiplying the intermediate frequency signal by a sine and cosine signal generated by a DDS IP core, and moving the frequency spectrum of the echo signal to a low-frequency baseband position required by the DSP;
s72, filtering: and filtering harmonic components generated in the mixing processing process by an FIR (finite impulse response) filter to obtain a low-frequency baseband signal containing target information, and performing downsampling extraction filtering to obtain the low-frequency baseband signal after digital down-conversion and Doppler compensation.
In summary, compared with the prior art, the digital down-conversion and doppler compensation method based on the adjustable phase increment of the DSP and the FPGA provided by the present invention has the following advantages and beneficial effects:
1. according to the invention, each data in the complex matrix obtained by FPGA processing does not need to be corrected one by one, so that the overall calculation amount is small;
2. the invention calls the DDS IP core in the FPGA, does not need special DDS chips and other devices, has lower requirement on hardware equipment and is easy to realize;
3. the invention realizes real-time variable numerical control frequency synthesis and Doppler compensation by calling a DDS IP core and a small number of multipliers; the invention occupies less memory in the realization process, and generally only needs 4 BRAMs (embedded block RAMs) of 18 k;
4. the invention realizes the combined processing of digital down-conversion and Doppler compensation by adjusting the phase increment, and has flexible operation;
5. the invention does not need to construct a sine signal lookup table through an amplitude/phase conversion circuit, occupies less internal memory and has wider application range;
6. the invention realizes the quick update of the phase increment by means of the strong computing power of the DSP chip and has strong real-time performance.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (7)
1. A digital down-conversion and Doppler compensation method based on adjustable phase increment of DSP and FPGA is characterized by comprising the following steps:
s1, carrying out staggered repetition frequency processing by the DSP and the FPGA by using the single pulse signal, and solving the speed blur of the high-speed moving target to obtain the real speed of the target;
s2, the DSP calculates the Doppler frequency to be compensated according to the real speed of the target, and the Doppler compensation is carried out on the echo signal reflected by the target after the radar is transmitted;
s3, calculating a phase increment in real time by the DSP;
s4, transmitting the phase increment updated in the S3 to an internal RAM of the FPGA through an external memory interface of the DSP;
s5, the FPGA reads the updated phase increment from the internal RAM according to the signal processing completion flag of the frame;
s6, calling a DDS IP core in the FPGA, inputting a reference clock and an updated phase increment to the DDS IP core, and synthesizing a signal with required frequency;
s7, the FPGA mixes the echo signal after Doppler compensation with the signal generated by the DDS IP core, shifts the echo signal frequency spectrum to a low-frequency baseband position, and performs filtering processing; and the DSP and the FPGA cooperatively work to obtain the low-frequency baseband signal after digital down-conversion and Doppler compensation in real time.
2. The DSP and FPGA adjustable phase increment-based digital down-conversion and doppler compensation method of claim 1 wherein in S2, the DSP calculates the compensated doppler frequency f in real time based on the real velocity of the targetdReal-time Doppler compensation is carried out on echo signals which are transmitted by a radar and then reflected by a target; the method specifically comprises the following steps:
fd＝2×v_real/λ
wherein v _ real is the real speed of the target; λ is the wavelength of the echo signal.
3. The digital down-conversion and doppler compensation method based on adjustable phase increment of DSP and FPGA of claim 2, wherein in S3, according to the output frequency of DDS IP output signal that needs to be achieved at present, the corresponding frequency control word, i.e. phase increment K, is calculated in real time; the method specifically comprises the following steps:
wherein clk is the reference clock frequency of DDS IP; n is the bit width of the phase data; foutThe output frequency of the DDS IP output signal which is required to be reached currently.
4. The DSP and FPGA adjustable phase increment-based digital down-conversion and doppler compensation method of claim 3, wherein said S5 specifically comprises the steps of:
s51, setting a signal processing completion flag of the frame in the FPGA;
s52, the FPGA judges whether the signal processing of the frame is finished; if so, the signal processing of the current frame finishes the sign turnover; if not, the signal processing completion flag of the frame is kept unchanged;
and S53, the FPGA selects the phase increment according to the signal processing completion flag of the frame.
5. The DSP and FPGA adjustable phase increment-based digital down-conversion and Doppler compensation method according to claim 4, wherein in S53, the method specifically comprises: when the signal processing of the frame is finished and the mark is turned over, the FPGA reads the updated phase increment from the internal RAM and uses the phase increment; and when the signal processing completion mark of the frame is kept unchanged, the FPGA continues to use the current phase increment.
6. The DSP and FPGA adjustable phase increment-based digital down-conversion and doppler compensation method of claim 5, wherein said S6 specifically comprises the steps of:
s61, setting parameters of a system clock, a channel number, a spurious-free dynamic range and a frequency resolution of the DDS IP core;
and S62, inputting a reference clock and an updated phase increment to the DDS IP core, so that the DDS IP core takes the reference clock as a reference, performs controllable interval sampling on the phase, and synthesizes sine and cosine signals with required frequency.
7. The DSP and FPGA adjustable phase increment-based digital down-conversion and doppler compensation method of claim 6, wherein said S7 specifically comprises the steps of:
s71, mixing: performing ADC discretization sampling on the echo signal subjected to Doppler compensation to obtain an intermediate frequency signal; calling a multiplier, multiplying the intermediate frequency signal by a sine and cosine signal generated by a DDS IP core, and moving the frequency spectrum of the echo signal to a low-frequency baseband position;
s72, filtering: and filtering harmonic components generated in the mixing processing process through an FIR filter to obtain a low-frequency baseband signal containing target information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011460814.5A CN112698321B (en) | 2020-12-11 | 2020-12-11 | Digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011460814.5A CN112698321B (en) | 2020-12-11 | 2020-12-11 | Digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112698321A true CN112698321A (en) | 2021-04-23 |
| CN112698321B CN112698321B (en) | 2023-03-17 |
Family
ID=75507333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011460814.5A Active CN112698321B (en) | 2020-12-11 | 2020-12-11 | Digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112698321B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1881839A (en) * | 2005-06-16 | 2006-12-20 | 华为技术有限公司 | Multi-channel parameter unloading method and device for wireless communication system physical layer |
| CN101017203A (en) * | 2006-09-26 | 2007-08-15 | 南京大桥机器有限公司 | Portable X wave range Doppler weather radar signal processing method and device thereof |
| CN101777939A (en) * | 2010-01-27 | 2010-07-14 | 哈尔滨工程大学 | DDS-based Doppler compensation device in real-time water sound communication |
| CN102594750A (en) * | 2012-02-15 | 2012-07-18 | 福建星海通信科技有限公司 | Method for generating mid-band modulation signal |
| CN105093183A (en) * | 2015-08-14 | 2015-11-25 | 上海航天测控通信研究所 | Doppler compensation method for tracking radar phase coding signals |
| CN106293991A (en) * | 2016-08-10 | 2017-01-04 | 上海无线电设备研究所 | FPGA anti-single particle based on ECC upset fast refresh circuitry and method |
| CN109085879A (en) * | 2017-06-13 | 2018-12-25 | 北京航天计量测试技术研究所 | A kind of high-precision DDS frequency synthesizer for the multi-functional calibration platform of electricity |
| CN110798210A (en) * | 2019-11-29 | 2020-02-14 | 深圳市鼎阳科技股份有限公司 | Frequency synthesizer |
| CN111367494A (en) * | 2018-12-26 | 2020-07-03 | 中国科学院长春光学精密机械与物理研究所 | Serial data frame receiving method and device |
| CN111983579A (en) * | 2020-08-14 | 2020-11-24 | 成都亘波雷达科技有限公司 | Method for eliminating radar speed ambiguity by using pulse repetition time of difference |
| CN112014833A (en) * | 2020-09-04 | 2020-12-01 | 上海无线电设备研究所 | High-speed target time-frequency domain detection method |
-
2020
- 2020-12-11 CN CN202011460814.5A patent/CN112698321B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1881839A (en) * | 2005-06-16 | 2006-12-20 | 华为技术有限公司 | Multi-channel parameter unloading method and device for wireless communication system physical layer |
| CN101017203A (en) * | 2006-09-26 | 2007-08-15 | 南京大桥机器有限公司 | Portable X wave range Doppler weather radar signal processing method and device thereof |
| CN101777939A (en) * | 2010-01-27 | 2010-07-14 | 哈尔滨工程大学 | DDS-based Doppler compensation device in real-time water sound communication |
| CN102594750A (en) * | 2012-02-15 | 2012-07-18 | 福建星海通信科技有限公司 | Method for generating mid-band modulation signal |
| CN105093183A (en) * | 2015-08-14 | 2015-11-25 | 上海航天测控通信研究所 | Doppler compensation method for tracking radar phase coding signals |
| CN106293991A (en) * | 2016-08-10 | 2017-01-04 | 上海无线电设备研究所 | FPGA anti-single particle based on ECC upset fast refresh circuitry and method |
| CN109085879A (en) * | 2017-06-13 | 2018-12-25 | 北京航天计量测试技术研究所 | A kind of high-precision DDS frequency synthesizer for the multi-functional calibration platform of electricity |
| CN111367494A (en) * | 2018-12-26 | 2020-07-03 | 中国科学院长春光学精密机械与物理研究所 | Serial data frame receiving method and device |
| CN110798210A (en) * | 2019-11-29 | 2020-02-14 | 深圳市鼎阳科技股份有限公司 | Frequency synthesizer |
| CN111983579A (en) * | 2020-08-14 | 2020-11-24 | 成都亘波雷达科技有限公司 | Method for eliminating radar speed ambiguity by using pulse repetition time of difference |
| CN112014833A (en) * | 2020-09-04 | 2020-12-01 | 上海无线电设备研究所 | High-speed target time-frequency domain detection method |
Non-Patent Citations (5)
| Title |
|---|
| 吴迪等: "随机参差重频法抗雷达导引头距离波门前拖研究", 《火控雷达技术》 * |
| 岳兵: "一种非线性调频脉冲压缩的多普勒补偿方法", 《信息化研究》 * |
| 李鹏: "基于FPGA的LFMCW雷达信号处理机研究", 《火控雷达技术》 * |
| 郭崇贤: "《相控阵雷达接收技术》", 31 March 2012 * |
| 郭敏等: "基于FPGA的一种数字下变频控制策略研究", 《电子测量技术》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112698321B (en) | 2023-03-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108427102B (en) | Radar baseband clutter generation device and method | |
| US7787533B2 (en) | Alternative method for equalizing DDS generated waveforms | |
| CN109765535B (en) | Simulation method and simulator for ultra-high speed target radar echo | |
| US3987285A (en) | Digital matched filtering using a step transform process | |
| US5684484A (en) | Method and apparatus for multi-channel digital reception and apparatus of ultrasonic diagnosis | |
| CN110488228B (en) | Linear frequency modulation signal generation method and device and storage medium | |
| JP2020060547A (en) | Radar target simulator in radar target simulation and method thereof | |
| JPH10304001A (en) | Modulator and modulation method | |
| CN109061580B (en) | Method for mitigating mutual interference of frequency modulation discontinuous continuous wave radar | |
| CN110045375A (en) | A kind of processing method and system of bit SAR echo data | |
| CN111337890A (en) | LFMCW radar target echo signal simulation method | |
| CN101190137A (en) | Real time digital quadrature demodulation method and device used in ultrasonic imaging system | |
| CN106772264A (en) | A kind of ground and spaceborne general ultra-wideband radar signal generating means and method | |
| CN107885276B (en) | Waveform generation method and generation device | |
| CN101621279A (en) | Method and device for digital down converter and filtering extraction | |
| CN101144857B (en) | Two-stage digital down frequency-change low-power consumption GPS receiver | |
| CN112698321B (en) | Digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment | |
| CN102353940B (en) | Pulse compression optimization method based on field programmable gate array (FPGA) | |
| CN114442046A (en) | Method, device, equipment and medium for generating modulation and selection separation radar waveform | |
| CN109633613A (en) | A kind of FPGA implementation method of hypersonic Platform Alliance pulse compression and the compensation of bullet speed | |
| CN105302225B (en) | A kind of production method of guinea pig echo frequency signal | |
| CN111220957B (en) | FPGA-based distance migration compensation system | |
| CN106125054A (en) | Digital phase control array antenna intermediate-freuqncy signal simulation source generating device | |
| CN109218238B (en) | Real signal Doppler frequency shift method based on Hilbert transform | |
| CN110808935B (en) | Accurate and efficient implementation method and device for autocorrelation operation of linear frequency modulation signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |