CN1877856A - Deep trench and high power MOS device and method for fabricating same - Google Patents
Deep trench and high power MOS device and method for fabricating same Download PDFInfo
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- CN1877856A CN1877856A CN 200510026546 CN200510026546A CN1877856A CN 1877856 A CN1877856 A CN 1877856A CN 200510026546 CN200510026546 CN 200510026546 CN 200510026546 A CN200510026546 A CN 200510026546A CN 1877856 A CN1877856 A CN 1877856A
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Abstract
The invention discloses a large-power MOS element and making method, which comprises the following steps: growing field oxide layer; removing silicon nitride, silicon oxide; growing hard mask; etching groove; injecting ion from bottom of groove; etching bottom of groove; removing hard mask; growing grid oxide layer and polysilicon grid; interconnecting metal layer. The invention produces thicker grid oxide layer of bottom than groove, which reduces parasitic capacitance CGD between grid and drain with excellent frequent property.
Description
Technical field
The present invention relates to the manufacture method of a kind of large-power MOS part and large-power MOS part, relate in particular to a kind of deep groove structure large-power MOS part and manufacture method thereof.
Background technology
Power MOS (Metal Oxide Semiconductor) device has better integration with respect to bipolar device, has become the main flow of current power device development.Deep slot type large-power MOS part opposite planar large-power MOS part, its integrated level is higher, thereby has satisfied the requirement of big electric current and low switch loss to greatest extent, makes the deep slot type large-power MOS part become the main flow of power MOS (Metal Oxide Semiconductor) device.
Present most high-performance large-power MOS part all is to adopt the deep groove structure large-power MOS part.This large-power MOS part advantage aspect low-power consumption is remarkable.
Along with the power MOS (Metal Oxide Semiconductor) device more applications in communication apparatus, the requirement of power MOS (Metal Oxide Semiconductor) device frequency characteristic is also improved constantly.But its deficiency aspect frequency characteristic is also more obvious.
The deep groove structure large-power MOS part structure of using always in the prior art as shown in Figure 1.Because it has used the vertical MOS-transistor structure, the MOS transistor primitive unit cell size of its MOS transistor primitive unit cell size opposite planar structure reduces greatly.So can integrated more MOS transistor primitive unit cell in same chip area, thereby have lowered power loss greatly.This is the advantage of this structure.
The circuit diagram of prior art deep groove structure large-power MOS part as shown in Figure 2.This deep groove structure large-power MOS part is having bigger parasitic capacitance between grid and the drain electrode and between grid and the source electrode.Parasitic capacitance comprises C
GDGate to drain capacitance) and C (grid-drain capacitance:
GS(grid-source electric capacity: gate to source capacitance).Parasitic capacitance C between grid and the drain electrode
GD, because the deep trench bottom area is big, C
GDCorresponding also very big.This has reduced the frequency characteristic of device widely.
As shown in Figure 4, the method step of manufacturing deep groove large power MOS device is as follows in the prior art:
The first step, the growth field oxide;
In second step, remove silicon nitride;
In the 3rd step, remove silicon dioxide;
The 4th step, the hard mask of growing up;
The 5th step, trench lithography;
The 6th step, the groove main etching;
The 7th step, channel bottom sphering etching;
In the 8th step, remove hard mask;
The 9th step, the growth gate oxide;
The tenth step, the growth polysilicon gate;
The 11 step, layer metal interconnection.
In above-mentioned prior art, the formation of deep trench need be through two step etching technics.The 6th step groove main etching makes groove reach the corresponding degree of depth, and the structure of groove as shown in Figure 6 after the groove main etching.Carry out channel bottom behind the groove main etching and inject when mixing, inject though require ion to be injected to 0 degree in theory, real technology can not definitely be 0 degree, and trenched side-wall has slight doping.The 7th step channel bottom sphering etching is an isotropic etching in the prior art, just in time can remove this part silicon that is doped of trenched side-wall during isotropic etching, and have only channel bottom to stay impurity, and this makes channel bottom become circle, and trenched side-wall is smooth.After the channel bottom sphering etching of carrying out above-mentioned steps the structure chart of deep groove large power MOS device as shown in Figure 7, wherein dotted line is the shape of the groove of groove main etching.
Summary of the invention
Technical problem to be solved by this invention provides a kind of deep groove large power MOS device, under the prerequisite of not sacrificing the low-power consumption characteristic, has frequency characteristic preferably.
Another technical problem that the present invention will solve provides a kind of method of making above-mentioned deep groove large power MOS device.
For solving the problems of the technologies described above, a kind of deep groove large power MOS device of the present invention, its deep trench bottom gate thickness of oxide layer is than the gate oxidation bed thickness on the groove.
For solving the problems of the technologies described above, the manufacture method of a kind of deep groove large power MOS device of the present invention may further comprise the steps:
The first step, the growth field oxide;
In second step, remove silicon nitride;
In the 3rd step, remove silicon dioxide;
The 4th step, the hard mask of growing up;
The 5th step, trench lithography;
The 6th step, the groove main etching;
In the 7th step, the channel bottom ion injects;
The 8th step, channel bottom sphering etching;
In the 9th step, remove hard mask;
The tenth step, the growth gate oxide;
The 11 step, the growth polysilicon gate;
The 12 step, layer metal interconnection.
A kind of deep groove large power MOS device of the present invention, deep trench bottom gate oxide layer has frequency characteristic preferably than the gate oxidation bed thickness on the groove.
A kind of method of making above-mentioned deep groove large power MOS device of the present invention, adding a step channel bottom ion in the middle of two step of deep trench etching technics injects, make deep trench bottom mix, thus when gate oxidation oxidation get faster thicker, thereby reduce parasitic capacitance between grid and the drain electrode.Can under the prerequisite of not sacrificing the low-power consumption characteristic, improve the frequency characteristic of device significantly.
Description of drawings
Below in conjunction with drawings and Examples the present invention is further described:
Fig. 1 is existing deep groove large power MOS device structure chart;
Fig. 2 is existing deep groove large power MOS device circuit diagram;
Fig. 3 is a deep groove large power MOS device structure chart of the present invention;
Fig. 4 is the manufacture method flow chart of existing deep groove large power MOS device;
Fig. 5 is the manufacture method flow chart of large-power MOS part of the present invention;
Fig. 6 is the structure chart of groove after the groove main etching in the prior art;
Fig. 7 is the structure chart of groove after the channel bottom sphering etching in the prior art.
Embodiment
The present invention proposes a kind of deep groove large power MOS device and a kind of method of making above-mentioned deep groove large power MOS device, applicable to the large-power MOS part manufacturing.
As shown in Figure 3, a kind of deep groove large power MOS device of the present invention, its deep trench bottom gate thickness of oxide layer is than the gate oxidation bed thickness on the groove.EPI N refers to N type outer rim layer among Fig. 3, and BODY is a transistor substrate.The C of large-power MOS part of the present invention
GDReduce greatly owing to the increase of gate oxide thickness.
As shown in Figure 5, a kind of method of making above-mentioned deep groove large power MOS device of the present invention may further comprise the steps: the first step, the growth field oxide (locally oxidized silicon, be called for short :); In second step, remove silicon nitride; In the 3rd step, remove silicon dioxide; The 4th step, the hard mask of growing up; The 5th step, trench lithography; The 6th step, the groove main etching; In the 7th step, the channel bottom ion injects; The 8th step, channel bottom sphering etching; In the 9th step, remove hard mask; The tenth step, the growth gate oxide; The 11 step, the growth polysilicon gate; The 12 step, layer metal interconnection.Wherein the hard mask growth in the 4th step can be adopted silicon dioxide.
The deep trench bottom gate thickness of oxide layer of a kind of deep groove large power MOS device of the present invention is than the gate oxidation bed thickness on the groove, and the parasitic capacitance between grid and the drain electrode is less, can improve the frequency characteristic of MOS device.
A kind of method of making above-mentioned deep groove large power MOS device of the present invention increases the step that the channel bottom ion injects between groove main etching and channel bottom sphering etching, make deep trench bottom mix and when gate oxidation oxidation get faster thicker, under the situation that does not influence grid oxide layer thickness on the normal groove, thus thicken deep trench bottom gate oxidated layer thickness reduce grid and the drain electrode between parasitic capacitance C
GDImprove its frequency characteristic.
Claims (2)
1. a deep groove large power MOS device is characterized in that, its deep trench bottom gate thickness of oxide layer is than the gate oxidation bed thickness on the groove.
2. a method of making the described deep groove large power MOS device of claim 1 is characterized in that, may further comprise the steps:
The first step, the growth field oxide;
In second step, remove silicon nitride;
In the 3rd step, remove silicon dioxide;
The 4th step, the hard mask of growing up;
The 5th step, trench lithography;
The 6th step, the groove main etching;
In the 7th step, the channel bottom ion injects;
The 8th step, channel bottom sphering etching;
In the 9th step, remove hard mask;
The tenth step, the growth gate oxide;
The 11 step, the growth polysilicon gate;
The 12 step, layer metal interconnection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510026546 CN1877856A (en) | 2005-06-08 | 2005-06-08 | Deep trench and high power MOS device and method for fabricating same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510026546 CN1877856A (en) | 2005-06-08 | 2005-06-08 | Deep trench and high power MOS device and method for fabricating same |
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| CN1877856A true CN1877856A (en) | 2006-12-13 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777497A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Production method of power MOS field-effect tube |
| CN102097378A (en) * | 2009-12-10 | 2011-06-15 | 力士科技股份有限公司 | Method for manufacturing trench metal-oxide semiconductor field effect transistor (MOSFET) |
| CN102569367A (en) * | 2010-12-22 | 2012-07-11 | 株式会社电装 | Silicon carbide semiconductor device and manufacturing method of the same |
-
2005
- 2005-06-08 CN CN 200510026546 patent/CN1877856A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097378A (en) * | 2009-12-10 | 2011-06-15 | 力士科技股份有限公司 | Method for manufacturing trench metal-oxide semiconductor field effect transistor (MOSFET) |
| CN102097378B (en) * | 2009-12-10 | 2013-12-04 | 力士科技股份有限公司 | Method for manufacturing trench metal-oxide semiconductor field effect transistor (MOSFET) |
| CN101777497A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Production method of power MOS field-effect tube |
| CN102569367A (en) * | 2010-12-22 | 2012-07-11 | 株式会社电装 | Silicon carbide semiconductor device and manufacturing method of the same |
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