CN102097378A - Method for manufacturing trench metal-oxide semiconductor field effect transistor (MOSFET) - Google Patents
Method for manufacturing trench metal-oxide semiconductor field effect transistor (MOSFET) Download PDFInfo
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- CN102097378A CN102097378A CN2009102534407A CN200910253440A CN102097378A CN 102097378 A CN102097378 A CN 102097378A CN 2009102534407 A CN2009102534407 A CN 2009102534407A CN 200910253440 A CN200910253440 A CN 200910253440A CN 102097378 A CN102097378 A CN 102097378A
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- 229910052721 tungsten Inorganic materials 0.000 claims description 14
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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Abstract
The invention discloses a method for manufacturing a trench metal oxide semiconductor field effect transistor (MOSFET). According to the trench MOSFET provided by the invention, the bottom of a trench grid in the epitaxial layer of the trench MOSFET has a thicker insulation layer compared with the side wall of the trench grid. The manufacture method provided by the invention avoids a bird beak effect generated by the thicker insulation layer at the bottom of the trench grid growing by utilizing a LOCOS (Local Oxidation Of Silicon) method in the prior art. Meanwhile, a shallow trench MOSFET based on the invention has lower Qgd (Grid Drain Charge) and lower Rds (Resource Drain Charge).
Description
Technical field
The present invention relates to a kind of cellular construction, device configuration and technology manufacturing of semiconductor power device, the cellular construction and the process of particularly a kind of groove MOSFET (mos field effect transistor).
Background technology
Has the problem of higher grid electric charge in order to solve conventional groove metal oxide semiconductor field effect tube (MOSFET), disclosed the shallow trench MOSFET structure that the degree of depth (to call shallow trench MOSFET in the following text) that a kind of dependence reduces trench gate reduces the grid electric charge in the prior art, the N raceway groove groove MOSFET shown in Figure 1A.Yet, in the process of etching contact trench, because the etch rate of polysilicon greater than the etch rate of monocrystalline silicon, causes the degree of depth Cdpoly (shown in Figure 1A) of grid contact trench to be about 1.5 times of degree of depth Cdsi (shown in Figure 1A) of source body contact trench easily.Simultaneously, because the degree of depth of trench gate reduces in the epitaxial loayer, therefore when etching grid contact trench 109, very easily produce the over etching phenomenon, the bottom that is grid contact trench 109 conventional trench gate extends into epitaxial loayer, thereby causes the metal plug in the grid contact trench 109 and the short circuit of drain electrode.
Another weak point of prior art is, from analysis of experimental data, shown in the curve that is positioned at the top among Fig. 2, increase for fear of source ohmic leakage Rds, difference between the degree of depth Pd (shown in Figure 1A) in degree of depth Td of trench gate (shown in Figure 1A) and tagma must be greater than 0.4 μ m, and this can cause the area that directly contacts between trench gate and the epitaxial loayer to increase, thereby causes grid leak charge Q gd (shown in Figure 1A) to increase.
In order further to reduce Qgd, another prior art (U.S. Patent number: 5,126,807) disclosed a kind of trench MOSFET structure, in this trench MOSFET structure, the thickness of the grid oxic horizon of trench gate bottom is greater than the thickness (having " than thick oxide layer " to call the trench gate bottom in the following text) of trench gate sidewall grid oxic horizon, shown in Figure 1B.Yet, what be positioned at trench gate bottom is to be carried out selective oxidation (LOCOS) and formed by the silicon to channel bottom than thick oxide layer 129, therefore have beak effect (Bird ' s Beak) zone 131 at the place, bottom that is positioned at sidewall nitride 130, the grid oxic horizon at trench gate bottom corners place is too weak to cause reducing of puncture voltage thereby this can cause.
Therefore, in field of semiconductor devices, especially in the design and manufacturing field of groove MOSFET, cellular construction, device configuration and manufacture method that a kind of novelty need be provided are to solve above-mentioned difficulty and design limitation.
Summary of the invention
The present invention has overcome the shortcoming that exists in the prior art, a kind of manufacture method of groove metal oxide semiconductor field effect transistor is provided, thereby has guaranteed that device has lower source ohmic leakage (Rds), less grid leak electric charge (Qgd) and bigger puncture voltage.
According to embodiments of the invention, the manufacture method of a kind of shallow trench metal oxide semiconductor field effect tube (MOSFET) is provided, comprising:
(a) operation that on substrate, forms epitaxial loayer and one deck dura mater is provided at the epitaxial loayer upper surface;
(b) upper surface at described dura mater provides trench mask plate and the described dura mater of etching and described epitaxial loayer to form the operation of described a plurality of grooves;
(c) form sacrificial oxide layer and eliminate the operation that etching process is introduced defective by removing this sacrificial oxide layer;
(d) form the operation of screen oxide at the inner surface of described a plurality of grooves;
(e) carry out the operation injected with the ion of described epitaxial loayer identical conduction type dopant;
(f) remove the operation of described screen oxide and described dura mater;
(g) form the operation of oxide layer at the inner surface of described a plurality of grooves and the upper surface of described epitaxial loayer as first insulating barrier;
(h) operation of unadulterated polysilicon layer of formation or amorphous silicon layer on described first insulating barrier;
(i) operation of formation nitride layer on described unadulterated polysilicon layer or amorphous silicon layer;
(g) described nitride layer is carried out the operation that anisotropic etching only keeps the nitride layer that is positioned at described a plurality of trenched side-walls; With
(k) unadulterated polysilicon layer or the amorphous silicon layer that is positioned at described a plurality of channel bottom and described epitaxial loayer upper surface carried out the operation that oxidation forms oxide layer, make to be positioned at the thickness of oxide layer of described a plurality of channel bottom and described epitaxial loayer upper surface greater than thickness of oxide layer along described a plurality of trenched side-walls.
According to embodiments of the invention, the manufacture method of another kind of shallow trench metal oxide semiconductor field effect tube (MOSFET) is provided, comprising:
(a) operation that on substrate, forms epitaxial loayer and one deck dura mater is provided at the epitaxial loayer upper surface;
(b) upper surface at described dura mater provides trench mask plate and the described dura mater of etching and described epitaxial loayer to form the operation of described a plurality of grooves;
(c) remove the operation of described dura mater;
(d) form sacrificial oxide layer and eliminate the operation that etching process is introduced defective by removing this sacrificial oxide layer;
(e) form the operation of screen oxide at the inner surface of described a plurality of grooves;
(f) carry out the operation injected with the ion of described epitaxial loayer identical conduction type dopant;
(g) remove the operation of described screen oxide;
(h) form the operation of oxide layer at the inner surface of described a plurality of grooves and the upper surface of described epitaxial loayer as first insulating barrier;
(i) operation of unadulterated polysilicon layer of formation or amorphous silicon layer on described first insulating barrier;
(j) operation of formation nitride layer on described unadulterated polysilicon layer or amorphous silicon layer;
(k) described nitride layer is carried out the operation that anisotropic etching only keeps the nitride layer that is positioned at described a plurality of trenched side-walls; With
(l) unadulterated polysilicon layer or the amorphous silicon layer that is positioned at described a plurality of channel bottom and described epitaxial loayer upper surface carried out the operation that oxidation forms oxide layer, make to be positioned at the thickness of oxide layer of described a plurality of channel bottom and described epitaxial loayer upper surface greater than thickness of oxide layer along described a plurality of trenched side-walls.
In some preferred embodiments, the manufacture method of described groove metal oxide semiconductor field effect pipe also comprises: (1) operation of deposit conductive region in described a plurality of grooves; (2) return quarter to remove unnecessary described conductive region to form the operation of trench gate; (3) form the operation of silicide at the top of described conductive region; (4) provide the operation of tagma mask plate; (5) ion that carries out the tagma dopant inject and the ion that advances this injection to form the operation in tagma; (6) etching is positioned at described on the described epitaxial loayer and arrives than thick oxide layer
Operation; (7) provide the operation of active region mask plate; (8) ion that carries out the source region dopant injects to form the operation in source region; (9) in the operation of deposit second insulating barrier on described epitaxial loayer and the described trench gate and the operation that source body contact trench mask plate is provided on this second insulating barrier; (10) described second insulating barrier of etching, described source region and described tagma are to form the operation of source body contact trench; (11) operation that removes described source body contact trench mask plate and grid contact trench mask plate is provided; (12) form the operation of grid contact trench according to described second insulating barrier of the definition etching of grid contact trench mask plate and described conductive region; (13) carrying out ion with described tagma identical conduction type dopant helps and carries out rapid thermal annealing and activate the ion of this injection to form the operation of the body contact zone that surrounds body contact trench bottom, described source; (14) in the inner surface deposit barrier layer Ti/TiN of described source body contact trench and described grid contact trench or the operation of Co/TiN or Ta/TiN; (15) depositing metal tungsten is filled described source body contact trench and described grid contact trench to form the operation of tungsten plug; (16) operation of resistance layer Ti or Ti/TiN and metal layer A l alloy or Cu alloy is fallen at the described second insulating barrier upper surface and described tungsten plug upper surface deposit successively; (17) provide metal mask plate and successively the described metal level of etching and the described resistance layer of falling to form the operation of source metal and grid metal.
More preferably, after described silicide forms and before described tagma mask plate is being provided, comprise that also operation that the guard ring mask plate is provided and the ion that carries out with epitaxial loayer films of opposite conductivity dopant inject to form the operation of guard ring.
More preferably, after the ion that carries out described source region dopant injects, also comprise the operation of the ion that advances this injection.
More preferably, as the metal field plate of termination environment, this metal field plate is arranged in the top in tagma, termination environment to described grid metal simultaneously, and the scope of covering epitaxial loayer is 2～10 μ m.
In some preferred embodiments, describedly on first insulating barrier, form unadulterated polysilicon layer 650 ℃ or above carrying out.
In some preferred embodiments, describedly carrying out below 650 ℃ forming amorphous silicon layer on first insulating barrier.
An advantage of the invention is, when etching is arranged in the described a plurality of groove of epitaxial loayer, after the deposition oxide layer, carries out ion with epitaxial loayer identical conduction type dopant and inject and form the doped region that surrounds described a plurality of channel bottoms.The introducing of this doped region can further reduce the Rds of device.With reference in the N raceway groove groove MOSFET shown in Figure 2, the comparison of experimental data when there is the As doped region in a plurality of channel bottoms described in the epitaxial loayer and does not have the As doped region, as can be seen, when there was the As doped region in the described a plurality of channel bottoms in the epitaxial loayer, the Rds of device was littler.Again with reference in figure 3 described these N raceway groove groove MOSFETs, concentration from epi-layer surface along each regional majority carrier of channel region, as can be seen, the concentration of described As doped region majority carrier will be higher than the concentration of majority carrier in the epitaxial loayer of this N raceway groove groove MOSFET.
Another advantage of the present invention is, unlike the prior art, a plurality of channel bottoms described in the epitaxial loayer is that unadulterated polysilicon or the amorphous silicon layer that utilizes oxidation to be positioned at described a plurality of channel bottom grid oxic horizons top obtains than thick oxide layer among the present invention, therefore, utilize groove MOSFET of the present invention can further reduce the Qgd of device and beak effect of the prior art can not occur and problem that the puncture voltage that causes reduces.
Another advantage of the present invention is, in manufacture process, the source body contact trench and the grid contact trench of device are to be defined respectively by two mask plates, and in twice different etching process, form respectively, this method can be avoided causing the problem of short circuit between the grid leak by the grid contact trench break-through trench gate bottom that utilizes the single mask plate to cause in the prior art.
Another advantage of the present invention is, in some preferred embodiments, when the ion of the doped region that is positioned at a plurality of channel bottoms described in the epitaxial loayer injected, the reduction of device electric breakdown strength was avoided in the termination environment that utilizes one deck dura mater to stop this ion-implanted device.
Another advantage of the present invention is in some preferred embodiments, can introduce the reduction of avoiding device electric breakdown strength with the guard ring of tagma identical conduction type in the termination environment of device, and the majority carrier concentration of this guard ring to be lower than described tagma.
The advantage of these and other execution modes of the present invention will be by the detailed description below in conjunction with accompanying drawing.
Description of drawings
Figure 1A is the cutaway view of groove MOSFET in the prior art.
Figure 1B is the cutaway view that has bottom the trench gate in the prior art than the groove MOSFET of thick oxide layer.
Fig. 2 is in the N raceway groove groove MOSFET, when there is the As doped region in channel bottom in the epitaxial loayer and does not have the As doped region, and the experimental data that concerns between the difference of gash depth Td and tagma degree of depth Pd and the Rds of device.
Fig. 3 for the N raceway groove groove MOSFET among Fig. 2 when channel bottom in the epitaxial loayer has the As doped region from epi-layer surface the concentration along channel direction various piece majority carrier.
Fig. 4 is the cutaway view of trench MOSFET structure according to an embodiment of the invention.
Fig. 5 is the cutaway view of trench MOSFET structure according to another embodiment of the invention.
Fig. 6 is the cutaway view of trench MOSFET structure according to another embodiment of the invention.
Fig. 7 A～7H is the cutaway view of the manufacture method of the trench MOSFET structure among Fig. 4.
Fig. 8 A～8B is the cutaway view of the manufacture method of the trench MOSFET structure among Fig. 5.
Fig. 9 is the cutaway view of the part manufacture method of the trench MOSFET structure among Fig. 6.
Embodiment
Explain the present invention with reference to the accompanying drawings, wherein show the preferred embodiments of the present invention.The present invention can, but embody in a different manner, but should not be confined to embodiment described herein.For example, the groove MOSFET of N raceway groove is quoted in the explanation here more, but clearly other devices also are possible.
With reference to the N raceway groove shallow trench MOSFET according to a preferred embodiment of the present invention shown in Fig. 4.N type epitaxial loayer 201 is formed on the N+ substrate 200, the a plurality of grooved inner surfaces that are formed in the described epitaxial loayer are lined with grid oxic horizon 202 and fill the trench gate 211 that forms a plurality of trench gate 210 and at least one broad with the polysilicon that mixes, and the trench gate 211 of wherein said at least one broad is used to connect the grid metal.Especially, described grid oxic horizon 202 is positioned at the thickness of each channel bottom greater than its thickness along trenched side-wall.N is arranged at the bottom in each trench gate
*Doped region 203, the concentration of its majority carrier is greater than described epitaxial loayer.P type tagma 204 is formed between per two adjacent grooves grid, and, in zone, N+ source region 205 is arranged between per two adjacent grooves grid 210 near the tagma upper surface.This groove MOSFET also comprises: source body contact trench, and this source body contact trench is filled with tungsten plug 208 and is passed insulating barrier 206, described source region 205 and extend into described tagma 204; Grid contact trench, this grid contact trench are filled with the tungsten plug 209 and the trench gate 211 of passing described insulating barrier 206 and extending into described at least one broad; P+ body contact zone 207, this body contact zone are positioned at the below, bottom of each described source body contact trench.In addition, source metal 212 links to each other with described tagma 204 with described source region 205 by the tungsten plug 208 in the body contact trench of described source; Grid metal 212 ' links to each other with the trench gate 211 of described at least one broad by the tungsten plug 209 in the described grid contact trench.Described 212 ' the while of grid metal is as the metal field plate of termination environment, and the scope of covering termination environment epitaxial loayer is between 2～10 μ m.
With reference to the N raceway groove shallow trench MOSFET of the another one preferred embodiment of the present invention shown in Fig. 5, the main difference of this structure and structure shown in Figure 4 is that there is n in the epitaxial loayer upper surface in the termination environment
*Doped region 303 '.This n
*Doped region 303 ' is near the tagma 304 in the termination environment, and it is owing to when forming the doped region 303 of trench gate bottom, does not use the barrier layer of dura mater as the termination environment, thus n
*The n of doped region 303 ' bottom trench gate
*Doped region 303 forms simultaneously.
With reference to the N raceway groove shallow trench MOSFET according to a further preferred embodiment of the invention shown in Fig. 6.Compare with Fig. 5, there is p-guard ring 414 in the structure among Fig. 6 in the termination environment.This guard ring 414 is positioned at metal field plate 412 ' below, and is positioned at n
*Between doped region 403 ' and the tagma 404.
Fig. 7 A～7H shows the processing step of the shallow trench of N raceway groove shown in the shop drawings 4 MOSFET.In Fig. 7 A, at first on N+ substrate 200, grow N type epitaxial loayer 201, deposit one deck dura mater, for example oxide layer or oxide/nitride/oxide on this epitaxial loayer 201 then.Then, above this dura mater, provide trench mask plate (not shown) and carry out the groove 211a that etching forms a plurality of groove 210a and at least one broad.
In Fig. 7 B, one deck sacrificial oxide layer (not shown) and eliminate the defect silicon that causes in the etching process of at first growing by removing this sacrificial oxide layer.Afterwards, growth one deck screen oxide and carry out the n that the As ion inject to form the below, groove 211a bottom that is positioned at a plurality of groove 210a and at least one broad
* Doped region 203, and this n
*The majority carrier concentration of doped region 203 is higher than described epitaxial loayer 201.
In Fig. 7 C, at first remove described screen oxide and described dura mater, upper surface deposit successively one deck grid oxic horizon 202a, the unadulterated polysilicon of one deck or amorphous silicon 202b and one deck nitride 202c of the inner surface of the groove 211a that follows at described a plurality of groove 210a and at least one broad and described epitaxial loayer.Subsequently, described nitride 202c is carried out anisotropic etching, only keep the part that it is positioned at the groove 211a sidewall of described a plurality of groove 210a and at least one broad.
In Fig. 7 D, oxidation is carried out in the bottom of the groove 211a that is positioned at described a plurality of groove 210a and at least one broad and the described unadulterated polysilicon or the amorphous silicon 202b that are positioned at described epitaxial loayer 201 upper surfaces, obtain being positioned at channel bottom and epitaxial loayer upper surface than thick oxide layer.
In Fig. 7 E, after removing the nitride layer that is positioned at trenched side-wall, deposit conductive region in the groove 211a of described a plurality of groove 210a and at least one broad, for example the mixture of the polysilicon of polysilicon of Can Zaing or doping and unadulterated polysilicon also forms the trench gate 211 of a plurality of trench gate 210 and at least one broad by chemico-mechanical polishing (Chemical MechanicalPolishing) or plasma etching (Plasma Etch), forms the silicide (not shown) to reduce resistance at the top of described conductive region afterwards.Then, the ion that tagma mask plate (not shown) is provided and carries out the tagma dopant inject and diffusion to form P type tagma 204.Afterwards, will be positioned at being etched to thickness than thick oxide layer and being of described epitaxial loayer upper surface
Active region mask plate (not shown) is provided then and carries out the ion injection and the propelling (when the active area depth of needs formation is more shallow, not advancing the step of source region dopant) of source region dopant, to form N+ source region 205.
In Fig. 7 F, at first at upper surface deposit second insulating barrier 206, for example oxide skin(coating) of the trench gate 211 of described epitaxial loayer 201, described a plurality of trench gate 210 and at least one broad.Then, provide source body contact trench mask plate, and, form source body contact trench 208a by described second insulating barrier 206 of etching, described source region 205 and described tagma 204.In Fig. 7 G, at first remove described source body contact trench mask plate, and grid contact trench mask plate is provided, by the conductive region in the trench gate 211 of described second insulating barrier 206 of etching and at least one broad, form grid contact trench 209a then.Afterwards, the ion that carries out BF2 injects the p+ body contact zone 207 that is positioned at below, described source body contact trench 208a bottom with formation, and activates dopant ion by rapid thermal annealing (Rapid Thermal Annealing).
In Fig. 7 H, at first at the inner surface of described source body contact trench 208a and described grid contact trench 209a and upper surface deposit one deck barrier layer Ti/TiN or the Co/TiN or the Ta/TiN of described second insulating barrier 206, and depositing metal tungsten forms tungsten plug 208 and tungsten plug 209 respectively to fill described source body contact trench 208a and grid contact trench 209a on this barrier layer.Subsequently, resistance layer Ti or Ti/TiN fall in the upper surface deposit one deck at described second insulating barrier 206, described tungsten plug 208 and tungsten plug 209, and deposited metal Al alloy or Cu alloy on the resistance layer fall at this, by being provided, metal mask plate and etching form source metal 212 and grid metal 212 '.
Fig. 8 A～8B shows the part processing step of the shallow trench of N raceway groove described in the shop drawings 5 MOSFET.In Fig. 8 A, the N epitaxial loayer 301 of at first on N+ substrate 300, growing, and on this epitaxial loayer 301, provide one deck dura mater.Then, the trench mask plate is provided and passes through the described dura mater of etching and the groove 311a of the described epitaxial loayer 301 a plurality of groove 310a of formation and at least one broad at described dura mater upper surface.Subsequently, remove described dura mater, growth one deck sacrificial oxide layer is also eliminated the defective that may introduce in etching process by removing this sacrificial oxide layer.Then, growth one deck screen oxide, and carry out the As ion and inject the n that is positioned at the groove 311a bottom of described a plurality of groove 310a and described at least one broad with formation
*Standing mixes goes 303, and the n of close described epitaxial loayer 301 upper surfaces
*Doped region 303 '.And described n
* Doped region 303 and 303 ' majority carrier concentration are higher than described epitaxial loayer.
In Fig. 8 B, at first remove described sacrificial oxide layer, it is identical with step after the dura mater to remove sacrificial oxide layer among step afterwards and Fig. 7 C～7H.
Fig. 9 shows the part processing step of the shallow trench of N raceway groove shown in the shop drawings 6 MOSFET.Be that with the difference of structure shown in the shop drawings 5 before the tagma mask plate was provided, the ion that one deck guard ring mask plate is provided earlier and carries out P type dopant injected and to be positioned at tagma 404 and n with formation
*Guard ring 414 between the doped region 403 '.
Although various embodiment have been described, are appreciated that without departing from the spirit and scope of the present invention and can make various modifications the present invention at this.For example, can form the structure of its conduction type and the various semiconductor regions of opposite conduction type described in the literary composition with method of the present invention, but the modification of having done should be forgiven within the scope of protection of present invention.
Claims (9)
1. the manufacture method of a groove metal oxide semiconductor field effect pipe is characterized in that, comprising:
The operation that on substrate, forms epitaxial loayer and one deck dura mater is provided at the epitaxial loayer upper surface;
Upper surface at described dura mater provides trench mask plate and the described dura mater of etching and described epitaxial loayer to form the operation of described a plurality of grooves;
Form sacrificial oxide layer and eliminate the operation that etching process is introduced defective by removing this sacrificial oxide layer;
Form the operation of screen oxide at the inner surface of described a plurality of grooves;
Carry out the operation injected with the ion of described epitaxial loayer identical conduction type dopant;
Remove the operation of described screen oxide and described dura mater;
Form the operation of oxide layer at the inner surface of described a plurality of grooves and the upper surface of described epitaxial loayer as first insulating barrier;
On described first insulating barrier, form the operation of unadulterated polysilicon layer or amorphous silicon layer;
On described unadulterated polysilicon layer or amorphous silicon layer, form the operation of nitride layer;
Described nitride layer is carried out the operation that anisotropic etching only keeps the nitride layer that is positioned at described a plurality of trenched side-walls; With
Unadulterated polysilicon layer or the amorphous silicon layer that is positioned at described a plurality of channel bottom and described epitaxial loayer upper surface carried out the operation that oxidation forms oxide layer, make to be positioned at the thickness of oxide layer of described a plurality of channel bottom and described epitaxial loayer upper surface greater than thickness of oxide layer along described a plurality of trenched side-walls.
2. the manufacture method of a groove metal oxide semiconductor field effect pipe is characterized in that, comprising:
The operation that on substrate, forms epitaxial loayer and one deck dura mater is provided at the epitaxial loayer upper surface;
Upper surface at described dura mater provides trench mask plate and the described dura mater of etching and described epitaxial loayer to form the operation of described a plurality of grooves;
Remove the operation of described dura mater;
Form sacrificial oxide layer and eliminate the operation that etching process is introduced defective by removing this sacrificial oxide layer;
Form the operation of screen oxide at the inner surface of described a plurality of grooves;
Carry out the operation injected with the ion of described epitaxial loayer identical conduction type dopant;
Remove the operation of described screen oxide;
Form the operation of oxide layer at the inner surface of described a plurality of grooves and the upper surface of described epitaxial loayer as first insulating barrier;
On described first insulating barrier, form the operation of unadulterated polysilicon layer or amorphous silicon layer;
On described unadulterated polysilicon layer or amorphous silicon layer, form the operation of nitride layer;
Described nitride layer is carried out the operation that anisotropic etching only keeps the nitride layer that is positioned at described a plurality of trenched side-walls; With
Unadulterated polysilicon layer or the amorphous silicon layer that is positioned at described a plurality of channel bottom and described epitaxial loayer upper surface carried out the operation that oxidation forms oxide layer, make to be positioned at the thickness of oxide layer of described a plurality of channel bottom and described epitaxial loayer upper surface greater than thickness of oxide layer along described a plurality of trenched side-walls.
3. according to the manufacture method of claim 1 or 2 described groove metal oxide semiconductor field effect pipes, it is characterized in that, the unadulterated polysilicon layer that is positioned at described a plurality of channel bottom and described epitaxial loayer upper surface or amorphous silicon layer are carried out oxidation form after the operation of oxide layer, also comprise:
The operation of deposit conductive region in described a plurality of grooves;
Return and carve to remove unnecessary described conductive region to form the operation of trench gate;
Form the operation of silicide at the top of described conductive region;
The operation of tagma mask plate is provided;
Carry out the ion injection of tagma dopant and advance the operation of the ion of this injection with the formation tagma;
The described thicker oxide layer that etching is positioned at described epitaxial loayer upper surface arrives
Operation;
The operation of active region mask plate is provided;
The ion that carries out the source region dopant injects to form the operation in source region;
In the operation of deposit second insulating barrier on described epitaxial loayer and the described trench gate and the operation that source body contact trench mask plate is provided on this second insulating barrier;
Described second insulating barrier of etching, described source region and described tagma are to form the operation of source body contact trench;
The operation that removes described source body contact trench mask plate and grid contact trench mask plate is provided;
Operation according to described second insulating barrier of the definition etching of grid contact mask plate and described conductive region formation grid contact trench;
Carrying out ion with the dopant of described tagma identical conduction type injects and carries out rapid thermal annealing and activate the ion of this injection to form the operation of the body contact zone that surrounds body contact trench bottom, described source;
In the inner surface deposit barrier layer Ti/TiN of described source body contact trench and described grid contact trench or the operation of Co/TiN or Ta/TiN;
Depositing metal tungsten is filled described source body contact trench and described grid contact trench to form the operation of tungsten plug;
The operation of resistance layer Ti or Ti/TiN and metal layer A l alloy or Cu alloy is fallen at the described second insulating barrier upper surface and described tungsten plug upper surface deposit successively; With
Provide metal mask plate and successively the described metal level of etching and the described resistance layer of falling to form the operation of source metal and grid metal.
4. according to the manufacture method of the described groove metal oxide semiconductor field effect pipe of claim 3, it is characterized in that, be arranged in the polysilicon of described conductive region for mixing of groove.
5. according to the manufacture method of the described groove metal oxide semiconductor field effect pipe of claim 3, it is characterized in that, after described silicide forms and before described tagma mask plate is being provided, also comprise:
The operation of guard ring mask plate is provided; With
Carry out injecting to form the operation of guard ring with the ion of the dopant of epitaxial loayer films of opposite conductivity.
6. according to the manufacture method of the described groove metal oxide semiconductor field effect pipe of claim 3, it is characterized in that, after the ion that carries out described source region dopant injects, also comprise the operation of the ion that advances this injection.
7. according to the manufacture method of the described groove metal oxide semiconductor field effect pipe of claim 3, it is characterized in that, as the metal field plate of termination environment, this metal field plate is arranged in the top in tagma, termination environment to described grid metal level simultaneously, and the scope of covering epitaxial loayer is 2～10 μ m.
8. according to the manufacture method of claim 1 or 2 described groove metal oxide semiconductor field effect pipes, it is characterized in that when forming described unadulterated polysilicon layer on described first insulating barrier, described unadulterated polysilicon layer is 650 ℃ or above formation.
9. according to the manufacture method of claim 1 or 2 described groove metal oxide semiconductor field effect pipes, it is characterized in that when forming described amorphous silicon layer on described first insulating barrier, described amorphous silicon layer is forming below 650 ℃.
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