CN1873634A - Card controller, and method for controlling IC card - Google Patents
Card controller, and method for controlling IC card Download PDFInfo
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- CN1873634A CN1873634A CNA2005100263510A CN200510026351A CN1873634A CN 1873634 A CN1873634 A CN 1873634A CN A2005100263510 A CNA2005100263510 A CN A2005100263510A CN 200510026351 A CN200510026351 A CN 200510026351A CN 1873634 A CN1873634 A CN 1873634A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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Abstract
The invention discloses an IC card controller and a method that an IC card controller can control multi (N) IC card. The IC card controller include :control cell, clock signal pin, reset signal pin and data exchange pin; simultaneity, the IC card controller includes Multi(N) electrify control signal pin, and configure controller cell as a reset signal and Multi(N) electrify control signal, the IC card controller work uses time multiplexing among clock signal pin, and reset signal pin and data exchange pin, so ,it is possible that one IC card controller can control Multi(N) IC card(N>1,N is integer).
Description
Technical field
The present invention relates to a kind of IC-card controller, control an above IC-card job with an IC-card controller by the time division multiplex realization of stitch (pin).The invention still further relates to a kind of method of controlling more than one IC-card with an IC-card controller.
Background technology
1970, Frenchman rowland De Moruinuo (Roland Moreno) IC (Integrated Circuit) chip that is provided with of can programming for the first time was put in the card, makes card have more function.He had done following elaboration to this invention in application for patent at that time: have the storer that can carry out self-protection on the card.First IC-card in the world so just has been born.
After IC-card occurs, in the world it there is multiple call.English name has " Smart Card ", " IC Card " etc.; Particularly port, tableland district in the Asia, then " smart card ", " smart cards " of being called reach " smart card " etc. more; And in the China mainland area, people generally are referred to as " IC-card " or " smart card ".Below we are referred to as IC-card.
With reference to figure 1, Fig. 1 is the sketch of a common IC-card 10.As shown in Figure 1, has IC-card chip 11 (hereinafter for convenience's sake, with they unified IC-cards that is called, this is to understand easily for a person skilled in the art) in the IC-card 10.IC-card 10 generally has 8 contact C1～C8, and the definition of each contact is as shown in table 1:
Table 1
| Touch period | Distribute | Touch period | Distribute |
| C1 | Supply voltage (VCC) | C5 | Ground (GND) |
| C2 | (RST) resets | C6 | Program voltage (VPP) |
| C3 | Clock (CLK) | C7 | I/O (I/O) |
| C4 | Keep and treat following the use | C8 | Keep and treat following the use |
The particular content of relevant IC-card standard please be joined ISO7816, is not described further here.As those skilled in the art was known, the contact of IC-card was not limited to 8, but depended on specific application scenario.For example, in the example shown in the above-mentioned table 1, IC-card 10 can omit contact C4 and C8 and only have 6 contacts.Therefore, according to specific application scenario, those skilled in the art can design the IC-card with different number of contacts.
IC-card has a wide range of applications at aspects such as finance, communication, pay TVs.Be divided into storage card, encrypt storage card, CPU card and RF card four big classes.Can touch a lot of IC-cards in the daily life, as the SIM card in phone IC-card, Bus Card, the mobile phone.Card can also be divided into contact and contactless IC-card.
The deciphering of charge Digital Television realizes by IC-card that generally the program that operator provided needs corresponding IC-card to decipher, if there are a plurality of operators, just needs the IC-card of corresponding number.At present, the digital TV set-top box of selling on the market has only an IC-card slot, just needs to change the IC-card in the slot if will watch program that different operators provides, and is cumbersome, and frequent plug can make IC-card and IC-card slot quicken to damage.As known in the art, a plurality of IC-card slots are set just need correspondingly be increased the IC-card controller and control IC-card work, but so will increase taking of area of chip, chip periphery pin number and system resource, be unfavorable for reducing the design and the manufacturing cost of chip.
With reference to figure 2, Fig. 2 illustrates two IC-card controllers: IC-card controller 21 and IC-card controller 22; Two IC-card interface chips: IC-card interface chip 211 and IC-card interface chip 221; And two IC-cards: the logic relation picture that is connected of IC-card 212 and IC-card 222.
IC- card interface chip 211 and 221 can adopt the known various IC-card interface chips of industry, for example can adopt TDA8004AT chip of PHILIPS Co.'s design or the like.At this, it mainly act as voltage coupling, and certainly, this part function also can be integrated in the IC-card controller and save this interface chip.Here, TDA8004AT is that example describes (those skilled in the art can adopt other present interfaces chip certainly, and the stitch definition of these interface chips is similar with the stitch definition of TDA8004AT, does not do tired stating here).
The stitch definition of TDA8004AT is as shown in table 2:
Table 2
| The stitch title | Distribute |
| OFF | The signal output (corresponding) whether IC-card exists with PRES |
| CMDVCC | Electric control signal input on the IC-card |
| XTAL1 | The clock input |
| RSTIN | The |
| 3V/5V | Voltage is selected the control signal input |
| I/OUC | The data I/O |
| RST | Reset signal output (corresponding) with RST |
| CLK | Clock output (corresponding) with XTAL1 |
| I/O | Data I/O (corresponding) with I/OUC |
| VCC | IC-card supply voltage (controlled by CMDVCC) |
| GND | Ground |
| PRES | The signal input whether IC-card exists |
IC-card controller 21 and the definition of 22 stitch (only enumerate the stitch definition of IC-card controller 21 here, the stitch of IC-card controller 22 is identical with the definition of IC-card controller 21) as shown in table 3:
Table 3
| The stitch title | Distribute |
| i_sc_detect1_b | The signal input whether IC- |
| o_vcc_en1_b | Electric control signal output on the IC- |
| o_sc_clk | Clock output |
| o_sc_rstin_b | Reset signal output |
| 3v5 | Voltage is selected control signal output |
| b_sc_data_b | Data exchange channel |
IC-card slot (not shown) is provided with the whether terminal in groove of test card, and detection signal is delivered to the PRES pin of IC-card interface chip 211, IC-card interface chip 211 is delivered to the i_sc_detect1_b pin of IC-card controller 21 to this signal by the OFF pin again, tells whether IC-card controller 21 is inserted with IC-card 212 in the IC-card slot.
The GND pin of IC-card interface chip 211 is connected with the C5 contact of IC-card 212, and the earth level of standard is provided for IC-card.
The o_sc_vcc_en1_b pin of IC-card controller 21 is connected with the CMDVCC pin of IC-card interface chip 211.When IC-card controller 21 will be operated IC-card 212, the o_sc_vcc_en1_b human hair combing waste goes out power on signal, this signal is a lasting level, make the VCC pin of IC-card interface chip 211 produce the operation level of IC-card 212 from this level of CMDVCC pin input, the C1 contact by IC-card 212 provides operating voltage for IC-card 212.
The b_sc_data_b pin of IC-card controller 21 is connected with the C7 contact of IC-card 212 by the I/OUC pin and the I/O pin of IC-card interface chip 211, realizes the exchanges data of IC-card controller 21 and IC-card 212.
The o_sc_clk pin of IC-card controller 21 outputs to the XTAL1 pin of IC-card interface chip 211 to clock, and IC-card interface chip 211 outputs to the C3 contact of IC-card 212 to clock by the CLK pin again, for IC-card 212 provides work clock.
The o_sc_rstin_b pin of IC-card controller 21 is connected with the RSTIN pin of IC-card interface chip 211, and the RST pin of IC-card interface chip 211 is connected with the C2 contact of IC-card 212, and reset signal is delivered to IC-card 212 from IC-card controller 21.
The C6 contact of IC-card 212 is that the program voltage of IC-card 212 inserts, in using, this does not need IC-card 212 is programmed, so do not use this contact (it is emphasized that here the using method about programming contact C6 is known for a person skilled in the art).
Signal flow between IC-card controller 22, IC-card interface chip 221 and the IC-card 222 to IC-card controller 21, IC-card interface chip 211 and IC-card 212 between signal flow to identical, so in this omission.
Fig. 3 illustrates the logic diagram of prior art IC-card controller 21.IC-card controller 21 comprises bus interface module (BUS Interface) 311, direct memory access module (DMA Mode) 312, clock generator (SC_CLK Generator) 313, register module (REGs) 314, cache module (TX/RX_FIFO) 315, transceiver (Transceiver) 316, baud rate generation module (Baudrate) 317.Wherein, bus interface module 311 is connected with system bus (BUS) 32, finishes the exchanges data of IC-card controller 21 and system's (not shown); Direct memory access module 312 can send the DMA request to system by bus interface module 311 and system bus 32 under the control of register module 314, the IC-card controller 21 and the exchanges data of system are carried out under the DMA pattern; Clock generator 313 produces the needed clock o_sc_clk of IC-card work under the control of register module 314; Cache module 315 is connected with transceiver 316 and register module 314 respectively, becomes the exchanges data path of IC-card and system; Baud rate generation module 317 produces the clock enable signal of certain baud rate and gives transceiver under the control of register module 314, the exchanges data speed that control IC-card and IC-card controller are 21; Register module 314 is control centers of entire I C card controller 21, and it receives the signal input I_sc_detect1_b whether IC-card exists, electric control signal output o_vcc_en1_b and reset signal output o_sc_rstin_b on the output IC-card.
Summary of the invention
For chip design, the peripheral stitch of chip is very precious, under the situation of above-mentioned example, increase an IC-card controller and just will increase by 6 stitch, simultaneously also can increase area of chip, also can take the register interface of a bus more, be unfavorable for reducing the chip design and manufacturing cost.
Therefore, the present invention provides a kind of IC-card controller in view of the above problems, has: control module; Go up the electric control signal pin for clock signal pin, reset signal pin, exchanges data pin and N; Described control module is configured to provide a reset signal and the individual electric control signal of going up of N, this IC-card controller carries out time division multiplex to clock signal pin, reset signal pin and exchanges data pin, with N IC-card of an IC-card controller control, wherein N is the integer greater than 1.
The present invention also provides a kind of method with N IC-card of an IC-card controller control, wherein N is the integer greater than 1, described IC-card controller carries out time division multiplex to reset signal pin, clock signal pin and the exchanges data pin that is used for a described N IC-card, and the last electric control signal that is used for a described N IC-card is controlled separately.
The present invention utilizes an IC-card controller to operate different IC-cards by the time division multiplex of stitch in needs, have the advantages such as register interface of saving chip area, chip periphery pin number and system bus, be beneficial to the design and the manufacturing cost that reduce chip.Design proposal of the present invention gets final product because in the process of Digital Television deciphering, only need operate, so can not influence actual use to an IC-card.Therefore, the present invention has advantages such as the system resource of saving, reduction chip area, minimizing chip periphery stitch.
Description of drawings
Fig. 1 is the structure diagram of common IC-card in the prior art.
Fig. 2 is the connection logic relation picture of two IC-card controllers, two IC-card interface chips and two IC-cards in the prior art.
Fig. 3 is the logic diagram of prior art IC-card controller.
Fig. 4 is the logic relation picture that is connected of IC-card controller and IC-card interface chip and IC-card according to an embodiment of the invention.
Fig. 5 is the logic diagram of IC-card controller according to an embodiment of the invention.
Fig. 6 is the generation circuit of IC-card power on signal according to an embodiment of the invention.
Embodiment
With reference to figure 4, Fig. 4 illustrates the logic relation picture that IC-card controller 31 and two IC- card interface chips 211 and 221 and two IC-cards 212 according to an embodiment of the invention are connected with 222.The IC-card controller stitch definition of the embodiment of the invention is as shown in table 4:
Table 4
| The stitch title | Distribute |
| i_sc_detect1_b | The signal the input whether IC-card of IC-card 1 exists |
| o_sc_vcc_en1_b | Electric control signal output on the IC-card of IC-card 1 |
| o_sc_clk | Clock output |
| o_sc_rstin_b | Reset signal output |
| b_sc_data_b | Data exchange channel |
| i_sc_detect2_b | The signal the input whether IC-card of IC-card 2 exists |
| o_sc_vcc_en2_b | Electric control signal output on the IC-card of IC-card 2 |
IC- card interface chip 211 and 221 adopts traditional IC-card interface chip, for example TDA8004AT.Below be that example is described with TDA8004AT, certainly, those skilled in the art can also use other interface chip arbitrarily or the function of interface chip is incorporated in the IC-card controller, this is included within the scope of the present invention.
Present most of IC-card all adopts 5V voltage, so present embodiment directly is connected to the IC-card that 5V is realized supporting in " 1 " on the circuit board to the 3V/5V pin of TDA8004AT.But, as those skilled in the art is known, also can adopt the IC-card of 3V voltage, these depend on designing requirement and application scenario.
31 pairs of clock signal pins of IC-card controller of the present invention (o_sc_clk), reset signal pin (o_sc_rstin_b) and three stitch of exchanges data pin (b_sc_data_b) carry out time division multiplex, using independent two stitch respectively for each IC-card---IC-card detection signal pin (i_sc_detect1_b and i_sc_detect2_b) is controlled (in the text with IC-card power on signal pin (o_sc_vcc_en1_b and o_sc_vcc_en2_b), do not needing to distinguish under the situation of two IC-cards, the IC-card detection signal is referred to as i_sc_detect_b, the IC-card power on signal is referred to as o_sc_vcc_en_b), by the switching of software control card.At this, the most registers that keep existing IC-card controller are constant, only need to revise the logic that relates to IC-card detection signal (i_sc_detect_b) and IC-card power on signal (o_sc_vcc_en_b).Here, it should be noted that the IC-card detection signal is not is necessary.Such as known to persons skilled in the art, for example in the occasion of digital television system of charging, IC-card may always be inserted in the different grooves, the mode that system can give tacit consent to is given tacit consent to the existence of IC-card, system will do is switching and control between different IC-cards, promptly only needs to relate in the IC-card controller logic of IC-card power on signal (o_sc_vcc_en_b).
With reference to figure 5, Fig. 5 illustrates the logic diagram of the IC-card controller 31 of embodiments of the invention.IC-card controller 41 of the present invention is that with the difference of aforesaid prior art IC-card controller 21 the interior logic of register module is different.Below, the component identical with component in the prior art IC-card controller 21 is with identical reference number sign.IC-card controller 31 of the present invention comprises bus interface module (BUSInterface) 311, direct memory access module (DMA Mode) 312, clock generator (SC_CLKGenerator) 313, register module (REGs) 514, cache module (TX/RX_FIFO) 315, transceiver (Transceiver) 316, baud rate generation module (Baudrate) 317.Wherein, bus interface module 311 is connected with system bus (BUS) 32, finishes the exchanges data of IC-card controller 31 and system's (not shown); Direct memory access module 312 sends the DMA request by bus interface module 311 and system bus 32 to system under the control of register module 314, the IC-card controller 31 and the exchanges data of system are carried out under the DMA pattern; Clock generator 313 produces the needed clock of IC-card work under the control of register module 514; Cache module 315 is connected with transceiver 316 and register module 514 respectively, becomes the exchanges data path of IC-card and system; Baud rate generation module 317 produces the clock enable signal of certain baud rate and gives transceiver under the control of register module 514, the exchanges data speed that control IC-card and IC-card controller are 31; Register module 514 is control centers of entire I C card controller 31.The register module 514 in the IC-card controller 31 of the present invention and the difference of the register module 314 in the IC-card controller 21 of the prior art are: 514 pairs of clock signal pins of the register module in the IC-card controller 31 of the present invention (o_sc_clk), reset signal pin (o_sc_rstin_b) and three stitch of exchanges data pin (b_sc_data_b) carry out time division multiplex, use independent IC-card detection signal pin (i_sc_detect1_b and i_sc_detect2_b) and IC-card power on signal pin (o_sc_vcc_en1_b and o_sc_vcc_en2_b) to control respectively for each IC-card, switching by the software control card (is noted, as mentioned above, the detection signal pin not necessarily, therefore, also can only use independent power on signal pin respectively) for each IC-card.
Here for convenience's sake, register module 514 is set to comprise two registers: status register and control register (not shown) below describe two registers of the register module 514 of the embodiment of the invention:
Status register (SR register) (16):
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Describe | -- | -- | SEN | IDLE | BGT | COL2 | COL1 | sc_detect2 |
| Visit | R | R | R | R/W | R/W | R/W | R/W | R |
| Default | -- | -- | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Describe | sc_detect1 | MODE | TXMT | THRE | OE | TXPE | RXPE | FE |
| Visit | R | R | R | R | R | R | R | R |
| Default | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 |
FE: receive the state of FIFO, value is 1 o'clock, and it is empty that expression receives FIFO; Be to represent that data were arranged at 0 o'clock.
OE: receive FIFO overflow error.When reading the SR register, be reset.
RXPE: the even parity check mistake that receives the character frame.When reading the SR register, be reset.
TXPE: the even parity check mistake that sends the character frame.When reading the SR register, be reset.
THRE: send the state of FIFO, value is to represent to send FIFO for empty at 1 o'clock; Be to represent that data were arranged at 0 o'clock.
TXMT: sending the state of the shift register of FIFO and transmission, is to represent that the both was empty at 1 o'clock; Any one has data then is 0.
Sc_detect2: the state of second IC-card 222 is to represent that second IC-card 222 was in slot at 1 o'clock; Be to represent that second IC-card 222 was not in slot at 0 o'clock.Default to 0, expression not card is inserted into.
Sc_detect1: the state of first IC-card 212 is to represent that first IC-card 212 was in slot at 1 o'clock; Be to represent that first IC-card 212 was not in slot at 0 o'clock.Default to 0, expression not card is inserted into.
COL2: when second IC-card 222 is moved out of, be set to 1.When CPU writes 0, perhaps system reset the time, just can reset.
COL1: when first IC-card 212 is moved out of, be set to 1.When CPU writes 0, perhaps system reset the time, just can reset.
BGT: expression and 22 etu (elementary time unit: the mode bit of relevant counter basic time unit).The start bit of this counter on each I/O line begins counting, if counting finished before next start bit, the BGT position is set to 1.This position is used to help check card 22 etu after last character sends to block before the time not reply, and perhaps after the character of a last reception, 22 etu did not have transmission character (this does not have the gauge tap position) before the time.Can reset by writing 0, when running into the start bit, can be automatically reset at every turn.
The definition of BGT in the ISO7816 agreement: Block Guard Time (BGT) is the shortest time between the initial edge of the continuation character that sends of two equidirectionals.Therefore between last character that has received piece and first character that is transmitted piece delay should be BGT at least but less than BWT.
IDLE: the state of transmit status machine and receive status machine is that the state of representing transmit status machine and receive status machine at 1 o'clock is IDLE (idle condition), is defaulted as 0.
SEN: card switches enable bit (switch_en), is the switching that 1 expression allows software to block, and is defaulted as 0.
Control register (16):
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Describe | ？ | ？ | ？ | ？ | PSE2 | RSTIN | ？ | PSE1 |
| Visit | R | R | R | R | R/W | R/W | R | R/W |
| Default | -- | -- | -- | -- | -- | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Describe | CE | CD | CP | -- | -- | DIV | ||
| Visit | R/W | R/W | R/W | R | R | R/W | ||
| Default | 0 | 0 | 0 | -- | -- | 3’b000 | ||
PSE2: the CMDVCC of the TDA8004AT that control is connected with second IC-card 222, (port o_sc_vcc_en2).
PSE1: the CMDVCC of the TDA8004AT that control is connected with first IC-card 212, (port o_sc_vcc_en1).
RSTIN: the reset signal that outputs to TDA8004AT.
The IC-card interface chip provides clock signal sc_clk to IC-card, and system uses bit 7～bit 0 to control the generation of sc_clk, comprising:
CE: clock enable/disable position.
CD: when card is moved out of clock disable.
CP: the polarity of clock signal.
DIV: the frequency of clock signal output.
| DIV | Describe |
| 3’b000 | F/2 |
| 3’b001 | F/4 |
| 3’b010 | F/6 |
| 3’b011 | F/8 |
| 3’b100 | F/10 |
| 3’b101 | F/12 |
| 3’b110 | F/14 |
| 3’b111 | F/16 |
F is the employed system clock frequency of this module.
More than describe two registers in the register module of embodiments of the invention in detail, after having read above-mentioned explanation, can programme to register simply for a person skilled in the art, realize above-mentioned two register modules.Here programmed method is not described further.On the other hand, though the foregoing description comes the description control unit with control register and these two registers of status register, but as those skilled in the art is known, control register and status register all are the registers that is positioned at control module inside, the difference that only is logic function that they are different.Therefore, for a person skilled in the art, can not will control module be divided into status register or control register particularly, can programme to the register in the control module by the mode of programming, to realize above-mentioned functions.
With reference to figure 6, Fig. 6 example illustrates the generation circuit of the power on signal o_sc_vcc_en1_b of IC-card 212.Because the power on signal of IC-card 222 generation circuit is identical with IC-card 212, describe so produce circuit in this power on signal to IC-card 212.Two main modular are arranged here---modular converter 641 and " with " logic module 642.If the sc_detect1 position 0 of status register illustrates IC-card 212 not in slot, will pass through reverser 611 and modular converter 641 the COL1 position 1 of status register; Otherwise, if the sc_detect1 position 1 of status register illustrates IC-card 212 in slot, but can't be the COL1 position 0 of status register; The COL1 position needs systematic reset signal sys_reset or CPU to put 0 by modular converter 641.As shown in Figure 6, the o_sc_vcc_en1_b signal be by three signals of COL1, sc_detect1 and PSE1 (in the control register) through " with " logic module 642 generates.
The switching of card realizes by software control, and when needs switched, as long as SEN (switch_en) of inquiry SR register, this position was 1 just can switch.Because this position is, illustrate that sending and accepting FIFO all be sky, and transmission and receive status machine all are in the IDLE state at 1 o'clock.At this moment wait the switching block will be not can obliterated data, software just can be operated the switching that blocks by PSE1 and PSE2 position to control register then.
For the sake of clarity above-mentioned, described the configuration of status register and control register in detail, but this is very easy for a person skilled in the art, because inventive point of the present invention just is clock signal pin, reset signal pin and exchanges data pin are carried out time division multiplex, and provide electric control signal respectively, thereby utilize an IC-card controller to control a plurality of IC-cards to a plurality of IC-cards.In order to achieve this end, those skilled in the art can at random revise the register module in the IC-card controller of the prior art fully, realizes above-mentioned functions.
As mentioned above, under the situation that does not need the IC-card detection signal, those skilled in the art can revise power on signal generative circuit shown in Figure 6 and the control register in the IC-card controller in the foregoing description and the logic of status register fully, this is not need performing creative labour, is to be completely contained in this
Within the scope of invention.
In addition, only carried out illustration with two IC-cards in the foregoing description, still, those skilled in the art fully can be under the application's inspiration, by performing creative labour the application is not applied to IC-card more than three or three, this is included within the application's the scope.
Claims (6)
1. IC-card controller has:
Control module; And
Clock signal pin, reset signal pin and exchanges data pin;
It is characterized in that, this IC-card controller also has N and goes up the electric control signal pin, described control module is configured to provide a reset signal and the individual electric control signal of going up of N, this IC-card controller carries out time division multiplex to clock signal pin, reset signal pin and exchanges data pin, with N IC-card of an IC-card controller control, wherein N is the integer greater than 1.
2. IC-card controller as claimed in claim 1, it is characterized in that, the control bit of last electric control signal of control IC-card is set in the described control module,, whether the expression IC-card be present in the IC-card existence position in the IC-card slot and represent that the IC-card whether IC-card is moved out of the IC-card slot shifts out mode bit.
3. IC-card controller as claimed in claim 2 is characterized in that, described control module shifts out mode bit according to described control bit, IC-card existence position and IC-card and controls the described electric control signal of going up of output.
4. method with N IC-card of IC-card controller control, wherein N is the integer greater than 1, described IC-card controller carries out time division multiplex to reset signal pin, clock signal pin and the exchanges data pin of a described N IC-card, and the last electric control signal of a described N IC-card is controlled separately.
5. method as claimed in claim 4, it is characterized in that, described IC-card controller is provided with control module, and described method comprises: in described control module, be provided with the control IC-card on control bit, the expression IC-card of electric control signal whether be present in the IC-card whether IC-card existence position in the IC-card slot and expression IC-card be moved out of the IC-card slot and shift out mode bit.
6. method as claimed in claim 5 is characterized in that, shifts out mode bit according to described control bit, IC-card existence position and IC-card and controls the described electric control signal of going up of output.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100263510A CN100385428C (en) | 2005-06-01 | 2005-06-01 | Card controller, and method for controlling IC card |
| PCT/CN2006/000847 WO2006128348A1 (en) | 2005-06-01 | 2006-04-28 | A ic card controller and a method for controlling the ic card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100263510A CN100385428C (en) | 2005-06-01 | 2005-06-01 | Card controller, and method for controlling IC card |
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| Publication Number | Publication Date |
|---|---|
| CN1873634A true CN1873634A (en) | 2006-12-06 |
| CN100385428C CN100385428C (en) | 2008-04-30 |
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| CNB2005100263510A Expired - Fee Related CN100385428C (en) | 2005-06-01 | 2005-06-01 | Card controller, and method for controlling IC card |
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| CN (1) | CN100385428C (en) |
| WO (1) | WO2006128348A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106203574A (en) * | 2016-06-24 | 2016-12-07 | 恒宝股份有限公司 | A kind of smart card and write card mode |
| WO2017045178A1 (en) * | 2015-09-16 | 2017-03-23 | 华为技术有限公司 | Information card recognition circuit and terminal |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2356275B (en) * | 1999-11-15 | 2002-01-09 | China Hk Consultants Ltd | Mobile phone battery pack |
| FR2819111B1 (en) * | 2000-12-28 | 2003-03-07 | Thomson Csf | INTERCONNECTION MODULE FOR ELECTRICAL DEVICE HOUSING BACKGROUND |
| US7096298B2 (en) * | 2003-02-11 | 2006-08-22 | 02Micro International Limited | Reduced cardbus controller |
| TW200506733A (en) * | 2003-08-15 | 2005-02-16 | Via Tech Inc | Apparatus and method for the co-simulation of CPU and DUT modules |
-
2005
- 2005-06-01 CN CNB2005100263510A patent/CN100385428C/en not_active Expired - Fee Related
-
2006
- 2006-04-28 WO PCT/CN2006/000847 patent/WO2006128348A1/en active Application Filing
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017045178A1 (en) * | 2015-09-16 | 2017-03-23 | 华为技术有限公司 | Information card recognition circuit and terminal |
| CN106203574A (en) * | 2016-06-24 | 2016-12-07 | 恒宝股份有限公司 | A kind of smart card and write card mode |
| CN106203574B (en) * | 2016-06-24 | 2019-05-24 | 恒宝股份有限公司 | A kind of smart card and its write card mode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100385428C (en) | 2008-04-30 |
| WO2006128348A1 (en) | 2006-12-07 |
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