WO2006128348A1

WO2006128348A1 - A ic card controller and a method for controlling the ic card

Info

Publication number: WO2006128348A1
Application number: PCT/CN2006/000847
Authority: WO
Inventors: Zhenya Zhou; Yonggang Wang
Original assignee: Magima Digital Information Co., Ltd.
Priority date: 2005-06-01
Filing date: 2006-04-28
Publication date: 2006-12-07
Also published as: CN1873634A; CN100385428C

Abstract

The invention provides an IC card controller and a method for controlling N numbers of IC cards. Said IC card controller includes a control unit, a clock signal pin, a reset signal pin, and a data exchange pin. The controller also includes N numbers of control signal pins. Said control unit provides a reset signal and N numbers of control signals. The IC card controller controls the clock signal pin , the reset signal pin and the data exchange pin by time mulitiplexing, such that controlling N numbers of IC cards by one IC card controller, wherein N>1, N is integer.

Description

IC card controller and IC card control method

Technical field

The present invention relates to an IC card controller that controls the operation of one or more IC cards with one IC card controller by time division multiplexing of pins. The invention further relates to a method of controlling more than one IC card with an IC card controller.

Description of the prior art

In 1970, the Frenchman Roland Moreno placed the IC (Integrated Circuit) chip, which can be programmed, on the card for the first time, making the card more functional. At the time, in the patent application, the invention was described as follows: The card has a self-protecting memory. This gave birth to the world's first IC card.

Since the advent of the IC card, there have been many international names for it. The English names are "Smart Card", "IC Card", etc.; in Asia, especially in Hong Kong and Taiwan, they are often called "smart cards", "smart cards" and "smart cards"; in mainland China, people generally Call it "IC card" or "smart card". Below we are collectively referred to as the IC card.

Referring to Figure 1, Figure 1 is a simplified diagram of a conventional IC card 10. As shown in Fig. 1, the IC card 10 has an IC card chip 11 (hereinafter, collectively referred to as an IC card for convenience, it will be easily understood by those skilled in the art). The IC card 10 generally has eight contacts C1 to C8, and the definition of each contact is as shown in Table 1:

Table 1

Please refer to IS07816 for details of the IC card standard, which will not be described in detail here. As is known to those skilled in the art, the contacts of the IC card are not limited to eight, but depend on the particular application. For example, in the example shown in Table 1 above, the IC card 10 can omit the contacts C4 and C8 and have only 6 Contacts. Therefore, an IC card having a different number of contacts can be designed by those skilled in the art depending on the particular application.

IC cards have a wide range of applications in finance, communications, pay TV, and more. It is divided into four categories: memory card, encrypted memory card, CPU card and RF card. You can get a lot of IC cards in your daily life, such as phone IC card, bus card, SIM card in mobile phone. Cards can also be divided into contact and contactless IC cards.

The decryption of the charged digital TV is generally realized by the IC card. The program provided by one operator needs the corresponding IC card to decrypt. If there are multiple operators, the corresponding number of IC cards is required. At present, the digital TV set-top box sold on the market has only one IC card slot. To watch the programs provided by different operators, it is necessary to replace the IC card in the slot, which is troublesome, and the frequent insertion and removal will cause the IC card and the IC card. The slot is accelerated and damaged. As is known in the art, to set multiple IC card slots, the IC card controller needs to be added accordingly to control the IC card operation, but this will increase the chip area, the number of chip peripheral pins, and system resources. Occupation is not conducive to reducing the design and manufacturing cost of the chip.

Referring to FIG. 2, FIG. 2 shows two IC card controllers: an IC card controller 21 and an IC card controller 22; two IC card interface chips: an IC card interface chip 211 and an IC card interface chip 221; and two ICs. Card: A connection logic diagram of the IC card 212 and the IC card 222.

The IC card interface chips 211 and 221 can employ various IC card interface chips known in the art, for example, the TDA8004AT chip designed by Philips, and the like. Here, its main function is voltage coupling. Of course, this part of the function can also be integrated in the IC card controller and the interface chip is omitted. Here, the TDA8004AT is taken as an example for description (of course, those skilled in the art can use other existing interface chips, and the pin definitions of these interface chips are similar to the pin definition of the TDA8004AT, and will not be described here).

The pin definitions for the TDA8004AT are shown in Table 2:

Table 2

Pin name assignment

OFF Signal output of the IC card (corresponding to PRES)

CMDVCC IC card power-on control signal input

XTAL1 clock input

RSTIN reset signal input

3V/5V voltage selection control signal input I/OUC data input/output

RST reset signal output (corresponding to RST)

CLK clock output (corresponds to XTAL1)

I/O data input/output (corresponding to I/0UC)

VCC IC card power supply voltage (controlled)

GND ground

Signal input for the presence of the PRES IC card

The pin definitions of the IC card controllers 21 and 22 are as shown in Table 3 (only the pin definitions of the IC card controller 21 are listed here, and the pins of the IC card controller 22 are the same as those of the IC card controller 21):

table 3

The IC card slot (not shown) is provided with a terminal for detecting whether the card is in the slot, and sends a detection signal to the PRES pin of the IC card interface chip 211, and the IC card interface chip 211 sends the signal to the IC through the pin. The i-sc_detectlj) pin of the card controller 21 tells the IC card controller 21 whether or not the IC card 212 is inserted in the IC card slot.

The GND pin of the IC card interface chip 211 is connected to the C5 contact of the IC card 212 to provide a standard ground level for the IC card.

The 0-sc-vcc-enl-b pin of the IC card controller 21 is connected to the CM C pin of the IC card interface chip 211. When the IC card controller 21 is to operate the IC card 212, the o_sc_vcc-enl-b pin sends a power-on signal, the signal is a continuous level, and the level input from the foot enables the _IC card interface chip. The VCC pin of 211 generates the operating level of the IC card 212, and the IC card 212 is supplied with the operating voltage through the C1 contact of the IC card 212.

The b_sc_data_b pin of the IC card controller 21 passes through the I/0UC pin of the IC card interface chip 211 and The I/O pin is connected to the C7 contact of the IC card 212, and data exchange between the IC card controller 21 and the IC card 212 is realized.

The 0-sc-elk pin of the IC card controller 21 outputs the clock to the XTAL1 pin of the IC card interface chip 211, and the IC card interface chip 211 outputs the clock to the C3 contact of the IC card 212 through the CLK pin, which is the IC card 212. Provide a working clock.

The 0-sc-rstin-b pin of the IC card controller 21 is connected to the RSTIN pin of the IC card interface chip 211, and the RST pin of the IC card interface chip 211 is connected to the C2 contact of the IC card 212, and the reset signal is controlled from the IC card. The device 21 is sent to the IC card 212.

The C6 contact of the IC card 212 is the programming voltage of the IC card 212. In this application, the IC card 212 is not required to be programmed, so the contact is not used (it is emphasized here that the use of the programming contact C6 is emphasized). Methods are known to those skilled in the art).

The signal flow between the IC card controller 22, the IC card interface chip 221, and the IC card 222 is the same as that between the IC card controller 21, the IC card interface chip 211, and the IC card 212, and is therefore omitted here.

FIG. 3 shows a logic block diagram of a prior art IC card controller 21. The IC card controller 21 includes a bus interface module (BUS Interface) 311, a memory direct access module (DMA Mode) 312, a clock generator (SC_CLK Generator) 313, a register module (REGs) 314, and a cache module (TX/RX). - FIFO) 315, Transceiver 316, Baud Rate Generation Module (Baudrate) 317 ο where the bus interface module 311 is connected to the system bus (BUS) 32 to complete the IC card controller 21 and system (not shown) Data exchange; the memory direct access module 312 can send a DMA request to the system through the bus interface module 311 and the system bus 32 under the control of the register module 314, so that the data exchange between the IC card controller 21 and the system is performed in the DMA mode; The clock generator 313 generates a clock 0_sc_elk required for the IC card to operate under the control of the register module 314; the buffer module 315 is respectively connected to the transceiver 316 and the register module 314 to become a data exchange path between the IC card and the system; The rate generation module 317 generates a clock enable signal of a certain baud rate under the control of the register module 314 to the transceiver, and controls the IC card and the IC card control. Data exchange rate between 21; register module 314 is a control center of the whole _IC card controller 21, which receives an input signal I- sc- detectl- b, the control signal output outputs an IC card if the IC card o- vcc- present Enl — b and reset signal output 0 — sc__rstin — b. Summary of invention

For the chip design, the peripheral pins of the chip are very precious. In the case of the above example, adding an IC card controller will increase 6 pins, and also increase the chip area, and also occupy a bus. The register interface is not conducive to reducing chip design and manufacturing costs.

Accordingly, the present invention has been made in view of the above problems, and provides an IC card controller having: a control unit; a clock signal pin, a reset signal pin, a data exchange pin, and N power-on control signal pins; the control unit configured to provide a reset The signal and the N power-on control signals, the IC card controller time-multiplexes the clock signal pin, the reset signal pin, and the data exchange pin, and controls an N IC card by an IC card controller, where N is an integer greater than 1. .

The present invention also provides a method for controlling N IC cards by an IC card controller, wherein N is an integer greater than 1, and the IC card controller pairs reset signal pins and clock signals for the N IC cards The pin and the data exchange pin perform time division multiplexing to individually control the power-on control signals for the N IC cards.

The invention utilizes an IC card controller to operate different IC cards when needed by time division multiplexing of pins, which has the advantages of saving chip area, number of peripheral pins of the chip, and register interface of the system bus, thereby reducing the design and manufacturing cost of the chip. . Because only one IC card needs to be operated during the process of digital TV decryption, the design of the present invention does not affect the actual use. Therefore, the present invention has the advantages of saving system resources, reducing chip area, and reducing chip peripheral pins. BRIEF DESCRIPTION OF THE DRAWINGS

1 is a schematic structural view of a conventional IC card in the prior art.

2 is a connection logic diagram of two IC card controllers, two IC card interface chips, and two IC cards in the prior art.

Figure 3 is a logic block diagram of a prior art IC card controller.

4 is a diagram showing a connection logic relationship between an IC card controller and an IC card interface chip and an IC card according to an embodiment of the present invention.

Figure 5 is a logic block diagram of an IC card controller in accordance with an embodiment of the present invention.

FIG. 6 is a circuit for generating an IC card power-on signal according to an embodiment of the present invention. Detailed description of the preferred embodiment

Referring to FIG. 4, there is shown a logical relationship diagram of an IC card controller 31 connected to two IC card interface chips 211 and 221 and two IC cards 212 and 222, in accordance with an embodiment of the present invention. The IC card controller pin definitions of the embodiments of the present invention are as shown in Table 4:

The IC card interface chips 211 and 221 use a conventional IC card interface chip such as the TDA8004AT. The following describes the TDA8004AT as an example. Of course, those skilled in the art can also use other interface chips arbitrarily or combine the functions of the interface chip into the IC card controller, which are included in the scope of the present invention. - At present, most IC cards use 5V voltage. Therefore, this example connects the 3V/5V pin of the TDA8004AT directly to the "1" on the board to implement an IC card supporting 5V. However, as is known to those skilled in the art, an IC card of 3V voltage can also be used, depending on design requirements and application.

IC card controller 31 of the present invention, the clock signal pin (o_ _SC Elk a), the reset signal pins (o_sc_rstin_b) and a data exchange needle (b- sc- data- b) time multiplexing three pins, for each IC card Separate two pins, one IC card detection signal pin (i-sc-detect ljD and i-sc-detect2-b) and the IC card power-on signal pin (o_sc-vcc-enl-b and o-sc) — vcc— en2 — b ) Control (in the text, in the case where there is no need to distinguish between two IC cards, the IC card detection signals are collectively referred to as i-sc_detect-b, and the IC card power-on signals are collectively referred to as o- Sc_vcc—en_b), switched by the software control card. Here, the majority of the registers of the existing IC card controller are kept unchanged, and only the IC card detection signal (i-sc_detect-b) and the IC card power-on signal (o-sc_vcc-en) need to be modified. - b) Logic. Here, it should be noted that the IC card detection signal is not necessary. As is known to those skilled in the art, for example, in the case of a charging digital television system, the IC card may always be inserted in a different slot, and the system may default to the presence of the default IC card, and the system has to do differently. Switching and control between the IC cards, that is, only the logic involved in the IC card power-on signal ( o_sc_vcc_en_b ) in the IC card controller is required.

Referring to Figure 5, there is shown a logic block diagram of a C-Card Controller 31 of an embodiment of the present invention. The IC card controller 41 of the present invention differs from the prior art IC card controller 21 as described above in that the logic within the register module is different. Hereinafter, the same components as those of the prior art IC card controller 21 are identified by the same reference numerals. The IC card controller 31 of the present invention includes a bus interface module (BUS Interface) 311, a memory direct access module (DMA Mode) 312, a clock generator (SC-CLK Generator) 313, a register module (REGs) 514, and a cache module ( TX/RX—FIFO) 315, Transceiver 316, Baudrate 317. The bus interface module 311 is connected to the system bus (BUS) 32 to complete data exchange between the IC card controller 31 and the system (not shown); the memory direct access module 312 passes the bus interface module 311 under the control of the register module 314. And the system bus 32 sends a DMA request to the system, so that the data exchange between the IC card controller 31 and the system is performed in the DMA mode; the clock generator 313 generates the clock required for the IC card to operate under the control of the register module 514; the cache module 315 Connected to the transceiver 316 and the register module 514, respectively, to become a data exchange path between the IC card and the system; the baud rate generation module 317 generates a clock enable signal of a certain baud rate under the control of the register module 514 to the transceiver, the control IC The data exchange speed between the card and the IC card controller 31; the register module 514 is the control center of the entire IC card controller 31. The register module 514 in the IC card controller 31 of the present invention is different from the register module 314 in the IC card controller 21 of the prior art in that: the register module 514 in the IC card controller 31 of the present invention pairs the clock signal pin (0-sc-elk), reset signal pin (0-sc-rstin-b), and data exchange pin (b-sc-data-b) three pins for time division multiplexing, using separate ICs for each IC card The card detection signal pins (i-sc_detectl_b and i-sc-detect2-b) are controlled by the IC card power-on signal pins (o-sc-vcc-enl-b and o-sc-vcc-en2-b). Switching by the software control card (note that, as mentioned above, the detection signal pin is not necessary, so it is also possible to use a separate power-on signal pin for each IC card only).

Here, for convenience, register module 514 is set to contain two registers: Status Register And a control register (not shown), the following two registers of the register module 514 of the embodiment of the present invention are described:

Status register (SR register) (16 bits):

FE: Receive FIFO status. When the value is 1, it indicates that the receive FIFO is empty. When it is 0, it indicates that there is data.

0E: Receive FIFO overflow error. It is reset when the SR register is read.

RXPE: Receive even parity error for character frames. It is reset when the SR register is read.

TXPE: The even parity error of the transmitted character frame. It is reset when the SR register is read. 'THRE: The status of the transmit FIFO. A value of 1 indicates that the transmit FIFO is empty; a value of 0 indicates that there is data.

TXMT: The status of the transmit FIFO and the transmitted shift register. When 1 is set, both are empty; any one with data is 0.

Sc_detect2: The status of the second IC card 222, when 1 indicates that the second IC card 222 is in the slot; when 0, it indicates that the second IC card 222 is not in the slot. The default is 0, which means no cards are inserted.

Sc_detectl: The state of the first IC card 212, when 1 indicates that the first IC card 212 is in the slot; when 0, it indicates that the first IC card 212 is not in the slot. The default is 0, which means no cards are inserted.

C0L2 : Set to 1 when the second IC card 222 is removed. It can be reset when the CPU writes 0, or when the system is reset.

C0L1 : Set to 1 when the first IC card 212 is removed. It can be reset when the CPU writes 0, or when the system is reset.

BGT: indicates that it is associated with a 22 etu (elementary time unit) The status bit of the off counter. This counter starts counting at the start bit of each I/O line. If the count ends before the next start bit, the BGT bit is set to 1. This bit is used to help the check card not respond to the card before the last character is sent, or after the last received character, before the last etu time, no characters are transmitted (this bit has no control switch bit) . It can be reset by writing a 0 and will be automatically reset each time the start bit is encountered.

BGT is defined in the IS07816 protocol: Block protection time (BGT) is the shortest time between the start edges of consecutive characters sent in two identical directions. Therefore, the delay between the last character of a received block and the first character of a transmitted block should be at least BGT but less than BWT.

IDLE: The status of the transmit state machine and the accept state machine. When 1 is set, the status of the transmit state machine and the accept state machine are both IDLE (idle state), and the default is 0.

SEN: Card switch enable bit (switch-en), a value of 1 indicates that the software is allowed to switch the card, defaulting to 0.

Control register (16 bits):

PSE2: Controls the CMD CC of the TDA8004AT connected to the second IC card 222, (port o_sc_vcc_en2).

PSE1 : Controls the CMDVCC of the TDA8004AT connected to the first IC card 212, (port o_sc_vcc_enl).

RSTIN: Outputs a reset signal to the TDA8004AT.

The IC card interface chip provides a clock signal sc_ clk to the IC card, and the system uses bits 7 to 0 to control the generation of sc-elk, including:

CE: Clock enable/di sable bit. CD: When the card is removed from the clock, disable.

CP: The polarity of the clock signal.

DIV: The frequency of the clock signal output.

F is the system clock frequency used by this module.

The two registers in the register module of the embodiment of the present invention have been described in detail above, and it will be apparent to those skilled in the art that after reading the above description, the registers can be simply programmed to implement the two register modules. The programming method is not described in detail here. On the other hand, although the above embodiment describes the control unit in two registers, a control register and a status register, as is known to those skilled in the art, both the control register and the status register are registers located inside the control unit. The only difference is the difference in logic functions. Therefore, it is not necessary for a person skilled in the art to specifically divide the control unit into a status register or a control register, and the registers in the control unit can be programmed by programming to achieve the above functions.

Referring to FIG. 6, FIG. 6 illustrates a generation circuit of the power-on signal 0-sc-vcc-en1-b of the IC card 212. Since the power-on signal generating circuit of the IC card 222 is the same as that of the IC card 212, only the power-on signal generating circuit of the IC card 212 will be described here. There are two main modules, a conversion module 641 and an AND logic module 642. If the s _C _detectl bit of the status register is 0, indicating that the IC card 212 is not in the slot, the C0L1 bit of the status register is set by the inverter 611 and the conversion module 641; otherwise, the sc_detectl bit of the status register is 1, the IC card 212 is in the slot, but the C0L1 bit of the status register cannot be set to 0; the C0L1 bit requires the system reset signal sys-reset or the CPU is set to 0 by the conversion module 641. As can be seen from Figure 6, the 0-sc-vcc_enl-b signal is 3⁄4ϊ, The sc_detectl and PSE1 (one bit in the control register) three signals are generated by the AND logic module 642.

The card switching is implemented by software control. When the switch needs to be switched, the SEN (switch-en) bit of the SR register is queried, and the bit is 1 to switch. Because this bit is 1, it indicates that both the transmit and receive FIFOs are empty, and both the transmit and receive state machines are in the IDLE state. At this time, the card switching will not lose data, and then the software can switch the card by operating the PSE1 and PSE2 bits of the control register.

The above description of the configuration of the status register and the control register has been described in detail for the sake of clarity, but this is very easy for those skilled in the art since the invention is based on the clock signal pin, the reset signal pin and the data. The exchange pin performs time division multiplexing, and provides power-on control signals to a plurality of IC cards, thereby controlling a plurality of IC cards by using one IC card controller. In order to achieve this, those skilled in the art are fully capable of arbitrarily modifying the register modules in the IC card controller of the prior art to achieve the above functions.

As described above, those skilled in the art can completely modify the power-on signal generating circuit shown in FIG. 6 and the control register and status register in the IC card controller in the above embodiment without requiring an IC card detection signal. The logic, which does not require creative labor, is fully within the scope of the present invention.

Further, in the above embodiment, only two IC cards have been exemplified, but those skilled in the art can fully apply the present application to three or more ICs without creative labor, inspired by the present application. Cards, which are included in the scope of this application.

Claims

Rights request

1. An IC card controller with:

Control unit;

a clock signal pin, a reset signal pin, and a data exchange pin;

The IC card controller further has N power-on control signal pins, the control unit is configured to provide a reset signal and N power-on control signals, and the IC card controller pairs the clock signal pin and the reset signal pin And the data exchange pin performs time division multiplexing, and controls an N IC card with an IC card controller, where N is an integer greater than 1.

2. The IC card controller according to claim 1, wherein the control unit is provided with a control bit for controlling a power-on control signal of the IC card, and an IC indicating whether the IC card exists in the IC card slot. The card presence status bit and the IC card removal status bit indicating whether the IC card has been removed from the IC card slot.

3. The IC card controller according to claim 2, wherein the control unit controls the output of the power-on control signal according to the control bit, the IC card presence status bit, and the IC card removal status bit.

4. A method of controlling N IC cards by an IC card controller, wherein N is an integer greater than 1, and the IC card controller resets a signal pin, a clock signal pin, and a data exchange of the N IC cards. The pins perform time division multiplexing to individually control the power-on control signals of the N IC cards.

The method according to claim 4, wherein the IC card controller is provided with a control unit, and the method comprises: setting a control bit for controlling a power-on control signal of the IC card in the control unit, Indicates whether the IC card exists in the IC card slot and the IC card presence status bit and the IC card removal status bit indicating whether the IC card is removed from the IC card slot.

The method according to claim 5, wherein the outputting the power-on control signal is controlled according to the control bit, an IC card presence status bit, and an IC card removal status bit.