CN1870656A - USB time sequential adaptive device, interface and its communication method - Google Patents
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Abstract
This invention discloses a time sequence adaptive interface of USB device including an interface, a negative along register and a multiple selector set between a physical layer and a protocol layer, in which, the multiple selector is set with a first, a second input ends and an output end connected with the protocol layer, the data line or control line transmitting signals to the protocol layer by the physical layer is connected with the first input end of the selector, the negative along register is set with a clock input end, a data input end and an output end, said data input end is connected with the first input end of the multiple selector, the output end of the register is connected with the second input of the multiple selector and said register is triggered by the negative along of clock signals of the USB device, which also discloses a USB time sequence adaptive device and a method.
Description
Technical field
The present invention relates to a kind of general-purpose serial bus USB (Universal Serial Bus) technology, specifically, relate to a kind of USB time sequential adaptive device, interface and the means of communication thereof.
Background technology
General-purpose serial bus USB (Universal Serial Bus) is the universal serial bus of communicating by letter by between manufacturers such as Intel connection computer of formulating and the multiple peripheral hardware with USB interface.Usb bus can support 127 USB peripheral hardwares to be connected to computer system at most.
The USB peripheral hardware can adopt internal electric source (+5V, 500mA), but also circumscribed USB power supply.
The transmission rate of USB1.1 is up to 12Mb/s (standard speed of low speed peripheral hardware is 1.5Mb/s, and the standard speed of high-speed peripheral is 12Mb/s).Fast 40 times than USB1.0/1.1 of the speed of USB2.0 standard reach 480Mb/s.Make USB be generalized to hard disk, cable modem, information household appliance network product and other quick peripheral hardware.
In USB2.0 equipment, there is a physical layer IP who is called PHY to come special disposal analog signal and high-speed digital signal, finally serial signal at a high speed transferred to than the parallel signal of low speed (30M/60M) and export to protocol layer.
Interface between PHY and the protocol layer is called UTMI.UTMI (USB2.0 TransceiverMacrocell Interface) is that the signal characteristic at USB2.0 defines, this interface mainly is usb protocol and a signal of handling the physics bottom, can become special-purpose asic chip with the SIE Integration Design, also can be independently as the transponder chip of physical layer (PHY).
The logic of protocol layer need be used the clock by PHY output, is called usbclk (30M/60M).When the PHY dateout, protocol layer is sampled to parallel data and control signal that PHY produces with usbclk.When the protocol layer dateout, these data are to be produced by the logic of usbclk clock zone.When FPGA prototype with discrete PHY chip, the clock of PHY and protocol layer interface part and the bad control of time-delay of normal signal, the sequential relationship between clock and data-signal, the control signal becomes bad.
As shown in Figure 1, usbclk (USB CLOCK) is the clock signal of USB, signal 0 be desirable usbclk just along acquired signal, can be complementary with data-signal, under the condition of signal 0, physical layer and protocol layer can normal communications.But in some cases, signal and reset signal after sampling are unmatched, make protocol layer can not in time receive the interactivity order after receiving the reset signal.For example, when signal 1 during faster than the usbclk clock signal, signal 1 can not just be triggered along A by usbclk, and along being sampled, protocol layer can not in time be received the signal 1 through over-sampling after receiving the reset signal, cause the garble of protocol layer and PHY at B.
Summary of the invention
Technical problem solved by the invention provides a kind of time sequential adaptive interface of USB device, makes the physical layer of USB device and protocol layer also can correctly carry out communication when distortion takes place the phase relation of the clock of interface and data.
The time sequential adaptive interface of USB device, described USB device comprises physical layer and protocol layer, described time sequential adaptive interface includes the interface that is arranged between physical layer and the protocol layer, described time sequential adaptive interface also includes negative edge register and the MUX that is arranged between physical layer and the protocol layer, wherein
MUX is provided with first input end, second input and output, and described output is connected with protocol layer, and described physical layer links to each other with the first input end of MUX to data wire or the control line that protocol layer transmits signal;
Negative edge register, be provided with input end of clock, data input pin and output, described data input pin links to each other with the first input end of MUX, second input of the output of described negative edge register and described MUX is connected, this negative edge register triggers by the negative edge of USB device clock signal, be used for the input signal of its data input pin is postponed back output, when described USB device inserts computer system, MUX selects the input signal of its first input end as output end signal, when described physical layer and protocol layer communication appearance mistake, the input signal of second input of MUX selection process negative edge register is as output end signal.
Preferably, described MUX includes the control end that is used to select input signal, and described control end is controlled by protocol layer.
Preferably, described negative edge register postpones the input signal of data input pin to output to MUX after half clock cycle.
Another one technical problem solved by the invention provides a kind of USB time sequential adaptive device, makes the physical layer of USB device and protocol layer also can correctly carry out communication when distortion takes place the phase relation of the clock of interface and data.
The USB time sequential adaptive device comprises physical layer and protocol layer, and the interface between physical layer and the protocol layer, and protocol layer comprises controller, micro-control unit, it is characterized in that, be provided with negative edge register and MUX between described controller and the physical layer, wherein
MUX is provided with first input end, second input and output, and described output is connected with controller, and described physical layer links to each other with the first input end of MUX to data wire or the control line that controller transmits signal;
Negative edge register, be provided with input end of clock, data input pin and output, described data input pin links to each other with the first input end of MUX, second input of the output of described negative edge register and described MUX is connected, this negative edge register triggers by the negative edge of USB time sequential adaptive device clock signal, be used for the input signal of its data input pin is postponed back output, when described USB time sequential adaptive device inserts computer system, MUX selects the input signal of its first input end as output end signal, when described physical layer and protocol layer communication appearance mistake, the input signal of second input of MUX selection process negative edge register is as output end signal.
Preferably, described negative edge register postpones the input signal of data input pin to output to MUX after half clock cycle.
Preferably, described MUX includes the control end that is used to select input signal, and described control end is by micro-control unit controls.
Preferably, when described USB time sequential adaptive device inserts computer system, described computer system transmission reset order and interactivity order are to the USB time sequential adaptive device, at this moment, described interactivity order enters controller through the first input end of MUX, received the interactivity order if micro-control unit is received in the reset order back stipulated time via described controller, thought that then physical layer and protocol layer communication are normal, otherwise think when mistake appears in physical layer and protocol layer communication.
Preferably, when physical layer and protocol layer communication appearance mistake, micro-control unit sends order to physical layer, make the USB time sequential adaptive device under the situation of not power down, simulate the action that realization is extracted and inserted, afterwards, described computer system resends the reset order and micro-control unit is given in the interactivity order, and at this moment, second input by MUX behind the described interactivity order process negative edge register enters controller.
Preferably, the serial data line of described physical layer is connected with computer system.
Technical problem solved by the invention provides a kind of time sequential adaptive means of communication of USB device.
The time sequential adaptive means of communication of USB device comprise the steps:
(1) the USB device is inserted computer system, described computer system is enumerated the USB device that inserts, and sends reset signal and interactivity order;
(2) if protocol layer has been received the interactivity order in the stipulated time after receiving the reset order, think that then physical layer and protocol layer communication are normal, otherwise carry out following step;
(3) protocol layer sends a command to physical layer, makes physical layer realize once soft plug, and computer system is enumerated the USB device, sends reset signal and interactivity order again;
(4) the interactivity order that will send again sends to protocol layer after postponing.
Further, the reset signal described in the step (1) is not disturbed by the usbclk clock signal.
Further, step (2) is specially, and after protocol layer is received the reset order, if receive the interactivity order in official hour, then realizes the correct communication of protocol layer and physical layer; If when not receiving the interactivity order in official hour, protocol layer then issues commands to MUX, make MUX select the signal of input from negative edge register.
Further, negative edge register described in the step (5) triggers by the negative edge of USB device clock signal, will postpone from the data-signal of physical layer collection to export after half clock cycle.
When the communication of physical layer and protocol layer goes wrong, reset by state physical layer, make PC enumerate again to USB device, realized " soft plug " under the situation of not power down of USB device.Can make protocol layer adopt correct clock signal and physical layer to carry out communication by negative edge register and MUX, even make USB physical layer and protocol layer when distortion takes place the phase relation of the clock of interface and data, also can correctly carry out communication, and technical solution of the present invention can adapt to multiple sequential phase change automatically.
Description of drawings
Fig. 1 is in the prior art, PHY and the protocol layer sequential chart when distortion takes place the phase relation of interface clock and data;
Fig. 2 is the structural representation of USB time sequential adaptive device;
Fig. 3 is PHY and the sequential chart of protocol layer when distortion takes place the phase relation of interface clock and data.
Embodiment
With reference to the accompanying drawings the preferred embodiments of the present invention are described in detail.
In the preferred embodiment of the present invention, on-site programmable gate array FPGA (Field ProgrammableGate Array) is a chip, and its inside includes USB controller, MCU and some other logics.USB transceiver and described FPGA are discretes, and it also can be called as physical layer (PHY).Yet, it is pointed out that in other embodiments the USB transceiver also may be integrated in the FPGA.
On the whole, USB time sequential adaptive device provided by the invention has added the negative edge register that one-level triggers by the usbclk negative edge by the interface between protocol layer and physical layer (UTMI), the output signal of this grade negative edge register given protocol layer is inner to be used, solve between protocol layer and the physical layer problem that the miscommunication that distortion causes takes place for phase relation because of clock signal and data-signal.
With reference to shown in Figure 2, in one embodiment, described USB time sequential adaptive device (also can be called the USB device for short) can be USB device such as USB formula hard disk, USB formula MP3 or USB flash disk.Described USB time sequential adaptive device comprises physical layer (PHY) 1, negative edge register 2, MUX (MUX) 3, protocol layer, wherein, protocol layer comprises micro-control unit (Micro Control Unit, be called for short MCU) 5 and USB controller 4, USB controller 4 is used for the signal of Treated Base, micro-control unit (MCU) 5 is used to finish the usb protocol on upper strata and the function of application, is provided with firmware program (Firmware) 5 li of micro-control units (MCU).
The input end of clock of negative edge register 2 is connected with the clock signal line of physical layer (PHY) 1, its data input pin is connected to data wire or the control line that USB controller 4 transmits signal with physical layer (PHY) 1, the output of negative edge register 2 is connected with second input of MUX (MUX) 3, this negative edge register 2 is by the negative edge triggering of USB clock signal, is used for the input signal of its data input pin is postponed to export after half clock cycle.The first input end of MUX (MUX) 3 is connected with the data input pin of negative edge register 2, and output is connected with USB controller 4.By default, the input signal that this MUX (MUX) 3 will be selected its first input end is as output signal, and exports USB controller 4 to; Occur when wrong in communication, firmware program is by changing the output of MUX (MUX) 3, makes input signal that MUX (MUX) 3 selects its second inputs as output signal, and exports USB controller 4 to.
Physical layer (PHY) 1 is sent USB serial data line 6 (D+ and D-) to come serial signal and is changed into the USB controller 4 that parallel signal is passed to protocol layer.When outwards sending data, the USB controller 4 output parallel signals of protocol layer, physical layer (PHY) 1 changes into serial signal with this signal and passes on the USB serial data line 6 (D+ and D-).
When USB devices such as hard disk, cable modem or information household appliance network product insert computer, an enumeration process is arranged at first between PC and the USB device.This process is specially: PC sends the reset signal, wherein the reset signal that sends of PC is not influenced by the usbclk clock signal, the USB controller 4 of protocol layer can receive this reset signal exactly, and the firmware program (firmware) of these event notice micro-control unit (MCU) 5 inside; Subsequently, PC sends the interactivity order, and the USB controller 4 of protocol layer can receive and identify described interactivity order, and the firmware program (firmware) of these event notice micro-control unit (MCU) 5 inside; Afterwards, physical layer (PHY) 1 and protocol layer carry out correct communication.
If USB controller 4 fails to discern the interactivity order, then USB controller 4 can not notified the firmware program (firmware) of micro-control unit (MCU) 5, firmware program (firmware) is received the notice of not receiving the USB controller in time of USB standard code behind the reset signal certainly, thinks that then mistake appears in communication between physical layer 1 and the protocol layer.This situation may be since USB controller 4 because sequential former thereby cause.When miscommunication, firmware program is controlled the control end of MUX (MUX) 3 by the state that changes the status register in the micro-control unit (MCU) 5, and finally makes MUX (MUX) 3 select the input signal of its second input as output signal.Next, firmware program (firmware) sends order to physical layer (PHY) 1, after physical layer (PHY) 1 detects the order of being sent by firmware program (firmware), make the physical layer 1 of USB device do the once action of " soft plug " (Soft disconnect), be the not power down of USB device, and PC is thought that the USB device is extracted again and is inserted.PC can be enumerated once more to the USB device of this moment,, sends reset signal and interactivity order again that is.In enumerating again, the reset signal of this repeating transmission arrives the firmware program (firmware) of micro-control unit 5 by physical layer 1, USB controller 4, at this moment, because MUX 3 has been selected the input signal of its second input, negative edge register 2 postpones half clock cycle after MUX 3 outputs to USB controller 4 with the interactive command that enters for the second time.USB controller 4 is discerned through the interactive command that postpones this, if USB controller 4 is confirmed as interactive command with it, described USB controller 4 is the firmware program (firmware) of this event notice micro-control unit (MCU) 5, thereby realized interactivity order correct communication between physical layer 1 and protocol layer.
As shown in Figure 3, the usbclk clock signal is the clock signal of USB, and signal 0 is desirable usbclk sampled signal, and under the condition of signal 0, firmware program (firmware) can normally receive the signal 0 after the collection, thereby realizes normal communication.
Determine because the phase relation between usbclk clock signal and data-signal, the control signal is bad, distortion sometimes can occur.Signal 1 as shown in Figure 3 has one to have only a wide high level signal of clock cycle.This signal should result from the A edge, is sampled on the B edge.When this signal transmission delay during less than the usbclk clock signal, this signal can not be at B along being gathered at B step-down before arrive.But, the signal of gathering through negative edge trigger 22 can access triggering in the negative edge of usbclk, and can be gathered, be entered into micro-control unit 5 by MUX 3 and controller 4 then on the B edge, firmware program (firmware) can normally receive signal 1, thereby has realized normal communication.
The USB time sequential adaptive means of communication of the present invention comprise the steps:
(1) PC is enumerated first to the USB device.
After the USB device inserted PC, PC sent the reset signal that not disturbed by the usbclk clock signal.This reset signal is by the firmware program (firmware) of the USB controller 4 arrival micro-control units 5 of physical layer 1, protocol layer, and firmware picks up counting after receiving the reset signal.
PC sends interactive command, enter through the first input end of physical layer 1 these interactivity orders of collection by MUX (MUX) 3, output to USB controller 4,4 pairs of these interactivity orders that enter of USB controller are discerned, if USB controller 4 is confirmed as interactive command with it, USB controller 4 is the firmware program (firmware) of this event notice micro-control unit (MCU) 5, thereby realized that interactivity order correct communication between physical layer 1 and protocol layer handles and reply the interactivity order that this enters by firmware program (firmware).If USB controller 4 fails to discern described interactive command, then USB controller 4 can not notified the firmware program (firmware) of micro-control unit (MCU) 5, firmware does not receive the notice of USB controller in the time of receiving USB standard code behind the reset signal, then think miscommunication between physical layer 1 and the protocol layer.
When (2) between physical layer 1 and protocol layer, miscommunication occurring, carry out correction process.
When miscommunication, firmware program is controlled the control end of MUX (MUX) 3 by the state that changes the status register among the MCU, and finally makes MUX (MUX) 3 select the input signal of its second input as output signal.
Simultaneously, firmware program (firmware) sends order to physical layer (PHY) 1, after physical layer (PHY) 1 detects the order of being sent by firmware program (firmware), in a period of time (this time span is by the decision of the counter among the firmware), the state of physical layer (PHY) 1 when makeing mistakes is to extracting state, get back to the USB device and normally insert state from extracting state again, promptly physical layer (PHY) 1 is equivalent to make a simulation and extracts the action that (Soff disconnect) inserts again.By the variation of physical layer 1 state, make the USB device under the situation of not power down, realize once " soft plug " (Soffdisconnect).At this moment, PC thinks that a new USB device inserts again.
(3) PC carries out enumerating the second time to the USB device.
PC can be enumerated once more to the USB device of this moment,, sends reset signal and interactivity order again that is.In enumeration process again, the reset signal of this repeating transmission arrives the firmware program (firmware) of micro-control units 5 by physical layer 1, USB controller 4.
At this moment, because MUX 3 has been selected the input signal of its second input, so the interactive command that PC sends once more arrives negative edge register 2 through physical layer 1, negative edge register 2 postpones half clock cycle after MUX 3 outputs to USB controller 4 with this interactive command that enters for the second time, and USB controller 4 carries out recognition and verification to this through the interactive command that postpones.If USB controller 4 is confirmed as interactive command with it,, thereby realized interactivity order correct communication between physical layer 1 and protocol layer with the firmware program (firmware) of this event notice micro-control unit (MCU) 5.
Like this, when PC enumerates again, by negative edge register 2 interactive command that PC sends is postponed half period, just can make controller 4 can correctly discern the interactive command that PC sends, and, so just can finish the correct communication between physical layer and the protocol layer with its firmware program (firmware) of notifying micro-control unit 5.
Claims (13)
1, a kind of time sequential adaptive interface of USB device, described USB device comprises physical layer and protocol layer, described time sequential adaptive interface includes the interface that is arranged between physical layer and the protocol layer, it is characterized in that, described time sequential adaptive interface also includes negative edge register and the MUX that is arranged between physical layer and the protocol layer, wherein
MUX is provided with first input end, second input and output, and described output is connected with protocol layer, and described physical layer links to each other with the first input end of MUX to data wire or the control line that protocol layer transmits signal;
Negative edge register, be provided with input end of clock, data input pin and output, described data input pin links to each other with the first input end of MUX, second input of the output of described negative edge register and described MUX is connected, this negative edge register triggers by the negative edge of USB device clock signal, be used for the input signal of its data input pin is postponed back output, when described USB device inserts computer system, MUX selects the input signal of its first input end as output end signal, when described physical layer and protocol layer communication appearance mistake, the input signal of second input of MUX selection process negative edge register is as output end signal.
2, USB time sequential adaptive interface according to claim 1 is characterized in that described MUX includes the control end that is used to select input signal, and described control end is controlled by protocol layer.
3, USB time sequential adaptive interface according to claim 1 is characterized in that, described negative edge register postpones the input signal of data input pin to output to MUX after half clock cycle.
4, a kind of USB time sequential adaptive device comprises physical layer and protocol layer, and the interface between physical layer and the protocol layer, protocol layer comprises controller, micro-control unit, it is characterized in that, is provided with negative edge register and MUX between described controller and the physical layer, wherein
MUX is provided with first input end, second input and output, and described output is connected with controller, and described physical layer links to each other with the first input end of MUX to data wire or the control line that controller transmits signal;
Negative edge register, be provided with input end of clock, data input pin and output, described data input pin links to each other with the first input end of MUX, second input of the output of described negative edge register and described MUX is connected, this negative edge register triggers by the negative edge of USB time sequential adaptive device clock signal, be used for the input signal of its data input pin is postponed back output, when described USB time sequential adaptive device inserts computer system, MUX selects the input signal of its first input end as output end signal, when described physical layer and protocol layer communication appearance mistake, the input signal of second input of MUX selection process negative edge register is as output end signal.
5, USB time sequential adaptive device according to claim 4 is characterized in that, described negative edge register postpones the input signal of data input pin to output to MUX after half clock cycle.
6, USB time sequential adaptive device according to claim 4 is characterized in that, described MUX includes the control end that is used to select input signal, and described control end is by micro-control unit controls.
7, USB time sequential adaptive device according to claim 4, it is characterized in that, when described USB time sequential adaptive device inserts computer system, described computer system transmission reset order and interactivity order are to the USB time sequential adaptive device, at this moment, described interactivity order enters controller through the first input end of MUX, if receiving in the reset order back stipulated time via described controller, micro-control unit received the interactivity order, think that then physical layer and protocol layer communication are normal, otherwise think when mistake appears in physical layer and protocol layer communication.
8, USB time sequential adaptive device according to claim 7, it is characterized in that, when physical layer and protocol layer communication appearance mistake, micro-control unit sends order to physical layer, make the USB time sequential adaptive device under the situation of not power down, simulate the action that realization is extracted and inserted, afterwards, described computer system resends the reset order and micro-control unit is given in the interactivity order, at this moment, described interactivity order is through entering controller by second input of MUX behind the negative edge register.
9, USB time sequential adaptive device according to claim 4 is characterized in that, the serial data line of described physical layer is connected with computer system.
10, a kind of time sequential adaptive means of communication of USB device, described USB device comprises physical layer and protocol layer, described method comprises the steps:
(1) the USB device is inserted computer system, described computer system is enumerated the USB device that inserts, and sends reset signal and interactivity order;
(2) if protocol layer has been received the interactivity order in the stipulated time after receiving the reset order, think that then physical layer and protocol layer communication are normal, otherwise carry out following step;
(3) protocol layer sends a command to physical layer, makes physical layer realize once soft plug, and computer system is enumerated the USB device, sends reset signal and interactivity order again;
(4) the interactivity order that will send again sends to protocol layer after postponing.
11, the time sequential adaptive means of communication of USB device according to claim 10 is characterized in that, the reset signal described in the step (1) is not disturbed by the usbclk clock signal.
12, the time sequential adaptive means of communication of USB device according to claim 10, it is characterized in that step (2) is specially, after protocol layer is received the reset order, if in official hour, receive the interactivity order, then realize the correct communication of protocol layer and physical layer; If when not receiving the interactivity order in official hour, protocol layer then issues commands to MUX, make MUX select the signal of input from negative edge register.
13, the time sequential adaptive means of communication of USB device according to claim 10, it is characterized in that, negative edge register described in the step (5) triggers by the negative edge of USB device clock signal, will postpone from the data-signal of physical layer collection to export after half clock cycle.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101464849B (en) * | 2007-12-21 | 2010-09-29 | Tcl集团股份有限公司 | Mixed digital interface |
| CN103514122A (en) * | 2012-06-29 | 2014-01-15 | 中国船舶重工集团公司第七0九研究所 | USB equipment identification enhancing method in VxWorks operation system |
| CN109378024A (en) * | 2018-11-21 | 2019-02-22 | 灿芯半导体(上海)有限公司 | A kind of ONFI interface write access transmitting line of multi-mode |
-
2006
- 2006-06-15 CN CNB2006100122818A patent/CN100493100C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101464849B (en) * | 2007-12-21 | 2010-09-29 | Tcl集团股份有限公司 | Mixed digital interface |
| CN103514122A (en) * | 2012-06-29 | 2014-01-15 | 中国船舶重工集团公司第七0九研究所 | USB equipment identification enhancing method in VxWorks operation system |
| CN109378024A (en) * | 2018-11-21 | 2019-02-22 | 灿芯半导体(上海)有限公司 | A kind of ONFI interface write access transmitting line of multi-mode |
| CN109378024B (en) * | 2018-11-21 | 2023-09-05 | 灿芯半导体(上海)股份有限公司 | Multi-mode ONFI interface write channel transmitting circuit |
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