CN109378024B - Multi-mode ONFI interface write channel transmitting circuit - Google Patents
Multi-mode ONFI interface write channel transmitting circuit Download PDFInfo
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- CN109378024B CN109378024B CN201811388798.6A CN201811388798A CN109378024B CN 109378024 B CN109378024 B CN 109378024B CN 201811388798 A CN201811388798 A CN 201811388798A CN 109378024 B CN109378024 B CN 109378024B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a multi-mode ONFI interface write channel transmitting circuit, which comprises a first transmitting unit and a second transmitting unit, wherein the first transmitting unit comprises a trigger, a clock latch and a clock selector, and a D end is connected with a first input end of the clock selector and is used for transmitting multi-period high levels and multi-period low levels; the CK end is connected with the trigger and the clock latch, the EN end is connected with the input end of the trigger, the output end of the trigger is connected with the input end of the clock latch, and the output end of the clock latch is connected with the second input end of the clock selector; the second transmitting unit includes a register and a first selector; the first input end of the first selector inputs rising edge driving data; the register converts the rising edge driving data into falling edge driving data and transmits the falling edge driving data to the first input end of the second selector. The compatibility problem of different modes and different transmission frequencies is solved.
Description
Technical Field
The invention relates to the technical field of ONFI (Open NAND Flash Interface Specification) interfaces, in particular to an ONFI interface write channel transmitting circuit.
Background
In the ONFI interface write channel transmitting circuit, the time sequence difference of transmitting signals in different modes is relatively large, and the transmission frequency is from 10Mhz to 400Mhz, so that great difficulty is brought to design, and the existing product technology cannot achieve compatibility of different modes and different frequencies.
Disclosure of Invention
The invention aims to provide a multi-mode ONFI interface write channel transmitting circuit, which solves the compatibility problem of different modes and different transmission frequencies.
The technical scheme for achieving the purpose is as follows:
a multi-mode ONFI interface write channel transmitting circuit comprises a first transmitting unit and a second transmitting unit, wherein,
the first transmitting unit includes a flip-flop, a clock latch and a clock selector,
the end D is connected with the first input end of the clock selector and is used for transmitting multicycle high level and multicycle low level;
the CK end is connected with the trigger and the clock latch, the EN end is connected with the input end of the trigger, the output end of the trigger is connected with the input end of the clock latch, and the output end of the clock latch is connected with the second input end of the clock selector;
the CK end and the EN end are used for transmitting clock-like signals with the same frequency as the clock of the controller;
the second transmitting unit includes a register and a first selector;
the first input end of the first selector inputs rising edge driving data;
the register converts the rising edge driving data into falling edge driving data and transmits the falling edge driving data to the first input end of the second selector.
Preferably, the D1 terminal is connected to the first input terminal of the first selector, and is configured to transmit rising edge driving data;
the D2 end is connected with the input end of the register and is used for transmitting rising edge driving data;
the output end of the register is connected with the second input end of the first selector;
the CK' end is connected with the register and used for transmitting a clock of the controller;
the SEL' end is connected with the first selector and is used for transmitting a signal with a clock delay of 1/4 period;
the SEL terminal is connected to the clock selector.
Preferably, the CK terminal is connected to a reverse clock signal of the controller, and the D terminal, the EN terminal, and the SEL terminal generate corresponding control signals according to a protocol through the controller.
The beneficial effects of the invention are as follows: the invention enables different modes and different transmission frequencies to be compatible through effective design, and greatly expands the application range of products.
Drawings
Fig. 1 is a circuit diagram of a first transmitting unit in the present invention;
fig. 2 is a circuit diagram of a second transmitting unit in the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
The ONFI protocol interface signals are as follows: ALE (address Enable), CE_n (chip select), CLE (command Enable), DQ (data), DQS (data Enable), RE_n/W (read Enable), WE_n/CLK (write Enable/clock), WP_n (write protect), R/B_n (idle/busy), ZQ. The invention is mainly described with respect to the write channel structures of DQ, DQS, RE_n/W, WE_n/CLK, and the other signals are single signals of the whole period.
For DQS, RE_n/W, WE_n/CLK, the three signals may be multi-periodic high, multi-periodic low, and co-frequency with the controller clock, as can be seen from the protocol. Therefore, the present invention proposes an interface circuit that can be compatible with the above several signal modes.
The multi-mode ONFI interface write channel transmitting circuit comprises a first transmitting unit and a second transmitting unit. The first transmitting unit is DQS, RE_n/W and WE_n/CLK signal transmitting unit; the second transmitting unit is a DQ signal transmitting unit.
Referring to fig. 1, the first transmitting unit includes a rising edge triggered flip-flop 11, a clock latch 12, and a clock selector 13.
The D terminal is connected to a first input terminal of the clock selector 13 for transmitting multi-period high levels and multi-period low levels.
The CK terminal is connected to the flip-flop 11 and the clock latch 12, the en terminal is connected to the input terminal of the flip-flop 11, the output terminal of the flip-flop 11 is connected to the input terminal of the clock latch 12, and the output terminal of the clock latch 12 is connected to the second input terminal of the clock selector 13. The CK terminal and the EN terminal are used to control the transmission of clock-like signals of the same frequency as the controller clock. The SEL terminal is connected to a clock selector 13 for controlling the selection of both types of inputs. In fig. 1, the output Q of the clock selector 13.
As can be seen from the NV-DDR (double edge sampling ONFI interface) mode protocol, CLK (clock) is different from the trigger time of other commands by half a clock period, so the CK terminal of the first transmitting unit is connected to the reverse clock signal of the controller, and the control terminals (D terminal, EN terminal, SEL terminal) of the other transmitting units can generate corresponding control signals according to the protocol through the controller.
For DQ signals, in the modes of NV-DDR and NV-DDR2/NV-DDR3 (double sampling ONFI interface 3 modes), it is known from the protocol that DQS signal transmission transitions need to be delayed in the middle of DQ in order to guarantee better timing requirements. Since DQ and DQS are signals of the same frequency, this requires a 1/4 clock period phase difference between DQS and DQ signals at the time of transmission.
Referring to fig. 2, the second transmitting unit includes a register 21 triggered by a negative clock delay and a first selector 22.
The D1 terminal is connected to the first input terminal of the first selector 22 for transmitting rising edge driving data.
The D2 terminal is connected to the input terminal of the register 21 for transmitting rising edge driving data. An output of the register 21 is connected to a second input of the first selector 22. The register 21 converts the rising edge driving data into the falling edge driving data.
The CK' terminal is connected to the register 21 for transmitting the controller clock.
The SEL' terminal is connected to a first selector 22 for transmitting a signal with a clock delay of 1/4 cycle. The first selector 22 selects the rising edge driving data and the falling edge driving data. Thereby satisfying the timing relationship of the DQS signal and the DQ signal.
The above embodiments are provided for illustrating the present invention and not for limiting the present invention, and various changes and modifications may be made by one skilled in the relevant art without departing from the spirit and scope of the present invention, and thus all equivalent technical solutions should be defined by the claims.
Claims (3)
1. A multi-mode ONFI interface write channel transmitting circuit is characterized by comprising a first transmitting unit and a second transmitting unit, wherein,
the first transmitting unit includes a flip-flop, a clock latch and a clock selector,
the end D is connected with the first input end of the clock selector and is used for transmitting multicycle high level and multicycle low level;
the CK end is connected with the trigger and the clock latch, the EN end is connected with the input end of the trigger, the output end of the trigger is connected with the input end of the clock latch, and the output end of the clock latch is connected with the second input end of the clock selector;
the CK end and the EN end are used for transmitting clock-like signals with the same frequency as the clock of the controller;
the second transmitting unit includes a register and a first selector;
the first input end of the first selector inputs rising edge driving data;
the register converts rising edge driving data into falling edge driving data and transmits the falling edge driving data to the second input end of the first selector;
the first sending unit is a data enabling unit, a reading enabling unit, a writing enabling unit or a clock signal sending unit; the second transmitting unit is a data signal transmitting unit.
2. The multi-mode ONFI interface write channel transmit circuit of claim 1, wherein the D1 terminal is coupled to the first input terminal of the first selector for transmitting rising edge drive data;
the D2 end is connected with the input end of the register and is used for transmitting rising edge driving data;
the output end of the register is connected with the second input end of the first selector;
the CK' end is connected with the register and used for transmitting a clock of the controller;
the SEL' end is connected with the first selector and is used for transmitting a signal with a clock delay of 1/4 period;
the SEL terminal is connected to the clock selector.
3. The multi-mode ONFI interface write channel transmit circuit of claim 2,
the CK terminal is connected to the reverse clock signal of the controller, and the D terminal, the EN terminal and the SEL terminal generate corresponding control signals according to a protocol through the controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811388798.6A CN109378024B (en) | 2018-11-21 | 2018-11-21 | Multi-mode ONFI interface write channel transmitting circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811388798.6A CN109378024B (en) | 2018-11-21 | 2018-11-21 | Multi-mode ONFI interface write channel transmitting circuit |
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| Publication Number | Publication Date |
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| CN109378024A CN109378024A (en) | 2019-02-22 |
| CN109378024B true CN109378024B (en) | 2023-09-05 |
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| CN201811388798.6A Active CN109378024B (en) | 2018-11-21 | 2018-11-21 | Multi-mode ONFI interface write channel transmitting circuit |
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| CN110489363B (en) * | 2019-10-08 | 2024-03-22 | 灿芯半导体(上海)股份有限公司 | Sending circuit based on DDR write channel |
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| CN1670801A (en) * | 2004-03-18 | 2005-09-21 | 精工爱普生株式会社 | Reference voltage generation circuit, data driver, display device, and electronic instrument |
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| CN104506179A (en) * | 2014-12-25 | 2015-04-08 | 中国电子科技集团公司第二十九研究所 | Multi-channel clock distribution and signal synchronization and distribution circuit and selecting control method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8134852B2 (en) * | 2008-10-14 | 2012-03-13 | Mosaid Technologies Incorporated | Bridge device architecture for connecting discrete memory devices to a system |
| JP6290468B1 (en) * | 2017-02-06 | 2018-03-07 | ウィンボンド エレクトロニクス コーポレーション | Semiconductor memory device and data set method |
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| CN1670801A (en) * | 2004-03-18 | 2005-09-21 | 精工爱普生株式会社 | Reference voltage generation circuit, data driver, display device, and electronic instrument |
| CN1870656A (en) * | 2006-06-15 | 2006-11-29 | 北京中星微电子有限公司 | USB time sequential adaptive device, interface and its communication method |
| CN102177553A (en) * | 2008-11-04 | 2011-09-07 | 莫塞德技术公司 | A bridging device having a configurable virtual page size |
| CN102737719A (en) * | 2011-04-15 | 2012-10-17 | 三星电子株式会社 | Non-volatile memory devices, methods of operating non-volatile memory devices, and systems including the same |
| CN102611431A (en) * | 2012-03-08 | 2012-07-25 | 无锡华大国奇科技有限公司 | Register with combinational logic path |
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