CN1858596A - Chip general detector and its structure method - Google Patents
Chip general detector and its structure method Download PDFInfo
- Publication number
- CN1858596A CN1858596A CN 200610066597 CN200610066597A CN1858596A CN 1858596 A CN1858596 A CN 1858596A CN 200610066597 CN200610066597 CN 200610066597 CN 200610066597 A CN200610066597 A CN 200610066597A CN 1858596 A CN1858596 A CN 1858596A
- Authority
- CN
- China
- Prior art keywords
- interface
- test
- interface module
- general
- daughter board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
This inventioin discloses a general test device for chips including a test mother board, a test sub-board and a general interface connector, in which, the mother board is corresponding to a test platform exclusively and connected with one end of the connector, the sub-board is corresponding to a chip structure and connected with the other end of the connector, which applies a standard interface. This invention also discloses a method for structuring the general test device for chips, which designs the general interface connector in light of designed uniform interface standard and sets up associations between interface signals of the boards and the connector, which realizes that a same test sub-board platform is used in different test mother boards and a same mother board uses different sub-boards.
Description
Technical field
The present invention relates to the semiconducter device testing technology, relate in particular to a kind of chip universal test device and construction method thereof.
Background technology
In order to guarantee the quality of semi-conductor chip, reduce cost of development, initial stage of development at chip generally can be at ATE (automatic test equipment) (Automatic Test Equipment, be abbreviated as ATE, the abbreviation test machine) do test on, its general proving installation comprises as shown in Figure 1: socket (Socket) or mechanical arm (HandlerContactor) B, be used for fixing packaged chip to be tested (Device Under Test is called for short DUT) A; Component interface plate (Device Interface Board is called for short DIB) C; Test platform E.As shown in Figure 1, DUT is connected with DIB by Socket, and DIB is connected with the interface channel of test platform by spring needle (pogo pin) D again.Like this, test platform can be sent to various signals each pin of DUT by the wiring on the DIB.
Perhaps, proving installation comprises: probe (probe card) is used for connecting unpackaged chip to be tested (Wafer die), DIB and test platform.Wafer die is connected with DIB by probe, and DIB is connected with the interface channel of test platform by pogo pin again, and therefore, test platform can be sent to various signals in the brilliant unit of Wafer die by the wiring on the DIB.
Because production firm's difference of test platform, model is also inequality, has therefore caused different test platforms, and its inner hardware configuration and distribution are inequality, and corresponding interface channel is also inequality.Test platform such as the test platform of Teradyne (Teradyne) company and Agilent (Agilent) company is inequality, and also variant between J750, the Catalyst of Teradyne company itself and the Flex type test platform.Even this just requires different test platforms at the chip of same encapsulation, the Waferdie of same contact point, all must design the DIB of different special couplings.
Simultaneously, device for said function, because the difference of Wafer die contact point physical arrangement position (PadMap), or for same chip because chip signal packaging pin position (Pin Map) changes, the pin after causing the test platform resource and changing does not match; Perhaps same chip causes with the DIB plate not match fully because the difference of packing forms has diverse pin configurations as ball grid array (BGA) encapsulation and dual-in-line package (DIP); Therefore, even at same test platform, for the different or same chip pin order different also inevitable requirement designing wiring different DIBs of said function chip owing to physical dimension.
Obviously, the diversity of test platform, Chip Packaging and pin order and changeability have caused the increase of DIB complexity of developing and time and cost.In order to overcome this problem, when industry is carried out the chip engineering test at present, adopt a kind of mother and sons' plate scheme based on single test platform:
For packaged chip DUT, mother and sons' plate scheme is on Fig. 1 basis, with the Function Decomposition of DIB for to finish jointly, as shown in Figure 2 by mother and sons' plate.In fact the function of DIB is the motherboard by an a certain test platform of correspondence, the daughter board of a respective devices, and interface connector that connects motherboard and daughter board is finished jointly.The interface of daughter board and chip still is that the socket Socket by chip is connected.
Accordingly, identical with Fig. 2 at mother and sons' plate scenario-frame of Wafer die, only " chip socket " need be replaced by probe " probe ".In this case, daughter board has played the effect of probe probe card, therefore, can directly be connected with probe probe.
Because the DIB plate is substituted by mother and sons' plate scheme, daughter board is developed at device, and motherboard is developed at test platform, has increased the exploitation dirigibility.When the difference encapsulation, perhaps the chip of different pin order just only needs the different daughter board of design, and does not need to testing motherboard the change that is provided with is arranged, thereby reduce repeatability, time and the cost of exploitation when same test platform is tested.
But in single test platform mothers and sons plate technique scheme, daughter board is not single test daughter board, and promptly daughter board is that interface according to certain platform motherboard is provided with; Therefore, single test platform mothers and sons plate technique scheme still exists a defective: have only the dirigibility of daughter board exploitation and do not have the dirigibility of motherboard exploitation, even the chip kind does not change, as long as the motherboard of test platform changes, then must design by corresponding adjustment daughter board, as shown in Figure 3.
When causing motherboard to be changed, must reset and make new motherboard and pairing daughter board, just can continue to develop new test procedure after completing when the test platform replacing.So there is long and cost problem of higher of construction cycle equally.
Summary of the invention
The objective of the invention is in order to overcome the defective in the above-mentioned existing single test platform mothers and sons plate technique scheme, propose a kind of chip universal test device and construction method thereof of striding test platform, avoid when different test platforms carry out test program development, making repeatedly the DIB test board.
For achieving the above object, the invention provides a kind of chip universal test device, comprise a test motherboard and a test daughter board, also comprise a general-purpose interface connector that connects described test motherboard and described test daughter board;
Described test motherboard is corresponding with a kind of test platform uniquely, and is connected with an end of described general-purpose interface connector, is used for the signal on switching test platform passage and the general-purpose interface connector passage;
Described test daughter board is corresponding with a kind of chip structure uniquely, and be connected with the other end of described general-purpose interface connector, be used for the signal on connect chip and the general-purpose interface connector passage, described chip structure comprises the distributed architecture of chip physical arrangement and chip signal type;
Described general-purpose interface connector is for adopting the interface connector of unified interface standard, and its two ends connect described test daughter board and described test motherboard respectively.
Preferable technical scheme is, described general-purpose interface connector comprises at least one power supply interface module, at least one digital interface module and/or at least one analog interface module, described digital interface module, analog interface module and power supply interface module have the fixed position with described unified interface matches criteria, are respectively applied for the digital signal, simulating signal and the power supply signal that connect on described test daughter board and the described test motherboard passage.
Described general-purpose interface connector also can comprise at least one gauge tap interface module, described gauge tap interface module has the fixed position that is complementary with described unified interface standard, is used to connect the relay control signal of described test daughter board and described test motherboard.
Described arbitrary interface module can be respectively arranged with a plurality of interface channels.
Described arbitrary interface module can be the module that is set with priority.
A kind of construction method of chip universal test device also is provided, has it is characterized in that may further comprise the steps:
Step 3, test daughter board structure is set according to the distributed architecture of the physical arrangement of chip and chip signal type, the distributed architecture with the physical arrangement of described chip and described chip signal type is corresponding uniquely to make described test daughter board, and sets up related with described general-purpose interface connector the interface signal of described test daughter board.
Technical scheme is preferably: describedly according to predefined unified interface standard the general-purpose interface connector is set, wherein the unified interface standard is self-defining unified interface standard or is the existing universal interface standard of industry.Be specially:
According to the unified interface standard power supply interface module, digital interface module and/or analog interface module in the general-purpose interface connector are set respectively, and are that described arbitrary interface module is specified the fixed position.
Also comprise according to the unified interface standard gauge tap interface module in the general-purpose interface connector is set, and be that described gauge tap interface module is specified the fixed position.
Comprise that also according to the unified interface standard be arbitrary described power supply interface module, digital interface module, analog interface module and/or gauge tap interface module assigned priority.Then in the step 2 interface signal of described test motherboard being set up related step with described general-purpose interface connector is specially:
According to the type of described test motherboard interface signal, determine the high interface module of described general-purpose interface connector medium priority;
In the high interface module of described priority, select to the shortest interface module of described test motherboard signalling channel physical connection;
In the test motherboard, set up the interface signal of described test motherboard and the mapping relations of described interface module.
In the step 3 interface signal of described test daughter board being set up related step with described general-purpose interface connector is specially:
According to the type of described test daughter board interface signal, determine the high interface module of described general-purpose interface connector medium priority;
In the high interface module of described priority, select to the shortest interface module of described test daughter board signalling channel physical connection;
In the test daughter board, set up the interface signal of described test daughter board and the mapping relations of described interface module.
Also comprise according to the unified interface standard being that arbitrary described power supply interface module, digital interface module, analog interface module and/or gauge tap interface module are provided with a plurality of interface channels, and be that described interface channel is specified the fixed position.
As shown from the above technical solution, the present invention is provided with the test daughter board by the test motherboard is set at test platform at the chip testing content, adopts the mode of unified test motherboard and test daughter board interface, has following beneficial effect:
1, at the corresponding single test motherboard of the disposable input of different test platforms, avoided the exploitation repeatedly of test motherboard, saved the time and the cost of chip testing exploitation;
2, in the chip engineering test stage, need not consider the selection problem of tester table, reduced the chip testing development difficulty;
3, to the chip of same structure, only need to make a test daughter board and can realize compatibility all test platforms, saved the time and the cost of chip testing exploitation.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 is DIB connection diagram in the prior art of the present invention;
Fig. 2 substitutes the DIB synoptic diagram for mother and sons' plate scheme of test platform in the prior art of the present invention;
Fig. 3 is the synoptic diagram of single test platform mothers and sons plate scheme in the prior art of the present invention;
Fig. 4 is the block diagram of chip universal test device provided by the present invention;
Fig. 5 is the application synoptic diagram of chip universal test device provided by the present invention;
Fig. 6 is the synoptic diagram of general-purpose interface attachment unit interface standard in the device shown in Figure 4;
Fig. 7 is provided with synoptic diagram for the passage of general-purpose interface connector digital interface module shown in Figure 6;
Fig. 8 is provided with synoptic diagram for the passage of general-purpose interface connector analog interface module shown in Figure 6;
Fig. 9 is provided with synoptic diagram for the passage of general-purpose interface connector power supply interface module shown in Figure 6;
Figure 10 is provided with synoptic diagram for the passage of general-purpose interface connector gauge tap interface module shown in Figure 6;
Figure 11 is the synoptic diagram of the main flow process of construction method of chip universal test device provided by the present invention;
Figure 12 is the process flow diagram of the construction method embodiment of chip universal test device provided by the present invention.
Embodiment
Chip universal test device provided by the present invention is connected the cross-platform test that combination realizes various devices by the test motherboard of different test platforms and the daughter board of different components.
Referring to Fig. 4, chip universal test device provided by the present invention comprises a test motherboard 1, a test daughter board 3 and a general-purpose interface connector 2 that is connected described test motherboard 1 and test daughter board 3.
Test daughter board 3 is connected with general-purpose interface connector 2, as the web joint between chip socket/probe and the general-purpose interface connector 2, is used for the signal on connect chip and the general-purpose interface connector passage.A kind of test daughter board 3 is corresponding with a kind of chip structure uniquely, and this structure comprises the distributed architecture of chip physical arrangement and chip signal type.Such as, be all the bga chip of 256 pins, if a certain pin signal of one of them is set to the power interface signal, and another same pin is when being set to the digital interface signal, corresponding test daughter board structure is inequality; Simultaneously, all be under the identical situation of 256 pins and chip signal type distribution structure, when promptly the signal type of each pin correspondence is all identical, if one is bga chip, another one is the PIC encapsulation, and then owing to the physical arrangement difference, corresponding test daughter board structure is also inequality.Therefore, the structure of the test daughter board 3 that is connected with general-purpose interface connector 2 is not limited to a kind of, but can change.Concrete, test daughter board 3 connects with corresponding chip socket/probe, according to the needs of new unit test connect up at any time setting and making.
Test daughter board 3 is that with traditional test daughter board difference it is single test daughter board, need not to consider the structure of test platform when being provided with.Therefore in the device provided by the present invention, a test motherboard is for mating and only mate a kind of single test motherboard of test platform, a test daughter board is for mating and only mate a kind of chip structure, it uses synoptic diagram as shown in Figure 5, be connected the cross-platform test that combination realizes various devices by the test motherboard of different test platforms and the daughter board of different components, such as, " test daughter board 1 " can be by the general-purpose interface connector respectively and " test motherboard 1 ", " test motherboard 2 " and " test motherboard 3 " combination respectively, " chip 1 " can go up test at " platform 1 " or " platform 2 " or " platform 3 " freely by same " test daughter board 1 " like this.
Certainly, consider that the test daughter board of test platform architecture is equally applicable to the present invention, but owing to, therefore, be not preferable technical scheme in cost of development and the waste on the development time.
General-purpose interface connector 2 is the key components in the technical program, adopts the setting of unified interface standard, and its two ends connect described test daughter board 3 and described test motherboard 1 respectively, will test motherboard 1 and test daughter board 3 to link together.Wherein, this unified interface standard can be self-defining standard, also can adopt industry present interfaces standard, and promptly the interface that is adopted among the present invention can be self-defining interface, also can be the industry general-purpose interface.
General-purpose interface connector 2 can adopt different physics modes to realize, includes but not limited to pogo pin (a kind of spring needle), connector (a kind of contact pin that mates with slot), concentric cable etc.
Like this, use unified interface standard to carry out the setting of general-purpose interface connector 2, then at having the chip that new encapsulation specification and test index require, only relate to the exploitation of test daughter board 3, promptly can be applicable to all test platforms, to the exploitation of corresponding test motherboard 1, realized seamless transitions between different test platforms when having avoided the conversion testing platform.
Embodiment:
As shown in Figure 6, general-purpose interface connector 2 comprises 16 digital interface modules 21, respectively with " DIGxx " expression, and 2 analog interface modules 22, respectively with " ANAxx " expression, and 4 power supply interface modules 23, represent with " DPSxx " respectively.Wherein, digital interface module 21, analog interface module 22 and power supply interface module 23 have the fixed position, and this fixed position is determined by the defined unified interface standard of present embodiment.Like this, general-purpose interface connector 2 just can connect digital signal, simulating signal and the power supply signal on described test daughter board 3 and described test motherboard 1 passage respectively.
In the present embodiment, general-purpose interface connector 2 also comprises 4 gauge tap interface modules 24, with " UTIxx " expression, described gauge tap interface module 24 has the fixed position that is complementary with the unified interface standard, is used to connect the relay control signal on test daughter board 3 and test motherboard 1 passage.
In the present embodiment, also further set the use priority of each interface module, shown in numeral in Fig. 6 circle, carried out actual interface when being provided with, can carry out the standard of actual test interface with reference to priority.
Each interface module in the general-purpose interface connector 2 can also be respectively arranged with a plurality of interface channels, as Fig. 7, Fig. 8, Fig. 9 and shown in Figure 10.
Shown in Figure 7, be the access diagram of a digital interface module 21, be provided with 64 passages, wherein numeral is set for the developer, so that sign is convenient; In this figure, the dark passage that indicates, as 01,03,05,07,10,12,14,16 etc., expression connects the passage of signal; The passage that light color indicates, as 02,04,06,08,09,11,13,15 etc., the passage of expression ground connection.It will be appreciated by those skilled in the art that shown in this figure, only is an instantiation and non-limiting, and the passage of digital interface module can be set arbitrarily as required by the developer.
Shown in Figure 8, be the access diagram of an analog interface module 22, be provided with 64 passages, wherein numeral is set for the developer, so that sign is convenient; In this figure, the dark passage that indicates, as 01,03,05,07,10,12,14,16 etc., expression connects the passage of signal; The passage that light color indicates, as 02,04,06,08,09,11,13,15 etc., the passage of expression ground connection.It will be appreciated by those skilled in the art that shown in this figure, only is an instantiation and non-limiting, and the passage of digital interface module can be set arbitrarily as required by the developer.
Shown in Figure 9, be the access diagram of a power supply interface module 23, be provided with 39 passages, wherein blank parts is a through hole, reference numerals is set for the developer, so that sign is convenient; In this figure, the passage that passage 01,15,27,39 expressions are connected with the ground of analog power; The passage that indicates with another gray scale, as 09,12,18,35 etc., expression connects the passage of power supply; The passage of blank expression, as 02,03,16,28 etc., the passage that expression is connected with the ground of digital power.It will be appreciated by those skilled in the art that shown in this figure, only is an instantiation and non-limiting, and the passage of digital interface module can be set arbitrarily as required by the developer.
Shown in Figure 10, be the access diagram of a gauge tap interface module 24, be provided with 15 passages, wherein blank parts is a through hole, reference numerals is set for the developer, so that sign is convenient; In this figure, the passage of passage 01,05,10 and 11 expression ground connection; Passage 02,04 is the passage that defines voluntarily; Passage 06-09 and 12-15, expression connects the passage of signal; Passage 03 expression gauge tap interface module connects the passage of power supply; Indicate with different gray scales respectively.It will be appreciated by those skilled in the art that shown in this figure, only is an instantiation and non-limiting, and the passage of digital interface module can be set arbitrarily as required by the developer.
Be to be understood that, present embodiment is only for illustrating clear four generic modules of having described, but technical scheme provided by the present invention not only is confined to above-mentioned four generic modules, can increase or reduce module type according to the unified interface standard of developer's definition, such as can only comprising power supply interface module and analog module, be used for adaptive analog chip, also can only comprise power supply interface module and digital module, be used for adaptive digit chip, simultaneously, also can on the basis of present embodiment, increase as the radiofrequency signal interface module, big current interface module, high speed signal interface module etc.; Technical scheme provided by the present invention also not only is confined to the location expression and the path setting of above-mentioned module.
Pass through interface connector in order to further specify, the seamless transplanting that can be implemented between each different test platforms is used, now Flex platform and the catalyst platform with Teradyne company is example, describes with its parameter at the DPS1 of power supply interface module 23.
| | Flex | Catalyst | |
| 1 | 1CH2F | DUTSRC2F(1F5) | |
| 2 | DGND | DGND | |
| 3 | DGND | DGND | |
| 4 | DGND | DGND | |
| 5 | DGND | DGND | |
| 6 | DGS1 | DGS1(1E21) | |
| 7 | DGND | DGND | |
| 8 | 1CH4F | DUTSRC3F(1F9) | |
| 9 | 1CH4F | DUTSRC3F(1F10) | |
| 10 | | DGND | |
| 11 | 1CH3S | DCMATRIX1S(1F17) | |
| 12 | 1CH3F | DCMATRIX1F(1F16) | |
| 13 | 1CH3F | DCMATRIX1F(1F16) | |
| 14 | 1CH3F | DCMATRIX1F(1F16) | |
| 15 | | DGND | |
| 16 | 1CH3S | DUTSRC3S(1F11) | |
| 17 | 1CH4F | DUTSRC3F(1F9) | |
| 18 | DGS1 | DGS1(1E21) | |
| 19 | 1CH2F | DUTSRC2F(1F5) | |
| 20 | | DGND | |
| 21 | | DGND | |
| | DGND | DGND | |
| | DGND | DGND | |
| 24 | DGS1 | DGS1(1E21) | |
| 25 | | DGND | |
| 26 | 1CH4F | DUTSRC3F(1F9) | |
| 27 | 1CH4F | DUTSRC3F(1F10) | |
| 28 | | DGND | |
| 29 | 1CH3S | DCMATRIX1S(1F17) | |
| 30 | 1CH3F | DCMATRIX1F(1F16) | |
| 31 | 1CH3F | DCMATRIX1F(1F16) | |
| 32 | 1CH3F | DCMATRIX1F(1F16) |
| 33 | | DGND | |
| 34 | 1CH3S | DUTSRC3S(1F11) | |
| 35 | 1CH4F | DUTSRC3F(1F9) | |
| 36 | DGS1 | DGS1(1E21) | |
| 37 | 1CH2F | DUTSRC2F(1F5) | |
| 38 | | DGND | |
| 39 | DGND | DGND |
In last table, secondary series is the title of Flex test platform to channel definition, and the 3rd row are Catalyst test platform titles to channel definition, and these can be known from the operation file of Teradyne company.First row then are a kind of channel patterns that the present invention is provided with, and are to gather each platform information to be defined reorganization.Obviously, those skilled in the art are easy to the concrete condition according to different test platforms, and each module of unified general-purpose interface connector 2 is provided with, and realize the mutual of signal.
Wherein, the passage setting is not limited to above-mentioned pattern, and interface module also is not limited to digital interface module, analog interface module, power supply interface module and the gauge tap interface module that present embodiment occurs; Simultaneously, test platform also is not limited to above-mentioned several, and its kind can increase and decrease.
In sum, the test motherboard is at different test platforms, such as Catalyst, and Flex, the disposable input of difference, need not to develop repeatedly, saved the time and the cost of chip testing exploitation; Like this,, just need not consider the selection problem of tester table, reduce the chip testing development difficulty in the chip engineering test stage; Simultaneously,, only need to make a test daughter board and can realize compatibility, saved the time and the cost of chip testing exploitation all test platforms to same chip.
The present invention also provides a kind of construction method of chip universal test device, and referring to Figure 11, its main flow process may further comprise the steps:
Wherein, unified interface standard in the step 101 is self-defining unified interface standard or is the existing universal interface standard of industry, defined title, quantity and the position of interface module, the title of signalling channel, quantity and position in the interface module, and the interface module priority class of traffic etc.
Step 101 is specially:
According to the unified interface standard power supply interface module, digital interface module and/or analog interface module in the general-purpose interface connector are set respectively, and are that described arbitrary interface module is specified the fixed position.
Step 101 can also comprise:
According to the unified interface standard gauge tap interface module in the general-purpose interface connector is set, and is that described gauge tap interface module is specified the fixed position;
According to the unified interface standard is described arbitrary interface module assigned priority; And be that described arbitrary interface module is provided with a plurality of interface channels, and be that described interface channel is specified the fixed position according to the unified interface standard.
Embodiment:
To use the digital interface module that is provided with in the general-purpose interface connector to be example,, may further comprise the steps referring to Figure 12:
Step 201, power supply interface module, digital interface module and analog interface module and gauge tap interface module in the general-purpose interface connector are set respectively, and are that described arbitrary interface module is specified the fixed position according to the unified interface standard;
Step 202, be power supply interface module, digital interface module, analog interface module and gauge tap interface module assigned priority, in the present embodiment, the priority of digital interface modules A, B, C, D is respectively 1,2,3,4;
Step 203, for power supply interface module, digital interface module, analog interface module and gauge tap interface module are provided with a plurality of interface channels, and be described interface channel appointment fixed position; In the present embodiment, digital interface modules A, B, C, D have 64 interface channels;
Step 204, the test motherboard structure is set, makes described test motherboard corresponding with the Catalyst test platform uniquely according to the Catalyst test platform architecture;
Step 205, discern this test motherboard the signal of 128 signalling channels to be arranged be digital signal, therefore determines that according to priority available interface module is digital interface modules A and B;
Step 206, in the test motherboard, set up the one-to-one relationship of interface channel among the signal of signalling channel of test motherboard and digital interface modules A and the B; In this step, can adopt according to the shortest principle of physical connection and set up corresponding relation, the signal of promptly testing each signalling channel of motherboard all selects apart from it nearest and still untapped interface channel to set up corresponding relation, thereby improves quality of signals;
Step 207, test daughter board structure is set according to the distributed architecture of the physical form of different chips and chip signal type, in the present embodiment, be that distributed architecture according to a kind of bga chip signal type is provided with test daughter board structure, make described test daughter board distribute corresponding with the signal type of bga chip uniquely;
Step 208, discerning this test daughter board, the signal of 48 signalling channels is arranged is digital signal, determines that available interface module is the digital interface modules A;
Step 209, set up the mapping relations of interface channel in the signal of whole passages of described test daughter board and the described digital interface modules A in the daughter board in test, in this step, the signal of these 48 signalling channels can selecting 48 sets up one-to-one relationship arbitrarily in 64 interface channels of digital interface module; But in order to improve signal quality, what present embodiment adopted is to set up this corresponding relation according to the shortest principle of physical connection.
As seen, present embodiment has adopted the unified interface standard, preferentially selects the high module of priority that the interface that this test daughter board is connected with the general-purpose interface connector is set; Under the condition that guarantees priority, the shortest with physical connection is that principle is set up mapping relations.
The foregoing description only provides a kind of construction method of preferable chip universal test device, it will be appreciated by those skilled in the art that its enforcement order is not unique.
In sum, the test motherboard is only at the test platform exploitation, and the test daughter board is only at chip development, by the general-purpose interface connector, arbitrary test motherboard and arbitrary test daughter board all can be realized coupling, have saved the time and the cost of chip testing exploitation, have reduced the chip testing development difficulty.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and scope of technical solution of the present invention.
Claims (13)
1, a kind of chip universal test device comprises a test motherboard and a test daughter board, it is characterized in that also comprising a general-purpose interface connector that connects described test motherboard and described test daughter board;
Described test motherboard is corresponding with a kind of test platform uniquely, and is connected with an end of described general-purpose interface connector, is used for the signal on switching test platform passage and the general-purpose interface connector passage;
Described test daughter board is corresponding with a kind of chip structure uniquely, and be connected with the other end of described general-purpose interface connector, be used for the signal on connect chip and the general-purpose interface connector passage, described chip structure comprises the distributed architecture of chip physical arrangement and chip signal type;
Described general-purpose interface connector is for adopting the interface connector of unified interface standard, and its two ends connect described test daughter board and described test motherboard respectively.
2, device according to claim 1, it is characterized in that described general-purpose interface connector comprises at least one power supply interface module, at least one digital interface module and/or at least one analog interface module, described digital interface module, analog interface module and power supply interface module have the fixed position with described unified interface matches criteria, are respectively applied for the digital signal, simulating signal and the power supply signal that connect on described test daughter board and the described test motherboard passage.
3, device according to claim 2, it is characterized in that described general-purpose interface connector also comprises at least one gauge tap interface module, described gauge tap interface module has the fixed position that is complementary with described unified interface standard, is used to connect the relay control signal of described test daughter board and described test motherboard.
4,, it is characterized in that described arbitrary interface module is respectively arranged with a plurality of interface channels according to claim 2 or 3 described devices.
5,, it is characterized in that described arbitrary interface module is the module that is set with priority according to claim 2 or 3 described devices.
6, a kind of construction method of chip universal test device is characterized in that may further comprise the steps:
Step 1, the general-purpose interface connector is set according to the unified interface standard of setting;
Step 2, the test motherboard structure is set, makes described test motherboard corresponding with described test platform uniquely, and set up related with described general-purpose interface connector the interface signal of described test motherboard according to test platform architecture;
Step 3, test daughter board structure is set according to the distributed architecture of the physical arrangement of chip and chip signal type, the distributed architecture with the physical arrangement of described chip and described chip signal type is corresponding uniquely to make described test daughter board, and sets up related with described general-purpose interface connector the interface signal of described test daughter board.
7, method according to claim 6 is characterized in that the unified interface standard in the described step 1 is self-defining unified interface standard or is the existing universal interface standard of industry.
8, method according to claim 6 is characterized in that described step 1 is specially:
According to the unified interface standard power supply interface module, digital interface module and/or analog interface module in the general-purpose interface connector are set respectively, and are that described arbitrary interface module is specified the fixed position.
9, method according to claim 8 is characterized in that described step 1 also comprises according to the unified interface standard gauge tap interface module in the general-purpose interface connector is set, and is that described gauge tap interface module is specified the fixed position.
10, according to Claim 8 or 9 described methods, it is characterized in that described step 1 comprises that also according to the unified interface standard be described arbitrary interface module assigned priority.
11, method according to claim 10 is characterized in that in the described step 2 interface signal of described test motherboard being set up related step with described general-purpose interface connector is specially:
According to the type of described test motherboard interface signal, select the high interface module of described general-purpose interface connector medium priority;
In the high interface module of described priority, select to the shortest interface module of described test motherboard signalling channel physical connection;
In the test motherboard, set up the interface signal of described test motherboard and the mapping relations of described interface module.
12, method according to claim 10 is characterized in that in the described step 3 interface signal of described test daughter board being set up related step with described general-purpose interface connector is specially:
According to the type of described test daughter board interface signal, determine the high interface module of described general-purpose interface connector medium priority;
In the high interface module of described priority, select to the shortest interface module of described test daughter board signalling channel physical connection;
In the test daughter board, set up the interface signal of described test daughter board and the mapping relations of described interface module.
13, according to Claim 8 or 9 described methods, it is characterized in that it is that described arbitrary interface module is provided with a plurality of interface channels that described step 1 also comprises according to the unified interface standard, and be that described interface channel is specified the fixed position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100665975A CN100439923C (en) | 2006-04-03 | 2006-04-03 | Chip general detector and its structure method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100665975A CN100439923C (en) | 2006-04-03 | 2006-04-03 | Chip general detector and its structure method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1858596A true CN1858596A (en) | 2006-11-08 |
| CN100439923C CN100439923C (en) | 2008-12-03 |
Family
ID=37297520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100665975A Expired - Fee Related CN100439923C (en) | 2006-04-03 | 2006-04-03 | Chip general detector and its structure method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100439923C (en) |
Cited By (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101799506A (en) * | 2010-04-21 | 2010-08-11 | 广州市广晟微电子有限公司 | Chip test method, device and system based on script control |
| CN101430719B (en) * | 2007-11-08 | 2010-09-29 | 青岛海信电器股份有限公司 | Debugging equipment |
| CN102360064A (en) * | 2011-08-01 | 2012-02-22 | 上海宏力半导体制造有限公司 | Chip test system |
| CN101369550B (en) * | 2008-08-12 | 2012-07-11 | 中国电子科技集团公司第四十五研究所 | Gold thread break detection apparatus of full-automatic lead bonding machine |
| CN103048611A (en) * | 2013-01-21 | 2013-04-17 | 烟台正海科技有限公司 | Universal COB module testing mode |
| CN103576073A (en) * | 2012-07-30 | 2014-02-12 | 合肥科盛微电子科技有限公司 | System and method for testing functions of chips |
| CN104280639A (en) * | 2014-10-20 | 2015-01-14 | 北京空间机电研究所 | Test device and method of high-speed video bus connectors |
| CN104375076A (en) * | 2014-11-12 | 2015-02-25 | 中国人民解放军第五三一一工厂 | Circuit module measurement switching device |
| CN104914339A (en) * | 2015-06-10 | 2015-09-16 | 中国航天科技集团公司第九研究院第七七一研究所 | High-speed test system and processing method thereof for ATE machine |
| CN105301516A (en) * | 2015-09-24 | 2016-02-03 | 浪潮电子信息产业股份有限公司 | Jig and method convenient for testing BGA chip power supply |
| CN105866658A (en) * | 2016-03-29 | 2016-08-17 | 深圳市九洲电器有限公司 | Electronic product single board for testing and testing apparatus |
| CN106033093A (en) * | 2015-03-10 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | Auxiliary device for testing |
| CN106054062A (en) * | 2016-08-03 | 2016-10-26 | 胜克公司 | Head of automatic test machine and automatic test machine with head |
| CN106571166A (en) * | 2016-11-09 | 2017-04-19 | 中国空间技术研究院 | MT29F series NAND FLASH test aging system with customizable process |
| CN106708023A (en) * | 2017-01-19 | 2017-05-24 | 延锋伟世通电子科技（上海）有限公司 | Multi-platform compatibility test system and working method thereof |
| CN107664741A (en) * | 2016-07-28 | 2018-02-06 | 三星电子株式会社 | The common board of the adapter of tester, the adapter of tester and tester |
| CN108459262A (en) * | 2017-12-14 | 2018-08-28 | 天津津航计算技术研究所 | A kind of unitized SiP chip test systems and test method |
| CN108983760A (en) * | 2018-10-16 | 2018-12-11 | 昆明北方红外技术股份有限公司 | Function of the MCU and source current test device |
| CN109491854A (en) * | 2017-09-12 | 2019-03-19 | 北京遥感设备研究所 | A kind of SoC prototype verification method based on FPGA |
| CN110023770A (en) * | 2017-10-25 | 2019-07-16 | 深圳市汇顶科技股份有限公司 | For testing method, test platform and the test macro of chip |
| CN111065930A (en) * | 2017-07-09 | 2020-04-24 | 德克萨斯仪器股份有限公司 | Test fixture with sintering connection between mother board and daughter board |
| CN111083269A (en) * | 2018-10-22 | 2020-04-28 | 深圳市广和通无线股份有限公司 | Functional assembly and test fixture |
| CN111965524A (en) * | 2020-08-14 | 2020-11-20 | 上海捷策创电子科技有限公司 | Chip testing device |
| CN112071354A (en) * | 2020-07-22 | 2020-12-11 | 深圳市宏旺微电子有限公司 | Test circuit and test method for NAND Flash |
| CN112083257A (en) * | 2020-09-22 | 2020-12-15 | 中国科学院长春光学精密机械与物理研究所 | CMOS image sensor's testing arrangement |
| CN112311453A (en) * | 2019-07-24 | 2021-02-02 | 仪腾科技有限公司 | Optical communication element testing device |
| CN113484720A (en) * | 2021-06-30 | 2021-10-08 | 展讯半导体(南京)有限公司 | Chip test switching device |
| CN114062893A (en) * | 2021-10-20 | 2022-02-18 | 珠海全志科技股份有限公司 | Mass production test system and method for multimedia interface |
| CN114675168A (en) * | 2022-05-31 | 2022-06-28 | 南京宏泰半导体科技有限公司 | Calibration interface board and system of universal card slot of automatic integrated circuit test equipment |
| CN116755002A (en) * | 2023-08-14 | 2023-09-15 | 上海季丰电子股份有限公司 | Connector welding state testing method and device and electronic equipment |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3378671B2 (en) * | 1994-08-22 | 2003-02-17 | 株式会社アドバンテスト | Test head for semiconductor test equipment |
| JP3135032B2 (en) * | 1995-04-07 | 2001-02-13 | 株式会社アドバンテスト | IC device interface unit structure for IC tester handler |
| JPH1130644A (en) * | 1997-07-14 | 1999-02-02 | Advantest Corp | Connecting mechanism between test head and specimen of integrated circuit testing device |
| JPH11102756A (en) * | 1997-09-25 | 1999-04-13 | Nippon Avionics Co Ltd | Fitting device for ic socket |
| US6462570B1 (en) * | 2001-06-06 | 2002-10-08 | Sun Microsystems, Inc. | Breakout board using blind vias to eliminate stubs |
| JP2003315408A (en) * | 2002-04-18 | 2003-11-06 | Mitsubishi Electric Corp | Test board for testing semiconductor |
| KR100717479B1 (en) * | 2002-10-31 | 2007-05-14 | 주식회사 아도반테스토 | Coupling unit for test apparatus |
| CN2655252Y (en) * | 2003-08-21 | 2004-11-10 | 英业达股份有限公司 | Measuring appliance for host machine circuit board |
| CN2733363Y (en) * | 2004-09-02 | 2005-10-12 | 王云阶 | Electronic component and circuit and circuit board detecting device |
-
2006
- 2006-04-03 CN CNB2006100665975A patent/CN100439923C/en not_active Expired - Fee Related
Cited By (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101430719B (en) * | 2007-11-08 | 2010-09-29 | 青岛海信电器股份有限公司 | Debugging equipment |
| CN101369550B (en) * | 2008-08-12 | 2012-07-11 | 中国电子科技集团公司第四十五研究所 | Gold thread break detection apparatus of full-automatic lead bonding machine |
| CN101799506A (en) * | 2010-04-21 | 2010-08-11 | 广州市广晟微电子有限公司 | Chip test method, device and system based on script control |
| CN102360064A (en) * | 2011-08-01 | 2012-02-22 | 上海宏力半导体制造有限公司 | Chip test system |
| CN103576073A (en) * | 2012-07-30 | 2014-02-12 | 合肥科盛微电子科技有限公司 | System and method for testing functions of chips |
| CN103048611A (en) * | 2013-01-21 | 2013-04-17 | 烟台正海科技有限公司 | Universal COB module testing mode |
| CN104280639B (en) * | 2014-10-20 | 2017-01-11 | 北京空间机电研究所 | Test device and method of high-speed video bus connectors |
| CN104280639A (en) * | 2014-10-20 | 2015-01-14 | 北京空间机电研究所 | Test device and method of high-speed video bus connectors |
| CN104375076A (en) * | 2014-11-12 | 2015-02-25 | 中国人民解放军第五三一一工厂 | Circuit module measurement switching device |
| CN104375076B (en) * | 2014-11-12 | 2018-09-04 | 中国人民解放军第五三一一工厂 | A kind of circuit module measurement switching device |
| CN106033093A (en) * | 2015-03-10 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | Auxiliary device for testing |
| CN104914339A (en) * | 2015-06-10 | 2015-09-16 | 中国航天科技集团公司第九研究院第七七一研究所 | High-speed test system and processing method thereof for ATE machine |
| CN105301516A (en) * | 2015-09-24 | 2016-02-03 | 浪潮电子信息产业股份有限公司 | Jig and method convenient for testing BGA chip power supply |
| CN105866658A (en) * | 2016-03-29 | 2016-08-17 | 深圳市九洲电器有限公司 | Electronic product single board for testing and testing apparatus |
| CN105866658B (en) * | 2016-03-29 | 2019-02-15 | 深圳市九洲电器有限公司 | A kind of test electronics product single board and test device |
| CN107664741A (en) * | 2016-07-28 | 2018-02-06 | 三星电子株式会社 | The common board of the adapter of tester, the adapter of tester and tester |
| CN106054062A (en) * | 2016-08-03 | 2016-10-26 | 胜克公司 | Head of automatic test machine and automatic test machine with head |
| CN106571166B (en) * | 2016-11-09 | 2020-02-14 | 中国空间技术研究院 | MT29F series NAND FLASH test aging system with customizable flow |
| CN106571166A (en) * | 2016-11-09 | 2017-04-19 | 中国空间技术研究院 | MT29F series NAND FLASH test aging system with customizable process |
| CN106708023A (en) * | 2017-01-19 | 2017-05-24 | 延锋伟世通电子科技（上海）有限公司 | Multi-platform compatibility test system and working method thereof |
| CN111065930A (en) * | 2017-07-09 | 2020-04-24 | 德克萨斯仪器股份有限公司 | Test fixture with sintering connection between mother board and daughter board |
| CN109491854A (en) * | 2017-09-12 | 2019-03-19 | 北京遥感设备研究所 | A kind of SoC prototype verification method based on FPGA |
| CN109491854B (en) * | 2017-09-12 | 2022-03-22 | 北京遥感设备研究所 | SoC prototype verification method based on FPGA |
| CN110023770A (en) * | 2017-10-25 | 2019-07-16 | 深圳市汇顶科技股份有限公司 | For testing method, test platform and the test macro of chip |
| CN108459262A (en) * | 2017-12-14 | 2018-08-28 | 天津津航计算技术研究所 | A kind of unitized SiP chip test systems and test method |
| CN108983760A (en) * | 2018-10-16 | 2018-12-11 | 昆明北方红外技术股份有限公司 | Function of the MCU and source current test device |
| CN111083269A (en) * | 2018-10-22 | 2020-04-28 | 深圳市广和通无线股份有限公司 | Functional assembly and test fixture |
| CN112311453A (en) * | 2019-07-24 | 2021-02-02 | 仪腾科技有限公司 | Optical communication element testing device |
| CN112311453B (en) * | 2019-07-24 | 2022-09-13 | 仪腾科技有限公司 | Optical communication element testing device |
| CN112071354A (en) * | 2020-07-22 | 2020-12-11 | 深圳市宏旺微电子有限公司 | Test circuit and test method for NAND Flash |
| CN111965524B (en) * | 2020-08-14 | 2021-06-29 | 上海捷策创电子科技有限公司 | Chip testing device |
| CN111965524A (en) * | 2020-08-14 | 2020-11-20 | 上海捷策创电子科技有限公司 | Chip testing device |
| CN112083257A (en) * | 2020-09-22 | 2020-12-15 | 中国科学院长春光学精密机械与物理研究所 | CMOS image sensor's testing arrangement |
| CN113484720A (en) * | 2021-06-30 | 2021-10-08 | 展讯半导体(南京)有限公司 | Chip test switching device |
| CN114062893A (en) * | 2021-10-20 | 2022-02-18 | 珠海全志科技股份有限公司 | Mass production test system and method for multimedia interface |
| CN114675168A (en) * | 2022-05-31 | 2022-06-28 | 南京宏泰半导体科技有限公司 | Calibration interface board and system of universal card slot of automatic integrated circuit test equipment |
| CN116755002A (en) * | 2023-08-14 | 2023-09-15 | 上海季丰电子股份有限公司 | Connector welding state testing method and device and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100439923C (en) | 2008-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1858596A (en) | Chip general detector and its structure method | |
| CN101334448B (en) | Test platform and method for testing PC board | |
| CN101065681A (en) | Interface apparatus for semiconductor device tester | |
| CN109885434B (en) | Integrated test system and method for FPGA high-speed SerDes interface | |
| CN202494750U (en) | Testing device of integrated circuit pin open short | |
| TW201324124A (en) | USB interface test device | |
| CN101031807A (en) | Test device, configuration method, and device interface | |
| CN1248001C (en) | Low-cost configuration for monitoring and controlling parametric measurement units in automatic test equipment | |
| CN1818700A (en) | Device and method for jtag test | |
| CN204216882U (en) | A kind of test macro for the small lot batch manufacture of High Speed High Precision ADC chip | |
| CN116660719A (en) | Universal ATE interface sub-motherboard testing method based on FLEX testing system | |
| US20090108859A1 (en) | Testing circuit board | |
| CN101515019A (en) | Dynamic boundary scanning chain test method based on programmable devices | |
| CN1501250A (en) | Multiprocessor system | |
| CN1748154A (en) | Testing of integrated circuits | |
| CN100350587C (en) | Semiconductor test system | |
| CN110501633B (en) | Packaging-level chip testing device and method | |
| CN1503911A (en) | LSI inspection method and apparatus, and LSI tester | |
| KR20140078170A (en) | JTAG interface board | |
| CN1501090A (en) | Scanning device of boundary | |
| CN1118006C (en) | Voltage Measuring circuit | |
| CN1573344A (en) | Equipment for testing semiconductor integrated circuit | |
| CN101398451A (en) | Rapid detection method for testing backing board | |
| JP2008286773A (en) | Probe card and dut card provided with mixed signal processing circuit | |
| CN109765480A (en) | A kind of test device and test equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: HAISI SEMICONDUCTOR CO., LTD., SHENZHEN Free format text: FORMER OWNER: HUAWEI TECHNOLOGY CO LTD Effective date: 20120214 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20120214 Address after: 518129 Bantian HUAWEI Longgang HUAWEI electric production center, Shenzhen District, Guangdong, China Patentee after: Haisi Semiconductor Co., Ltd., Shenzhen Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: Huawei Technologies Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081203 Termination date: 20170403 |