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CN1841978B - Method and apparatus for realizing multipath signal re-timing - Google Patents

Method and apparatus for realizing multipath signal re-timing Download PDF

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CN1841978B
CN1841978B CN 200510063022 CN200510063022A CN1841978B CN 1841978 B CN1841978 B CN 1841978B CN 200510063022 CN200510063022 CN 200510063022 CN 200510063022 A CN200510063022 A CN 200510063022A CN 1841978 B CN1841978 B CN 1841978B
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clock
signal
path
speed
time
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CN1841978A (en )
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邓莉
黄浩
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大唐电信科技股份有限公司
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Abstract

The invention discloses a method for achieving multi-path signal re-timing, especially to the re-timing of multi-path E1, T1 or other low speed signal. It uses a high speed clock source to generate a high frequency clock signal as system clock; the system clock generates a plurality of time slots; each time slot comprises a plurality of system clock periods; it separately stores the sampled low speed signal data in RAM and reads the data of all the paths of a time slot, which achieves each path synchronic processing.

Description

实现多路信号再定时的方法及装置 Method and apparatus for multi-channel signal retiming

技术领域 FIELD

[0001] 本发明涉及通信领域,特别是将多路异步信号处理为多路同步信号的实现方法。 [0001] The present invention relates to communication field, in particular the multi-channel signals into multiple asynchronous implementation of synchronization signal. 背景技术 Background technique

[0002] SDH系统(同步数字通信传输系统)广泛应用于现代高速电信网、高速因特网等重要传输体制中,对光纤,微波和卫星通信技术的发展都有重大意义。 [0002] SDH system (synchronous digital communications transmission systems) are widely used in modern high-speed telecommunications network, high-speed Internet and other important transport system, there are of great significance to the development of fiber optic, microwave and satellite communication technology. 在SDH系统中,数据适配时要经过映射或指针调整,然而在这个调整过程中,会引入数据的抖动和飘移,为了避免和减少这种情况发生时对同步定时带来的影响,需要进行信号定时处理。 In the SDH system, adapted to go through the map data or a pointer adjustment, this adjustment process, however, can introduce jitter and drift data, to avoid and reduce the impact that occurs when the synchronization timing brought required Timing signal processing.

[0003] 请参阅图1,其为一SDH系统的结构示意图。 [0003] Referring to FIG. 1, which is a schematic structural diagram of an SDH system. 在本地传送网层中,SDH环大多采用多路El、T1或其它低速信号分别连接ADM (分插服用器)和CPE (客户端设备),而CPE往往用输入的数据信号提取同步定时,为了避免SDH指针调整引起的抖动对定时带来的影响, 需要进行再定时,以便获取高质量的同步信号。 The local transport network layer, SDH ring mostly multi-channel El, T1, or other low-speed signals are connected to the ADM (add-drop administration) and the CPE (customer premises equipment), the CPE often sync timing data signal extraction inputted to avoid jitter caused by pointer adjustments SDH timing brought the need for re-timing synchronization signal in order to obtain a high quality.

[0004] 目前,通常通过缓存方式来实现多路信号再定时功能,由于RAM所占资源少,广泛用于缓存处理。 [0004] At present, the multiplex signal is typically achieved by way of the buffer re-timing function, since less resources occupied RAM, cache processing is widely used. 参阅图2,为实现多路信号再定时方法的基本原理图。 Referring to Figure 2, is a multi-channel signal retiming basic principle of the method of FIG. 对每路信号采用一个双口RAM,在一个口将数据写入,在另一个口将数据读出。 For each signal using a dual-port RAM, the data is written in a port, the other port in the read data. 写入的时钟采用从输入信号中提取出来的时钟,读出时钟采用再定时时钟,数据的写入与读出都在时钟沿上进行。 The write clock using a clock extracted from the input signal, using the read clock retiming clock, the data writing and readout are performed on clock edge. 每一路信号都配以一个RAM,通过增加RAM的数量来实现多路信号的再定时功能。 Each channel signals accompanied by a RAM, to achieve the retiming function multiplex signal by increasing the number of RAM. 并且,RAM—般直接采用FPGA芯片内的Block RAM(块存储单元)。 And, RAM- like directly from Block RAM (memory cell block) within the FPGA chip.

[0005] 上述实现多路信号再定时的方法存在以下缺陷: [0005] The method described above has the following defects multi-channel signal retiming:

[0006] 第一.片内的时钟资源是有限的,对大多数可编程器件而言,时钟只能在系统资源允许范围内使用,当信号路数增加时,如果直接用信号时钟处理数据的话,往往会因时钟资源不够导致设计无法完成。 [0006] The first clock resources within the chip is limited, for most programmable device, the clock can only be used within the scope of the system resources allow, when the signal is increased large ones, if the clock signal is directly processed data words , often due to insufficient resources led to the design clock can not be completed.

[0007] 第二:每种诸如FPGA的可编程芯片的Block RAM的数量是有限的。 [0007] Second: the number of each such Block RAM programmable FPGA chip is limited. 随着需要定时的信号路数量的增多,相应的需要Block RAM的片数就增加。 As the number of signal paths required timing, corresponding to the number of sheets Block RAM required increases. 然而,随着FPGA拥有的资源越多(比如,拥有的Block RAM片数增多),FPGA芯片的价格就越高。 However, with the FPGA has more resources (for example, RAM chip has increased the number of Block), FPGA chip, the higher the price. 即,随着网络的发展, 需要再定时的信号路数量增加,这就需要采用价格高的FPGA,由此导致成本高的缺陷。 That is, with the development of the network, it is necessary to increase the number of the timing signal path, which requires high cost the FPGA, thereby resulting in a high cost of defects.

[0008] 第三:一个Block RAM只存储一路信号,而每路信号是串行输入的,信号的位宽只有一位,因此一片BlockRAM只使用了Ibit (位)的宽度。 [0008] Third: a Block RAM stores only one signal, and each signal is serially inputted, only one bit width signal, and therefore only one BlockRAM Ibit width (bits). 请参阅图3,其为Block RAM的存储原理图。 See Figure 3, which is a schematic diagram Block RAM of memory. 每个Block RAM的存储单元都是由确定位数的宽度和确定位数的深度组成。 Block RAM of each memory cell is determined by the depth and width determined number of bits consisting of bits. 很显然,一片BlockRAM只使用了Ibit(位)的宽度,造成大量的资源浪费。 Obviously, only the width of a BlockRAM Ibit (position), resulting in a lot of waste of resources. 并且,多路信号再定时时需要和路数相应的BlockRAM片数,由此造成更大的资源浪费。 And requires large ones and the corresponding number of sheet BlockRAM retiming when multiple signals, thereby resulting in a greater waste of resources.

发明内容 SUMMARY

[0009] 本发明的目的在于提供一种实现多路信号再定时的方法及装置,以解决现有技术中存在实现再定时的成本高且资源浪费严重的技术问题。 [0009] The object of the present invention is to provide a method and apparatus for a multi-channel signal retiming implemented to address the high cost of the prior art and to achieve retiming waste of resources serious technical problems.

[0010] 为解决上述问题,本发明公开了一种实现多路信号再定时的方法,包括:[0011] (1)锁存每一路的数据,并产生每一路的写地址和公共的读地址; [0010] In order to solve the above problems, the present invention discloses a method for realizing multi-channel signal retiming, comprising: a data latch for each channel [0011] (1), and generates a write address for each channel and a common read address ;

[0012] (2)由系统时钟产生若干时隙,所述时隙分为用于将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙; [0012] (2) a plurality of slots generated by the system clock, reading the time slot is divided into time slots for each serial data channel time slots and written into the RAM write all the data read out in parallel paths;

[0013] (3)在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中; [0013] (3) at each slot arrives writing, the write data slots corresponding to the latched write channel RAM (random access memory);

[0014] (4)在读时隙到来时,将所有路的数据并行读出。 [0014] (4) in the read slot arrives, all the data read out in parallel paths.

[0015] 步骤⑴之前还包括: [0015] Step before ⑴ further comprising:

[0016] 将所述系统时钟的频率设置为大于MX低速信号频率X (路数+1),M为RAM读数据、改写数据、写入数据所需周期数之和; [0016] The system clock frequency is set to be greater than MX low frequency signal X (large ones +1), M is a data RAM read, the data is rewritten, the number of cycles required and write data;

[0017] 将RAM的宽度设置为N个低速信号的路数。 [0017] The width of the RAM is set to the large ones of the N low-speed signal.

[0018] 步骤(3)将所述写时隙对应路锁存的数据写入RAM中,具体为: [0018] Step (3) time slot corresponding to the write data written into the RAM latch passage in particular:

[0019] 先读出该路写地址对应的RAM存储单元中的数据,再将该路锁存的数据置入该路对应BIT特位,并将其他路的BIT位数据原样存回,一起写入该路写地址对应的RAM存储单元中。 [0019] reads the first path data RAM write address corresponding to the memory cell, and then the data latched into the path corresponding to the path Laid bit BIT and BIT data bit stored back other paths as, together with the write the passage into the RAM write address corresponding to the memory cell.

[0020] 步骤(¾将所述写时隙对应路锁存的数据写入RAM中具体为:先将该路锁存的数据写入RAM中该路写地址对应的存储单元,然后修改该路的写地址。所述修改该路的写地址包括将写地址加一或加X,所述X为缓存器深度一半。 Data [0020] Step (¾ time slot corresponding to the write RAM is written in the latch channel specifically is: the first RAM write data latch passage in the path memory cell corresponding to the write address, and then modify the path a write address of said write address modifying the path comprises a write address plus a plus or X, X is the half of the depth buffer.

[0021] 步骤(4)具体为:在读时隙到来时,读取读地址对应的存储单元的N个数据,然后修改所述读地址,所述N为信号路数,所述修改读地址包括将读地址加一。 [0021] Step (4) is specifically: When reading slot arrives, reading N data memory cells corresponding to the read address, the read address and then modify the signal N is large ones, the read address modifying comprises the read address plus one.

[0022] 本发明还公开了一种实现多路信号再定时的装置,包括:包含RAM(随机存储器) 的可编程逻辑器件和高频时钟源,其中: [0022] The present invention also discloses an apparatus for retiming multi-channel signal, comprising: a programmable logic device and a high frequency clock source comprises a RAM (random access memory), wherein:

[0023] 高频时钟源:连接可编程逻辑器件,用以给RAM提供系统时钟; [0023] The high frequency clock source: connecting a programmable logic device, for providing a system clock to the RAM;

[0024] 可编程逻辑器件:接收每一路输入信号及每一路对应的输入时钟和系统时钟,用以在每个系统时钟周期内将每路数据串行写入RAM,以及每路数据在统一的时钟控制下并行输出。 [0024] Programmable logic device: receiving input signals and each corresponding to each input channel clock and the system clock for each system clock cycle in each channel serial write data RAM, and data for each channel in a unified parallel output control clock.

[0025] 所述RAM的宽度等于低速信号路数,所述深度可根据系统允许最大、最小缓存时间选取,所述RAM的深度为10MBIT、768BIT、512BIT和256BIT中的其中之一。 The [0025] low-speed signal is equal to the width of the RAM is large ones, the system according to the maximum allowable depth, the minimum buffer time selected, the depth of the RAM is 10Mbit, one 768BIT, 512BIT and in 256BIT.

[0026] 所述可编程逻辑器件进一步包括:RAM、时隙分配单元、锁存单元和控制子单元,其中: [0026] The programmable logic device further comprising: the RAM, the time slot allocation unit, a latch unit and a control sub-unit, wherein:

[0027] 时隙分配单元:由系统时钟产生若干时隙,所述时隙又分为用于将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙,并且每个写时钟和读时钟都会触发时隙分配; When several time slots generated by the system clock, reading the time slot is divided into data for each channel serial write RAM and write data to all the time slots of the channel parallel readout of: [0027] The time slot allocating unit gap, and each of the write clock and the read clock will trigger slot allocation;

[0028] 锁存单元:锁存每一路的数据; [0028] The latch unit: a latch for each data path;

[0029] 控制子单元:在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中;在读时隙到来时,所有路的数据并行读出。 [0029] The control sub-unit: slot arrives at each writing, the write data slots corresponding to the latched write channel RAM (Random Access Memory); and in reading slot arrives, the data read out in parallel all the way .

[0030] 与现有技术相比,本发明具有以下优点: [0030] Compared with the prior art, the present invention has the following advantages:

[0031] 首先,本发明采用时分电路的原理在一个系统时钟周期内完成串行写入所有路的数据并且并行读出所有路的数据,只用一个时钟资源即可以实现多路数据同步处理的功能。 [0031] First, the present invention uses the principle of time division circuits is completed for all the serial write data path and the data read out in parallel all the way in one system clock cycle, i.e., only one clock can achieve multiple resource data synchronization process Features. [0032] 其次,本发明只需占用一个RAM资源即可完成多路信号处理,由此避免采用资源数多的可编程逻辑器件,进而降低成本,同时,也避免了大量存储空间的浪费,即提高了资源的利用率; [0032] Next, the present invention occupies only a RAM resources to complete the multi-channel signal processing, thereby avoiding the number of resources using multiple programmable logic devices, thus reducing costs, while also avoiding the waste of a lot of storage space, i.e., improve the utilization of resources;

[0033] 其次,本发明采用每一路都有一个单独的存储地址,所有路共用一个读地址(从而保证所有路信号同步输出),在某路信号发生读写冲突时,可以采用读地址不变,该写地址发生跳变的设计,由此保证任何一路的滑码不会影响到其它路。 [0033] Next, the present invention employs each channel has a separate memory address, all share a read address path (in order to ensure that all outputs synchronization signals), when a channel signal read conflict, the read address can be used unchanged hopping design, the write address occurs, thereby ensuring any slip all the way to the code will not affect the other way.

附图说明 BRIEF DESCRIPTION

[0034] 图1为一SDH系统的结构示意图; [0034] FIG. 1 is a schematic structural diagram of an SDH system;

[0035] 图2为实现多路信号再定时方法的基本原理图; [0035] FIG. 2 is a multi-channel signal retiming basic diagram of a method;

[0036] 图3为Block RAM的存储原理图; [0036] FIG. 3 is a schematic diagram of Block RAM memory;

[0037] 图4为一种实现多路信号再定时的装置的结构示意图; [0037] FIG. 4 is an apparatus for retiming the multiplexed signals to achieve structural diagram;

[0038] 图5为本发明实现多路信号再定时的流程图; [0038] FIG 5 is a flowchart multiplex signal retiming of realization of the present invention;

[0039] 图6为本实施例所采用的RAM的存储原理图。 [0039] FIG. 6 is a schematic diagram of the RAM storage used in Example embodiment.

具体实施方式 detailed description

[0040] 现有技术中,实现多路信号再定时的方法存在成本高且资源浪费严重的技术问题。 [0040] In the prior art, multi-channel signals are then high cost and waste of resources serious technical problems timing method. 为此,本发明的申请人经过长期的研究发现,可以利用时分电路的原理来实现多路信号再定时功能。 For this reason, the present applicant found that after long-term studies, the principle of time division circuit may be utilized to implement the multiplex signal retiming function. 其核心在于:利用一个高速时钟源产生一个高频率(其频率高于MX信号频率X (路数+1),M为RAM读数据、改写数据、写入数据所需周期数之和;信号频率为需要定时的低速信号的信号频率)的时钟信号作为系统时钟,由系统时钟产生若干时隙,每个时隙包含若干个系统时钟周期,在不同的时隙内将预先采样到的每一路低速信号数据(一个比特)分别存入RAM中,并在某一时隙将所有路的数据(每路的一个比特)并行读出,由此实现了各路同步处理的功能。 The core is: the number of cycles required to use a high speed clock source and generates a high frequency (a frequency above the signal frequency MX X (large ones +1), M is a RAM read data, rewriting the data, the write data; signal frequency each channel is required timing signal frequency low-speed signal) of the clock signal as the system clock, the system clock generated by a plurality of time slots, each time slot contains a number of system clock cycles, in different time slots previously sampled low signal data (one bit) are stored in the RAM, and a time slot for all channel data (one bit per channel) read out in parallel, thereby realizing the functions of the brightest synchronization process. 在本发明中,可以将RAM的宽度设置为N,即低速信号的路数, 这样,RAM的每一行中保存的是N个低速信号每个周期内写入的数据(一个比特),而RAM 的每一列则为某路低速信号顺序写入的的信号序列;读出RAM中一行的数据即为并行读出N路低速信号的一比特数据,从而实现了多路异步信号的同步处理。 In the present invention, the width of the RAM may be provided as N, i.e., the large ones of low-speed signal, so that each row stored in the RAM data written in the N low-speed signals for each cycle (one bit), and the RAM each column signal sequence was a low-speed signal is sequentially written; row readout of the data in RAM is the one-bit data read out in parallel N ways of low speed signals, thereby realizing sync multiplexing asynchronous signals.

[0041] 以下结合附图,具体说明本发明。 [0041] in conjunction with the following drawings, detailed description of the present invention.

[0042] 请参阅图4,其为一种实现多路信号再定时的装置的结构示意图。 [0042] Please refer to FIG. 4, a schematic structural diagram which retiming device into a multiplex signal achieved. 包括:包含RAM(随机存储器)13的可编程逻辑器件11和高频时钟源12,其中: Comprising: a RAM (random access memory) 13, a programmable logic device 11 and the high frequency clock source 12, wherein:

[0043] 高频时钟源12 :连接可编程逻辑器件11,用以给RAM13提供系统时钟。 [0043] The high frequency clock source 12: connecting a programmable logic device 11 to provide the system clock to RAM13. 高频时钟源12可以为一晶体振荡器,也可以是其他能够产生满足要求的时钟信号产生器。 High-frequency clock source 12 may be a crystal oscillator, it may be capable of producing other to meet the requirements of the clock signal generator.

[0044] 可编程逻辑器件11 :接收每一路输入信号及每一路对应的输入时钟和系统时钟, 用以在每个系统时钟周期内将每路数据串行写入RAM,以及每路数据在统一的时钟控制下并行输出。 [0044] Programmable logic device 11: receiving input signals and each corresponding to each input channel clock and the system clock for each system clock cycle in each channel serial write data RAM, and data for each channel in the unified parallel output of the clocked.

[0045] 还是请参阅图3,其为RAM的原理示意图。 [0045] See also FIG. 3, which is a schematic view of the principle of the RAM. 时隙分配的数量要大于或等于路数加一,RAM宽度等于路数即可。 Number of time slots allocated to be equal to or greater than large ones plus one, RAM width equal to large ones.

[0046] 所述可编程逻辑器件可以采用FPGA、CPLD等逻辑器件。 The [0046] Programmable logic devices may be employed FPGA, CPLD and other logic devices. 这些可编程逻辑器件进一步包括:RAM(若是采用CPLD,则需要片外存储器,可以是FIFO或其它缓存器,因为CPLD内部没有RAM)、时隙分配单元、锁存单元和控制子单元,其中: The programmable logic device further comprising: the RAM (CPLD if employed, is required chip memory may be a FIFO or other buffer, since no internal CPLD RAM), the time slot allocation unit, a latch unit and a control sub-unit, wherein:

[0047] 时隙分配单元:用于将系统时钟产生若干时隙,所述时隙包含将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙,其中读时隙只有一个。 [0047] The time slot allocation unit: generates the system clock for several time slots, said time slots each channel comprising serial write data RAM read and write time slots of time slot data channel parallel readout of all of wherein only a read time slot. 比如,需要进行再定时的信号路的总路数为8,则可以产生9个时隙:8个写时隙和1个读时隙。 For example, the need for retiming the signal path a total of 8 large ones, can be generated slots 9: 8 and a read-write time slots time slots. 本发明采用的时隙分配是动态的,由于各路信号来的先后顺序不确定,哪路先来就先给哪路分配时隙,读时隙最后分配。 The present invention uses time slot allocation is dynamic, because the sequence of signals from various quarters to uncertainty, which way to allocate time slots which will give way first, reading the last allocated time slots.

[0048] 在本发明中,当采样到每个信号时钟沿时,将数据锁存,同时时隙分配单元就为该路分配一写时隙。 [0048] In the present invention, when the sampling signal to each clock edge, latches the data, while the time slot allocation unit allocates a time slot for a write channel. 当有多路信号时钟沿同时来临,可按预定的优先级依次分配。 When multiple signals simultaneously coming clock edge, can be assigned a predetermined priority order.

[0049] 锁存单元:锁存每一路的数据。 [0049] The latch unit: a data latch for each channel. 根据每一路的输入时钟信号锁存该路的数据(一个比特)。 The data input clock signal of the latch of the passage of each channel (one bit). 锁存单元可以采用寄存器。 Latch register unit may be employed.

[0050] 控制子单元:根据时隙分配单元确定的时隙,在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中;在读时隙到来时,将所有路的数据并行读出。 [0050] The control sub-unit: The time slot allocation unit determined time slot, at each arrival of a write time slot, the time slot corresponding to said write data path to write the latched RAM (Random Access Memory); and a read slot upon arrival, the data read out in parallel all the way.

[0051] 基于上述的装置,具体说明本发明的实现多路信号再定时的方法。 [0051] Based on the above apparatus, the method specifically described multiplex signal retiming of realization of the present invention. 请参阅图5,其为本发明实现多路信号再定时的流程图。 Refer to FIG. 5, a flow chart of the multiplex signal which retiming of the present invention is implemented. 它包括: it includes:

[0052] SllO :锁存每一路的数据,并产生每一路的写地址和公共的读地址; [0052] SllO: latch data of each channel, and generates a write address for each channel and a common read address;

[0053] S120:由系统时钟产生若干时隙,所述时隙分为用于将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙; [0053] S120: generating a plurality of time slots by a system clock, reading the time slot is divided into time slots for each serial data channel time slots and written into the RAM write all the data read out in parallel paths;

[0054] S130 :在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中; [0054] S130: When writing each incoming time slot, the time slot corresponding to the write data latched write channel RAM (Random Access Memory);

[0055] S140 :在读时隙到来时,将所有路的数据并行读出 [0055] S140: When the arrival of the read time slot, the parallel read data path for all the

[0056] 在上述方法中,每一路输入信号在寄存器中锁存由系统时钟将每路锁存的一比特数据写入RAM中,并且将所有路的数据并行从RAM中读出,实现各路同步的功能。 [0056] In the above process, each input signal is latched by the system clock in a register by placing each latched one bit of data is written to the RAM, and the data read out in parallel for all the paths from the RAM, to achieve the brightest synchronization function.

[0057] 以下是例子来具体说明多路信号再定时的流程。 [0057] The following are specific examples illustrate the process of the multiplex signal retiming.

[0058] 需要进行再定时的信号路的总路数为8,其路数编号分别为1、2、3. . . 8,系统产生9个时隙,并且将序号为1-8的时隙分配给写时隙分别对应1-8路输入信号,序号为9的时隙为读时隙,系统时钟检测到各时钟沿变化时动态分配相应时隙序号。 [0058] The need for retiming the signal path of a total of 8 large ones, large ones are numbered 1, 2,... 8, the system generates nine slots, and the number of time slots 1-8 assigned time slots respectively corresponding to the write signal input 1-8, dynamically allocated slot number corresponding to the read time slot when the system clock to clock edges detected change in number is the slot 9.

[0059] 在本实施中所采用RAM的宽度为Sbit (请参阅图7)。 [0059] In the present embodiment the width of the RAM used sbit (see FIG. 7). 每一列是一路的信号数据。 Each column is the data all the way. 第一列是第一路数据,第二列是第二路数据...以此类推。 The first column is the first data channel, the second column is the path of the second data ... and so on.

[0060] 一个写时隙到来时,需要将该时隙对应路锁存的数据写入RAM中。 When [0060] the arrival of a write time slot, the time slot corresponding to the required channel data latched in the write RAM.

[0061] 当写时隙发生变化时,只需将该路锁存的数据写入该路写地址对应的RAM存储单元中。 [0061] When a write time slots is changed, only the way data is written into the latch passage of the write RAM address corresponding to the memory cell. 在每路信号时钟沿变化时修改该路写地址:通常是将该写地址+1。 Modifying the write address channel signals at each clock edge change: the write address is usually +1. 当该写地址接近或远离读地址时可以将该写地址重新设置新地址。 When the write address read address can be close to or away from the write address reset new address.

[0062] 当进行写操作时,可以采用以下步骤,将该写时隙对应路锁存的数据写入RAM中: [0062] When a write operation, the following steps may be employed, the time slot corresponding to the write data written to the RAM latch passage in which:

[0063] 先读出RAM中该路写地址对应的数据,再将所述数据存入RAM中该路写地址对应的存储单元中的相应BIT位。 [0063] The first read out the RAM write address corresponding to the data path, then the data stored in the RAM to write corresponding path bit BIT memory cell corresponding to the address. 当该路信号时钟沿变化时修改该路的写地址:通常是将该写地址+1。 Modify the path when the clock signals change in write address: the write address is usually +1. 当该写地址接近或远离读地址时,可以将该写地址重新设置新地址。 When the write address close to or away from the read address, you can reset the write address new address. 需要指出的是:在一写时隙过程中,正在将该路数据写入RAM某一存储地址中相应BIT位时,RAM中其他路数的比特数据应该保持不变,也就是说,每个时隙只修改该时隙对应路信号的数据。 It is noted that: during a write time slots, the channel data is being written into a RAM memory addresses the corresponding BIT is, data of other bits in RAM large ones should remain unchanged, that is, each only modify the time slot corresponding to the slot of the data signals.

[0064] 在读时隙到来时,读取读地址对应存储单元开始的8个比特数据,在读时钟沿发生变化时修改读地址,通常是将该读地址+1。 [0064] When reading slot arrives, the read address corresponding to the read data storing unit 8 start bits, modifications read address in the read clock edge changes, the read address is usually +1.

[0065] 每一路的存储写地址、读地址可以存储在可编程逻辑器件的寄存器中。 [0065] The write address stored in each way, the read address may be stored in a register in programmable logic devices.

[0066] 对整个可编程逻辑器件来说,读写是同时进行的,RAM的读写地址有一个起始距离,通常为RAM深度的一半。 [0066] the entire programmable logic device, the reading and writing are performed simultaneously, the read address of RAM has a start distance, usually half the depth of the RAM. 由于写时钟与读时钟不同时钟源,频率上也有抖动,所以随着时间不断增长,读写地址或是会越来越近,或是会越来越远,直至达到两者距离小到零或是距离大到RAM深度的大小,此时系统会强制把读写置新值,以防止地址冲突,于是就产生了滑码。 Since writing different clock source clock and read clock, the frequency of jitter, so grow over time, can read and write addresses or getting closer, or will it farther and farther, until both from small to zero or large depth is a distance the size of RAM, then the system will be forced to write the new value is set to prevent address conflict, and thus a slip code. 为了减少单位时间内滑码次数,或是增大滑码间隔时间可以加大RAM深度,但是RAM 深度变大以后会导致滞后时间增大。 In order to reduce the number of slips per unit time, or the interval can be increased to increase the slips RAM depth, but the depth of the RAM after the lag time can cause large increases. 既要保证滑码间隔的时间不能太小,又要保证滞后时间不能太大,因而RAM深度的选择就是滑码时间与延迟矛盾的一个折中。 Necessary to ensure that the time interval is not too small slips, but also to ensure the lag time can not be too large, and thus the choice is a compromise slips delay time contradiction RAM depth. 按照国家标准,El 信号再定时的存储时间至少要125us+18us (其中,125us是存储时间,ISus是滞后时间), 可根据具体的设计做出选择。 Accordance with national standards, retiming the signal storage time to El least 125us + 18us (wherein, the storage time is 125us, ISUS lag time), can make a choice depending on the particular design. 由于国家标准很宽泛,只要存储时间大于125us,滞后时间大于18us就可以。 Since the state standard is very broad, long storage time is greater than 125us, the lag time can be greater than 18us. 也就是说存储深度大于256BIT,即El信号的一帧,就可以;由于我们设计时采取读写地址距离为深度一半,所以滞后BIT最少为128BIT,即滞后时间最少是62. 5us。 That is greater than 256BIT memory depth, i.e., a signal El, can; because we designed to take the read address distance is half depth, the minimum hysteresis 128BIT BIT, i.e., the lag period is at least 62. 5us. 因此,该设计的这两个指标都是符合了国家标准的。 Therefore, the design of these two indicators are in line with national standards. 在这种条件下,发明人的设计提供了1024bit, 768bit,512bit,256bit四种深度选择,用户可以通过寄存器自行选择。 Under these conditions, the inventors design provides 1024bit, 768bit, 512bit, 256bit four kinds of depth selection, the user can choose by the register. 根据经验, 通常而言,深度不大于2048bit。 According to experience, generally, the depth is not greater than 2048bit. 由于每路都有一个单独的写地址,在强制拉开读写地址距离的时候,采用写地址更新,而读地址不变的设计,可保证任何一路的滑码不会影响到其他路数据。 Because each has a separate write address, read address when forced to pull away, the write-address updates, and read the same address design, can ensure that any slip all the way to the code will not affect other road data.

[0067] 对于整个再定时系统而言,相对以前的设计,只使用了一个RAM,而传输路数没有减少。 [0067] retiming for the entire system, compared to the past design, using only a RAM, and no reduction in the transmission of large ones. 这样节省了FPGA资源,可以使用小容量芯片代替大容量芯片,从而降低了系统成本。 This saves FPGA resources, may be used instead of a mass of small capacity chips chip, thus reducing system cost.

[0068] 以上公开仅为本发明的几个具体实施例,并本发明并非局限于此,任何本领域的技术人员能思之的变化都应落在本发明的保护范围内。 [0068] Although the invention has more than a few specific embodiments disclosed embodiments, and the present invention is not limited thereto, anyone skilled in the art can think of variations shall fall within the scope of the present invention.

Claims (8)

  1. 1. 一种实现多路信号再定时的方法,应用于SDH系统中多路低速信号的再定时,其特征在于,包括:(1)锁存每一路的数据,并产生每一路的写地址和公共的读地址;所述公共的读地址是指:为所述每一路共用的读地址;(2)由系统时钟产生若干时隙,所述时隙分为用于将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙;(3)在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中;(4)在读时隙到来时,将所有路的数据并行读出;其中,所述系统时钟的频率大于MX低速信号频率X (路数+1),M为RAM读数据、改写数据、写入数据所需周期数之和;RAM的宽度等于低速信号的路数,RAM的深度根据系统允许最大、最小缓存时间选取。 A method for realizing multi-channel signal retiming of SDH systems applied retiming multiple low-speed signal, characterized by comprising: a data latch for each channel (1), and generates a write address for each path and common read address; the common read address refers to: a common read address to each of said road; (2) a plurality of slots generated by the system clock, a time slot for each channel data into serial write slot and write into the RAM data channel parallel readout of all of the read time slot; (3) time slots at each arrival of a write, the write channel slot corresponding to the latched data is written to RAM (random Access memory ); and (4) in the read slot arrives, the data is read out in parallel for all paths; wherein the frequency of the system clock signal frequency is greater than the low-MX X (large ones +1), M is a RAM read data, rewriting data , the number of cycles required to write data and; RAM is equal to the width of the large ones of low-speed signal, the maximum allowable depth of the RAM, the minimum buffer time selected based system.
  2. 2.如权利要求1所述的实现多路信号再定时的方法,其特征在于,步骤(1)之前还包括:将所述系统时钟的频率设置为大于MX低速信号频率X (路数+1),M为RAM读数据、 改写数据、写入数据所需周期数之和;将RAM的宽度设置为N个低速信号的路数。 2. The method as claimed multiplex signal retiming of realization according to claim 1, characterized in that, prior to the step (1) further comprises: setting the frequency of the system clock signal frequency is greater than the low-MX X (large ones +1 ), M is a data RAM read, the data is rewritten, the number of cycles required for writing and data; the width of the RAM is set to the large ones of the N low-speed signals.
  3. 3 如权利要求1或2所述的实现多路信号再定时的方法,其特征在于,步骤(3)将所述写时隙对应路锁存的数据写入RAM中,具体为:先读出该路写地址对应的RAM存储单元中的数据,再将该路锁存的数据置入该路对应BIT特位,写入该路写地址对应的RAM存储单元中,并将其他路的BIT位数据保持不变。 The method of multiplex 3 timing signal is then implemented to claim 1 or claim 2, wherein the step (3) time slots corresponding to the write data written to the RAM latch passage, specifically: first readout the RAM write data path corresponding to the address in the storage unit, and then the data latched into the path corresponding to the path bIT Laid-bit writes the write channel RAM address corresponding to the memory cell, and the other channel bits bIT data remains unchanged.
  4. 4.如权利要求1或2所述的实现多路信号再定时的方法,其特征在于,步骤(3)将所述写时隙对应路锁存的数据写入RAM中具体为:先将该路锁存的数据写入RAM中该路写地址对应的存储单元,然后修改该路的写地址。 A method as claimed multiplex signal retiming of realization of claim 1 or 2, wherein step (3) time slots corresponding to the write data written to the RAM latch passage specifically: the first Road latched data is written to the RAM of the path corresponding to the write address of the memory cell, the write address and then modify the path.
  5. 5.如权利要求4所述的实现多路信号再定时的方法,其特征在于,所述修改该路的写地址包括将写地址加一或加X,所述X为RAM深度一半。 5. The method as claimed multiplex signal retiming of realization according to claim 4, wherein said modifying the write address path comprises a write address plus or plus X, X is the half of the RAM depth.
  6. 6.如权利要求1或2所述的实现多路信号再定时的方法,其特征在于,步骤(4)具体为:在读时隙到来时,读取读地址对应的存储单元的N个数据,然后修改所述读地址,所述N为信号路数,所述修改读地址包括将读地址加一。 6. A method as claimed multiplex signal retiming of realization of claim 1 or 2, wherein step (4) is specifically: When reading slot arrives, reading N data memory cells corresponding to the read address, and modifying the read address signal N is large ones, the read address comprises modifying the read address plus one.
  7. 7. 一种实现多路信号再定时的装置,应用于SDH系统中多路低速信号的再定时,其特征在于,包括:时隙分配单元、锁存单元和控制子单元,其中:锁存单元:锁存每一路的数据,并产生每一路的写地址和公共的读地址;所述公共的读地址是指:为所述每一路共用的读地址;时隙分配单元:由系统时钟产生若干时隙,所述时隙分为用于将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙;控制子单元:在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中;在读时隙到来时,将所有路的数据并行读出;其中,所述系统时钟的频率大于MX低速信号频率X (路数+1),M为RAM读数据、改写数据、写入数据所需周期数之和;所述RAM的宽度等于低速信号路数,RAM的深度根据系统允许最大、最小缓存时间选取。 An apparatus for implementing multiplex signal retiming applied to SDH systems retiming multiple low-speed signal, characterized by comprising: a time slot allocating unit, a latch unit and a control sub-unit, wherein: the latch means : latch data of each channel, and generates a write address for each channel and a common read address; the common read address refers to: a common read address to each of said channel; time slot allocation unit: generating a plurality of clocks by the system when writing each incoming time slot: a control sub-unit; slot, the slot into the serial data for each channel written in the RAM write and read time slot data time slot channel parallel readout of all of the , the write time slot corresponding to the latched data is written to channel RAM (random Access memory); and in reading slot arrives, the data is read out in parallel for all paths; wherein said system clock signal frequency greater than the frequency of the low-speed MX X (large ones +1), M is a data RAM read, the data is rewritten, the number of cycles required for writing and data; width of the RAM is equal to the low-speed signal large ones, the maximum allowable depth of the RAM, the minimum buffer time selected based system .
  8. 8.如权利要求7所述的多路信号再定时的装置,其特征在于,所述RAM的深度为1024BIT、768BIT、512BIT 和256BIT 中的其中之一。 8. A multiplex signal according to the retiming device of claim 7, characterized in that the depth of the RAM is one 1024BIT, 768BIT, 512BIT and in 256BIT.
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CN1551507A (en) 2003-05-09 2004-12-01 日本电气株式会社 Serial-to-parallel- and parallel-to-serial converter

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