CN114024844A - Data scheduling method, data scheduling device and electronic equipment - Google Patents
Data scheduling method, data scheduling device and electronic equipment Download PDFInfo
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- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40143—Bus networks involving priority mechanisms
- H04L12/4015—Bus networks involving priority mechanisms by scheduling the transmission of messages at the communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0896—Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40267—Bus for use in transportation systems
- H04L2012/4028—Bus for use in transportation systems the transportation system being an aircraft
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Abstract
The application discloses a data scheduling method, a data scheduling device and electronic equipment. The method is applied to the FPGA in the node and comprises the following steps: receiving configuration information and storing the configuration information to a local cache module; receiving data to be sent of the communication port, and storing the data to be sent of the communication port to an external memory according to the address index in the configuration information; taking the virtual link meeting the first preset condition as a target virtual link; respectively determining a target communication port for each target virtual link; reading data to be sent of a target communication port from an external memory according to the address index in the configuration information, and storing the data to be sent to a local cache module; and when the AFDX bus is idle, transmitting the data to be transmitted of the target communication port to the AFDX bus. Based on the technical scheme disclosed by the application, the scheduling of AFDX bus data can be realized without occupying resources of an operating system and software in the node, and the data scheduling has higher accuracy and stability.
Description
Technical Field
The present application belongs to the field of communications technologies, and in particular, to a data scheduling method, a data scheduling apparatus, and an electronic device.
Background
Communication services of a new generation of avionics system have been expanded from traditional data communication and voice communication to various services such as high-speed data, images, multimedia and the like, and requirements on integration, expandability, bandwidth, transmission real-time property, reliability and the like of an information transmission network are higher and higher. Conventional information transmission networks based on the ARINC 429 protocol or the Mil-STD-1553B bus (aircraft interior time division command/response multiplexed data bus) are not sufficient to meet such high bandwidth and rate requirements.
Under the background, an AFDX (avinics Full Duplex Switched Ethernet) bus derived by adaptive modification based on the conventional Ethernet communication standard has higher reliability, stronger adaptability to severe environments and higher real-time performance, the transmission rate of the AFDX bus can reach 100Mbit/s or even 1000Mbit/s, the AFDX bus can well meet the application requirements of the current Avionics system, and the AFDX bus is widely applied to the current large-scale passenger aircraft such as a380 and C919.
In a conventional bus network, message scheduling is generally performed by software or by combining software and hardware, and the message scheduling mode is relatively simple and easy to implement. However, the number of messages that can be carried is limited by software or by a manner of scheduling messages by combining software and hardware, and when the number of messages is large, a large amount of processor resources and memory resources are often consumed, so that the time for task execution and message processing is long. In addition, because the timing accuracy of the operating system itself is general, the scheduling deviation of the messages is often large, and the deviation is large when the number of the messages is large. In an AFDX bus, the bus bandwidth can reach hundreds of megabytes or even gigabytes, the longest length of a message can reach 8192 bytes, meanwhile, the number of messages of a single node is often more than hundreds, great challenges are brought to message scheduling, and the traditional message scheduling mode cannot meet the characteristic requirements of the AFDX bus.
Disclosure of Invention
In view of this, an object of the present application is to provide a data scheduling method, a data scheduling apparatus, and an electronic device, which implement scheduling of AFDX bus data without occupying resources of an operating system and software in a node, and improve stability and accuracy of data scheduling.
In order to achieve the above purpose, the present application provides the following technical solutions:
the application provides a data scheduling method, which is applied to a programmable logic chip in a node, and comprises the following steps:
receiving configuration information, and storing the configuration information to a local cache module, where the configuration information includes description information of a virtual link, description information of each communication port under the virtual link, and an address index of an external memory corresponding to each communication port, where the description information of the virtual link includes an identifier of the virtual link and a bandwidth allocation interval of the virtual link, and the description information of the communication port at least includes an identifier of the communication port;
receiving data to be sent of a communication port, and storing the data to be sent of the communication port to the external memory according to the address index in the configuration information;
the method comprises the following steps of taking a virtual link meeting a first preset condition as a target virtual link, wherein the first preset condition comprises the following steps: the time interval of the latest data transmission from the current moment to the virtual link is greater than or equal to the bandwidth allocation interval of the virtual link;
respectively determining a target communication port for each target virtual link;
reading the data to be sent of the target communication port from the external memory according to the address index in the configuration information, and storing the data to be sent of the target communication port to a local cache module;
and when the AFDX bus is idle, transmitting the data to be transmitted of the target communication port to the AFDX bus.
Optionally, the description information of the communication port further includes a communication type of the communication port, where the communication type of the communication port includes a periodic type and a non-periodic type, and when the communication type of the communication port is the periodic type, the description information of the communication port further includes a communication period of the communication port;
determining a target communication port for any one of the target virtual links, including:
searching a communication port meeting a second preset condition in the communication ports under the target virtual link as an alternative communication port, wherein the second preset condition comprises: the communication type of the communication port is periodic, and the time interval between the current moment and the moment when the communication port sends data last time is greater than or equal to the communication period of the communication port, or the communication type of the communication port is non-periodic;
and determining a target communication port from the alternative communication ports according to a preset rule.
Optionally, the determining a target communication port from the alternative communication ports according to a preset rule includes:
and under the condition that the number of the alternative communication ports is multiple, respectively determining the time interval between the latest data transmission time and the current time of each alternative communication port, and determining the alternative communication port with the largest time interval as the target communication port.
Optionally, after receiving the data to be sent of the communication port, the method further includes: updating data receiving time corresponding to the communication port;
the determining a target communication port from the alternative communication ports according to a preset rule includes: and under the condition that the number of the alternative communication ports is multiple, comparing the data receiving time corresponding to each alternative communication port, determining the alternative communication port with the earliest data receiving time as a target communication port, and clearing the data receiving time corresponding to the target communication port.
Optionally, the method further includes: and if the storage space indicated by the address index corresponding to the target communication port is empty, not performing data scheduling on the virtual link to which the target communication port belongs.
The present application further provides a data scheduling apparatus, which is applied to a programmable logic chip in a node, and the data scheduling apparatus includes:
the configuration information processing unit is used for receiving configuration information and storing the configuration information to a local cache module, wherein the configuration information comprises description information of a virtual link, description information of each communication port under the virtual link and an address index of an external memory corresponding to each communication port, the description information of the virtual link comprises an identifier of the virtual link and a bandwidth allocation interval of the virtual link, and the description information of the communication port at least comprises the identifier of the communication port;
the first data processing unit is used for receiving data to be sent of a communication port and storing the data to be sent of the communication port to the external memory according to the address index in the configuration information;
a target virtual link determining unit, configured to use a virtual link that satisfies a first preset condition as a target virtual link, where the first preset condition includes: the time interval of the latest data transmission from the current moment to the virtual link is greater than or equal to the bandwidth allocation interval of the virtual link;
a target communication port determining unit, configured to determine a target communication port for each target virtual link;
the second data processing unit is used for reading the data to be sent of the target communication port from the external memory according to the address index in the configuration information and storing the data to be sent of the target communication port to a local cache module;
and the data sending unit is used for transmitting the data to be sent of the target communication port to the AFDX bus when the AFDX bus is idle.
Optionally, the description information of the communication port further includes a communication type of the communication port, where the communication type of the communication port includes a periodic type and a non-periodic type, and when the communication type of the communication port is the periodic type, the description information of the communication port further includes a communication period of the communication port;
the target communication port determination unit includes:
a candidate communication port determining subunit, configured to search, as a candidate communication port, a communication port that meets a second preset condition in communication ports under the target virtual link, where the second preset condition includes: the communication type of the communication port is periodic, and the time interval between the current moment and the moment when the communication port sends data last time is greater than or equal to the communication period of the communication port, or the communication type of the communication port is non-periodic;
and the target communication port determining subunit is used for determining a target communication port from the alternative communication ports according to a preset rule.
Optionally, the target communication port determining subunit is specifically configured to:
and under the condition that the number of the alternative communication ports is multiple, respectively determining the time interval between the latest data transmission time and the current time of each alternative communication port, and determining the alternative communication port with the largest time interval as the target communication port.
Optionally, the first data processing unit is further configured to: after the data to be sent of the communication port is received, updating the data receiving time corresponding to the communication port;
the target communication port determination subunit is specifically configured to: and under the condition that the number of the alternative communication ports is multiple, comparing the data receiving time corresponding to each alternative communication port, determining the alternative communication port with the earliest data receiving time as a target communication port, and clearing the data receiving time corresponding to the target communication port.
The present application further provides an electronic device, comprising: the system comprises a processor, a memory and a programmable logic chip;
the memory is used for storing programs and data;
the processor is used for executing the program stored in the memory;
the programmable logic chip is used for: receiving configuration information, and storing the configuration information to a local cache module, where the configuration information includes description information of a virtual link, description information of each communication port under the virtual link, and an address index of each communication port in the memory, where the description information of the virtual link includes an identifier of the virtual link and a bandwidth allocation interval of the virtual link, and the description information of the communication port at least includes an identifier of the communication port; receiving data to be sent of a communication port, and storing the data to be sent of the communication port to the memory according to the address index in the configuration information; the method comprises the following steps of taking a virtual link meeting a first preset condition as a target virtual link, wherein the first preset condition comprises the following steps: the time interval of the latest data transmission from the current moment to the virtual link is greater than or equal to the bandwidth allocation interval of the virtual link; respectively determining a target communication port for each target virtual link; reading the data to be sent of the target communication port from the memory according to the address index in the configuration information, and storing the data to be sent of the target communication port to a local cache module; and when the AFDX bus is idle, transmitting the data to be transmitted of the target communication port to the AFDX bus.
Therefore, the beneficial effects of the application are as follows:
the data scheduling method is executed by an FPGA in a node, after configuration information is received, the configuration information is stored to a local cache module, the configuration information comprises description information of a virtual link, description information of each communication port under the virtual link and address indexes of an external memory corresponding to each communication port, and after data to be sent of the communication ports are received, the data to be sent are stored to corresponding storage spaces of the external memory according to the address indexes in the configuration information; determining whether each virtual link meets a first preset condition, determining the virtual link meeting the first preset condition as a target virtual link, determining a target communication port for each target virtual link, reading data to be sent of the target communication port from an external memory according to an address index in the configuration information, storing the read data to be sent to a local cache module, and transmitting the data to be sent of the target communication port to an AFDX bus when the AFDX bus is idle. It can be seen that the data scheduling method disclosed by the application is executed by the FPGA in the node, and the AFDX bus data can be scheduled without occupying resources of an operating system and software in the node. Moreover, the timing time is generated by the FPGA, so that the accuracy of the timing time can be ensured, and the data scheduling has higher accuracy and stability.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart of a data scheduling method disclosed herein;
FIG. 2 is a schematic illustration of configuration information disclosed herein;
FIG. 3 is a flow chart of a method of determining a target communication port for a target virtual link as disclosed herein;
fig. 4 is a schematic structural diagram of a data scheduling apparatus disclosed in the present application.
Detailed Description
The application discloses a data scheduling method, a data scheduling device and electronic equipment, which realize the scheduling of AFDX bus data and improve the stability and accuracy of data scheduling on the premise of not occupying resources of an operating system and software in a node.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart of a data scheduling method disclosed in the present application. The data scheduling method is applied to an FPGA (Field Programmable Gate Array) in a node, and the node communicates with other nodes through an AFDX (avionics full Duplex switched Ethernet) bus, that is to say, the node in the application refers to a node in an AFDX bus communication system. It should be noted that the node further includes a processor, and the processor executes programs stored in the memory, and the aforementioned programs may include a program for implementing an operating system and a program for implementing an application.
The data scheduling method comprises the following steps:
s101: and receiving the configuration information, and storing the configuration information to a local cache module.
The configuration information includes description information of the virtual link, description information of each communication port under the virtual link, and an address index of the external memory corresponding to each communication port. The description information of the virtual link comprises the identification of the virtual link and the bandwidth allocation interval of the virtual link, and the description information of the communication port at least comprises the identification of the communication port.
The Bandwidth Allocation interval is known by the english name Bandwidth Allocation Gap and by the english abbreviation BAG, and is used to indicate: the minimum time interval between the start bits (which are binary bits) of two adjacent frames in the same virtual link.
In the present application, messages are scheduled in units of virtual links according to the characteristics of the AFDX bus. Each virtual link may include several communication ports, each communication port having a respective periodic attribute, and communication ports belonging to the same virtual link share the bandwidth of the virtual link.
FIG. 2 is a schematic diagram of configuration information disclosed herein. The configuration information includes three levels, the first level is description information of the virtual link, the second level is description information of each communication port under one virtual link, and the third level is an address index of the external memory corresponding to each communication port.
In the initialization process, the upper layer software issues configuration information to the FPGA. The FPGA receives configuration information issued by upper-layer software, and stores the received configuration information to a local cache module, namely to a cache module in the FPGA. It should be noted that after the initialization is completed, the upper layer software cannot modify the configuration information any more. If the upper layer software needs to modify the configuration information, the FPGA needs to be initialized.
S102: and receiving data to be sent of the communication port, and storing the data to be sent of the communication port to an external memory according to the address index in the configuration information.
And the upper layer software issues the data to be sent of the communication port to the FPGA. The FPGA receives data to be sent of a communication port issued by upper-layer software, determines an address index of an external memory corresponding to the communication port according to configuration information, and then stores the data to be sent of the communication port into a corresponding storage space in the external memory. It can be understood that the data to be sent by the upper layer software carries the identifier of the communication port, so that after the FPGA receives the data to be sent, it can determine which communication port the data to be sent is.
It should be noted that, in the initialization process, the upper layer software may issue the data to be sent of the communication port to the FPGA in addition to issue the configuration information to the FPGA. In this case, the FPGA stores the received configuration information to a local cache module, and the FPGA determines, according to the configuration information, an address index of the external memory corresponding to the communication port, and stores the data to be sent of the communication port to a corresponding storage space in the external memory.
The external memory refers to a memory disposed outside the FPGA, and is a memory in the node. In implementations, types of external memory include, but are not limited to, SDRAM and DDR. The English name of SDRAM is Synchronous Dynamic Random Access Memory, and the Chinese name is SDRAM. The DDR is called Double Data Rate SDRAM in English and is called Double-Rate synchronous dynamic random access memory in Chinese.
S103: and taking the virtual link meeting the first preset condition as a target virtual link.
And the FPGA judges whether each virtual link meets a first preset condition or not, and takes the virtual link meeting the first preset condition as a target virtual link. Wherein, the first preset condition comprises: the time interval of the data sent for the last time from the current moment to the virtual link is greater than or equal to the bandwidth allocation interval of the virtual link.
The bandwidth allocation interval of the virtual link is used to indicate: the minimum time interval between the start bits (which are binary bits) of two adjacent frames in the same virtual link. Therefore, the target virtual link needs to satisfy at least: the time interval of the data sent for the last time from the current moment to the virtual link is greater than or equal to the bandwidth allocation interval of the virtual link.
In implementation, the FPGA may determine whether each virtual link satisfies a first preset condition in a polling manner, and use the virtual link satisfying the first preset condition as a target virtual link.
S104: one target communication port is determined for each target virtual link.
After the FPGA determines the target virtual links, executing the following steps for each target virtual link: a target communication port is determined among the plurality of communication ports under the target virtual link. It should be noted that, the FPGA determines one target communication port for each target virtual link, where the target communication port is one of the communication ports under the target virtual link.
S105: and reading the data to be sent of the target communication port from the external memory according to the address index in the configuration information, and storing the data to be sent of the target communication port to a local cache module.
After the FPGA determines the target communication ports, the data to be sent of each target communication port is read from an external memory according to the address index in the configuration information, and the data to be sent of each target communication port is stored in a local cache module.
It should be noted that the storage space indicated by the address index corresponding to the target communication port may be empty, that is, the external memory may not store the data to be sent of the target communication port. Optionally, if the storage space indicated by the address index corresponding to a certain target communication port is empty, the FPGA does not perform data scheduling on the virtual link to which the target communication port belongs this time, and continues to read data to be sent of a next target communication port. Optionally, if the storage space indicated by the address index corresponding to a certain target communication port is empty, the FPGA determines a new target communication port among other communication ports belonging to the same virtual link as the target communication port, reads data to be sent of the new target communication port from an external memory, and stores the data to be sent of the target communication port to a local cache module.
S106: and when the AFDX bus is idle, transmitting the data to be transmitted of the target communication port to the AFDX bus.
The local cache module can store data to be sent of the multiple target communication ports, and the FPGA sequentially transmits the data to be sent of the multiple target communication ports to the AFDX bus when the AFDX bus is idle. Wherein the order may be defined by upper layer software.
The data scheduling method is executed by an FPGA in a node, after configuration information is received, the configuration information is stored to a local cache module, the configuration information comprises description information of a virtual link, description information of each communication port under the virtual link and address indexes of an external memory corresponding to each communication port, and after data to be sent of the communication ports are received, the data to be sent are stored to corresponding storage spaces of the external memory according to the address indexes in the configuration information; determining whether each virtual link meets a first preset condition, determining the virtual link meeting the first preset condition as a target virtual link, determining a target communication port for each target virtual link, reading data to be sent of the target communication port from an external memory according to an address index in the configuration information, storing the read data to be sent to a local cache module, and transmitting the data to be sent of the target communication port to an AFDX bus when the AFDX bus is idle. It can be seen that the data scheduling method disclosed by the application is executed by the FPGA in the node, and the AFDX bus data can be scheduled without occupying resources of an operating system and software in the node. Moreover, the timing time is generated by the FPGA, so that the accuracy of the timing time can be ensured, and the data scheduling has higher accuracy and stability.
In one embodiment of the present application, the description information of the communication port further includes a communication type of the communication port. The communication type of the communication port comprises a periodic type and a non-periodic type, and when the communication type of the communication port is the periodic type, the description information of the communication port further comprises the communication period of the communication port.
Determining a target communication port for any one target virtual link, and adopting a scheme as shown in fig. 3, including:
s301: and searching the communication ports meeting the second preset condition in the communication ports under the target virtual link as alternative communication ports.
Wherein the second preset condition comprises: the communication type of the communication port is periodic, and the time interval between the current time and the latest data transmission time of the communication port is greater than or equal to the communication period of the communication port, or the communication type of the communication port is non-periodic.
S302: and determining a target communication port from the alternative communication ports according to a preset rule.
And if only one of the communication ports under the target virtual link meets the second preset condition, determining the communication port as the target communication port. And if a plurality of communication ports in the communication ports under the target virtual link meet a second preset condition, all the communication ports meeting the second preset condition are used as alternative communication ports, and then a target communication port is determined from the alternative communication ports according to a preset rule.
In the scheme for determining the target communication port for the target virtual link shown in fig. 3 of the present application, first, an alternative communication port is searched for in the communication port under the target virtual link, where if the communication type of the communication port is a periodic type, and a time interval between a current time and a time when the communication port has last transmitted data is greater than or equal to a communication period of the communication port, the communication port may be used as the alternative communication port, and if the communication type of the communication port is an aperiodic type, the communication port may be used as the alternative communication port, and then a target communication port is determined from the alternative communication ports according to a preset rule, which ensures that the target communication ports determined for the target virtual link all satisfy a data transmission condition.
As an embodiment, determining a target communication port from the alternative communication ports according to a preset rule includes: and under the condition that the number of the alternative communication ports is multiple, respectively determining the time interval between the latest data transmission time and the current time of each alternative communication port, and determining the alternative communication port with the largest time interval as the target communication port.
That is, the FPGA records the time when each communication port transmits data, and after determining the candidate communication ports in step S301, calculates the time interval between the latest data transmission time of the candidate communication port and the current time for each candidate communication port, and then determines the candidate communication port with the largest time interval as the target communication port.
It should be noted that, after each time the communication port sends data, the FPGA needs to update the time when the communication port sends data.
In addition, the storage space indicated by the address index of the target communication port determined according to the above rule may be empty, that is, the external memory does not store the data to be sent of the target communication port.
Optionally, if the storage space indicated by the address index corresponding to the target communication port is empty, data scheduling is not performed on the virtual link to which the target communication port belongs this time.
Optionally, if the storage space indicated by the address index corresponding to the target communication port is empty, a new target communication port is determined among other alternative communication ports belonging to the same virtual link as the target communication port. For example, among other alternative communication ports belonging to the same virtual link as the target communication port, an alternative communication port having a second largest time interval is determined as a new target communication port.
As another embodiment, after receiving data to be sent at a communication port, the method further includes: and updating the data receiving time corresponding to the communication port. Correspondingly, determining a target communication port from the alternative communication ports according to a preset rule comprises the following steps: and under the condition that a plurality of alternative communication ports are provided, comparing the data receiving time corresponding to each alternative communication port, determining the alternative communication port with the earliest data receiving time as a target communication port, and clearing the data receiving time corresponding to the target communication port.
After receiving the data to be sent of the communication port sent by the upper layer software, the FPGA records the data receiving time corresponding to the communication port, that is, the time when the data to be sent of the communication port is received, in addition to storing the data to be sent of the communication port to the external memory according to the address index in the configuration information. After the FPGA executes step S301 to determine the alternative communication ports, the data receiving time corresponding to each alternative communication port is compared, the alternative communication port with the earliest data receiving time is determined as the target communication port, and the data receiving time corresponding to the target communication port is cleared. This can ensure that data issued earlier by upper software can be sent earlier to the target through the AFDX bus.
It should be noted that, after receiving data to be sent of a communication port issued by upper-layer software each time, the FPGA needs to update data receiving time corresponding to the communication port, and after determining the communication port as a target communication port, the FPGA clears the data receiving time corresponding to the communication port.
In implementation, the target communication port is determined for the target virtual link, and other schemes may also be adopted.
For example: and respectively determining the time interval between the latest data sending time and the current time of each communication port under the target virtual link, and determining the communication port with the largest time interval as the target communication port.
For example: and comparing the data receiving time corresponding to each communication port under the target virtual link, and determining the communication port with the earliest data receiving time as the target communication port.
The application discloses a data scheduling method and correspondingly a data scheduling device, and the description of the data scheduling method and the data scheduling device in the specification can be mutually referred to.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a data scheduling apparatus disclosed in the present application. The data scheduling device is applied to an FPGA in a node, the node is communicated with other nodes through an AFDX bus, namely, the node in the application refers to a node in an AFDX bus communication system. It should be noted that the node further includes a processor, and the processor executes a program stored in the processor, where the program may include a program for implementing an operating system and a program for implementing an application.
The data scheduling apparatus includes:
and the configuration information processing unit 10 is configured to receive the configuration information and store the configuration information in a local cache module. The configuration information includes description information of the virtual link, description information of each communication port under the virtual link, and an address index of the external memory corresponding to each communication port. The description information of the virtual link comprises the identification of the virtual link and the bandwidth allocation interval of the virtual link, and the description information of the communication port at least comprises the identification of the communication port.
The first data processing unit 20 is configured to receive data to be sent from the communication port, and store the data to be sent from the communication port in the external memory according to the address index in the configuration information.
A target virtual link determining unit 30, configured to use a virtual link satisfying a first preset condition as a target virtual link. Wherein, the first preset condition comprises: the time interval of the data sent for the last time from the current moment to the virtual link is greater than or equal to the bandwidth allocation interval of the virtual link.
A target communication port determining unit 40, configured to determine one target communication port for each target virtual link.
And the second data processing unit 50 is configured to read, according to the address index in the configuration information, data to be sent of the target communication port from the external memory, and store the data to be sent of the target communication port to the local cache module.
And a data sending unit 60, configured to transmit data to be sent at the target communication port to the AFDX bus when the AFDX bus is idle.
The data scheduling device disclosed by the application is arranged in the FPGA in the node, so that the AFDX bus data can be scheduled without occupying resources of an operating system and software in the node. Moreover, the timing time is generated by the FPGA, so that the accuracy of the timing time can be ensured, and the data scheduling has higher accuracy and stability.
Optionally, if the storage space indicated by the address index corresponding to a certain target communication port is empty, the data scheduling device does not perform data scheduling on the virtual link to which the target communication port belongs this time, and continues to read data to be sent of a next target communication port.
Optionally, if the storage space indicated by the address index corresponding to a certain target communication port is empty, the data scheduling device determines a new target communication port among other communication ports belonging to the same virtual link as the target communication port, reads the data to be sent of the new target communication port from the external memory, and stores the data to be sent of the target communication port to the local cache module.
In one embodiment of the present application, the description information of the communication port further includes a communication type of the communication port. The communication type of the communication port comprises a periodic type and a non-periodic type, and when the communication type of the communication port is the periodic type, the description information of the communication port further comprises the communication period of the communication port.
The target communication port determination unit 40 includes:
the alternative communication port determining subunit is configured to search, as an alternative communication port, a communication port that meets a second preset condition in communication ports under the target virtual link, where the second preset condition includes: the communication type of the communication port is periodic, and the time interval between the current moment and the moment when the communication port sends data last time is greater than or equal to the communication period of the communication port, or the communication type of the communication port is non-periodic;
and the target communication port determining subunit is used for determining the target communication port from the alternative communication ports according to a preset rule.
As an embodiment, the target communication port determining subunit is specifically configured to: and under the condition that the number of the alternative communication ports is multiple, respectively determining the time interval between the latest data transmission time and the current time of each alternative communication port, and determining the alternative communication port with the largest time interval as the target communication port.
Optionally, if the storage space indicated by the address index corresponding to the target communication port is empty, the data scheduling apparatus does not perform data scheduling on the virtual link to which the target communication port belongs this time.
Optionally, if the storage space indicated by the address index corresponding to the target communication port is empty, the target communication port determination subunit determines a new target communication port from other alternative communication ports belonging to the same virtual link as the target communication port. For example, the target communication port determination subunit determines, as the new target communication port, an alternative communication port having the second largest time interval among the other alternative communication ports belonging to the same virtual link as the target communication port.
As another embodiment, the first data processing unit 20 is further configured to: and after receiving the data to be sent of the communication port, updating the data receiving time corresponding to the communication port. Correspondingly, the target communication port determining subunit is specifically configured to: and under the condition that a plurality of alternative communication ports are provided, comparing the data receiving time corresponding to each alternative communication port, determining the alternative communication port with the earliest data receiving time as a target communication port, and clearing the data receiving time corresponding to the target communication port.
The application also discloses an electronic device. The electronic equipment at least comprises a processor, a memory and an FPGA, and the processor, the memory and the FPGA can be communicated with each other.
The processor may be a central processing unit CPU, or an application Specific Integrated circuit asic, or one or more Integrated circuits, etc. The memory may comprise high speed RAM memory and may also include non-volatile memory. For example, the memory includes SDRAM or DDR. The memory is used to store programs and data, and the processor is used to execute the programs stored by the memory, which may include programs that implement an operating system and programs that implement applications.
The FPGA is used for:
receiving configuration information, and storing the configuration information to a local cache module, wherein the configuration information comprises description information of a virtual link, description information of each communication port under the virtual link, and an address index of a memory corresponding to each communication port, the description information of the virtual link comprises an identifier of the virtual link and a bandwidth allocation interval of the virtual link, and the description information of the communication port at least comprises an identifier of the communication port;
receiving data to be sent of the communication port, and storing the data to be sent of the communication port to a memory according to the address index in the configuration information;
the method comprises the following steps of taking a virtual link meeting a first preset condition as a target virtual link, wherein the first preset condition comprises the following steps: the time interval of the latest data transmission from the current moment to the virtual link is greater than or equal to the bandwidth allocation interval of the virtual link;
respectively determining a target communication port for each target virtual link;
reading data to be sent of the target communication port from a memory according to the address index in the configuration information, and storing the data to be sent of the target communication port to a local cache module;
and when the AFDX bus is idle, transmitting the data to be transmitted of the target communication port to the AFDX bus.
Alternatively, the refinement function and the extension function of the FPGA may be as described above.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The data scheduling device and the electronic device disclosed in the embodiments correspond to the method disclosed in the embodiments, so the description is relatively simple, and the relevant points can be referred to the description of the method.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A data scheduling method is applied to a programmable logic chip in a node, and the data scheduling method comprises the following steps:
receiving configuration information, and storing the configuration information to a local cache module, where the configuration information includes description information of a virtual link, description information of each communication port under the virtual link, and an address index of an external memory corresponding to each communication port, where the description information of the virtual link includes an identifier of the virtual link and a bandwidth allocation interval of the virtual link, and the description information of the communication port at least includes an identifier of the communication port;
receiving data to be sent of a communication port, and storing the data to be sent of the communication port to the external memory according to the address index in the configuration information;
the method comprises the following steps of taking a virtual link meeting a first preset condition as a target virtual link, wherein the first preset condition comprises the following steps: the time interval of the latest data transmission from the current moment to the virtual link is greater than or equal to the bandwidth allocation interval of the virtual link;
respectively determining a target communication port for each target virtual link;
reading the data to be sent of the target communication port from the external memory according to the address index in the configuration information, and storing the data to be sent of the target communication port to a local cache module;
and when the AFDX bus is idle, transmitting the data to be transmitted of the target communication port to the AFDX bus.
2. The data scheduling method according to claim 1, wherein the description information of the communication port further includes a communication type of the communication port, the communication type of the communication port includes a periodic type and a non-periodic type, and when the communication type of the communication port is the periodic type, the description information of the communication port further includes a communication period of the communication port;
determining a target communication port for any one of the target virtual links, including:
searching a communication port meeting a second preset condition in the communication ports under the target virtual link as an alternative communication port, wherein the second preset condition comprises: the communication type of the communication port is periodic, and the time interval between the current moment and the moment when the communication port sends data last time is greater than or equal to the communication period of the communication port, or the communication type of the communication port is non-periodic;
and determining a target communication port from the alternative communication ports according to a preset rule.
3. The data scheduling method according to claim 2, wherein the determining a target communication port from the alternative communication ports according to a preset rule comprises:
and under the condition that the number of the alternative communication ports is multiple, respectively determining the time interval between the latest data transmission time and the current time of each alternative communication port, and determining the alternative communication port with the largest time interval as the target communication port.
4. The data scheduling method of claim 2, further comprising, after receiving data to be transmitted from the communication port: updating data receiving time corresponding to the communication port;
the determining a target communication port from the alternative communication ports according to a preset rule includes: and under the condition that the number of the alternative communication ports is multiple, comparing the data receiving time corresponding to each alternative communication port, determining the alternative communication port with the earliest data receiving time as a target communication port, and clearing the data receiving time corresponding to the target communication port.
5. The data scheduling method of claim 1, further comprising:
and if the storage space indicated by the address index corresponding to the target communication port is empty, not performing data scheduling on the virtual link to which the target communication port belongs.
6. A data scheduling apparatus, applied to a programmable logic chip in a node, the data scheduling apparatus comprising:
the configuration information processing unit is used for receiving configuration information and storing the configuration information to a local cache module, wherein the configuration information comprises description information of a virtual link, description information of each communication port under the virtual link and an address index of an external memory corresponding to each communication port, the description information of the virtual link comprises an identifier of the virtual link and a bandwidth allocation interval of the virtual link, and the description information of the communication port at least comprises the identifier of the communication port;
the first data processing unit is used for receiving data to be sent of a communication port and storing the data to be sent of the communication port to the external memory according to the address index in the configuration information;
a target virtual link determining unit, configured to use a virtual link that satisfies a first preset condition as a target virtual link, where the first preset condition includes: the time interval of the latest data transmission from the current moment to the virtual link is greater than or equal to the bandwidth allocation interval of the virtual link;
a target communication port determining unit, configured to determine a target communication port for each target virtual link;
the second data processing unit is used for reading the data to be sent of the target communication port from the external memory according to the address index in the configuration information and storing the data to be sent of the target communication port to a local cache module;
and the data sending unit is used for transmitting the data to be sent of the target communication port to the AFDX bus when the AFDX bus is idle.
7. The data scheduling device of claim 6, wherein the description information of the communication port further includes a communication type of the communication port, the communication type of the communication port includes a periodic type and a non-periodic type, and when the communication type of the communication port is the periodic type, the description information of the communication port further includes a communication period of the communication port;
the target communication port determination unit includes:
a candidate communication port determining subunit, configured to search, as a candidate communication port, a communication port that meets a second preset condition in communication ports under the target virtual link, where the second preset condition includes: the communication type of the communication port is periodic, and the time interval between the current moment and the moment when the communication port sends data last time is greater than or equal to the communication period of the communication port, or the communication type of the communication port is non-periodic;
and the target communication port determining subunit is used for determining a target communication port from the alternative communication ports according to a preset rule.
8. The data scheduling apparatus of claim 7, wherein the target communication port determining subunit is specifically configured to:
and under the condition that the number of the alternative communication ports is multiple, respectively determining the time interval between the latest data transmission time and the current time of each alternative communication port, and determining the alternative communication port with the largest time interval as the target communication port.
9. The data scheduling apparatus of claim 7, wherein the first data processing unit is further configured to: after the data to be sent of the communication port is received, updating the data receiving time corresponding to the communication port;
the target communication port determination subunit is specifically configured to: and under the condition that the number of the alternative communication ports is multiple, comparing the data receiving time corresponding to each alternative communication port, determining the alternative communication port with the earliest data receiving time as a target communication port, and clearing the data receiving time corresponding to the target communication port.
10. An electronic device, comprising: the system comprises a processor, a memory and a programmable logic chip;
the memory is used for storing programs and data;
the processor is used for executing the program stored in the memory;
the programmable logic chip is used for: receiving configuration information, and storing the configuration information to a local cache module, where the configuration information includes description information of a virtual link, description information of each communication port under the virtual link, and an address index of each communication port in the memory, where the description information of the virtual link includes an identifier of the virtual link and a bandwidth allocation interval of the virtual link, and the description information of the communication port at least includes an identifier of the communication port; receiving data to be sent of a communication port, and storing the data to be sent of the communication port to the memory according to the address index in the configuration information; the method comprises the following steps of taking a virtual link meeting a first preset condition as a target virtual link, wherein the first preset condition comprises the following steps: the time interval of the latest data transmission from the current moment to the virtual link is greater than or equal to the bandwidth allocation interval of the virtual link; respectively determining a target communication port for each target virtual link; reading the data to be sent of the target communication port from the memory according to the address index in the configuration information, and storing the data to be sent of the target communication port to a local cache module; and when the AFDX bus is idle, transmitting the data to be transmitted of the target communication port to the AFDX bus.
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