CN117768418A

CN117768418A - Time-triggered switch with expandable port

Info

Publication number: CN117768418A
Application number: CN202311830478.2A
Authority: CN
Inventors: 龚国辉; 陈俊贤; 卢灵敏; 吴圳羲; 周嘉礼; 王磊
Original assignee: Hunan Greatwall Galaxy Technology Co ltd
Current assignee: Hunan Greatwall Galaxy Technology Co ltd
Priority date: 2023-12-27
Filing date: 2023-12-27
Publication date: 2024-03-26

Abstract

A time trigger switch of an expandable port comprises a MAC layer module, a MAC address module, a data link scheduling module, a mixed data scheduling module, a descriptor caching module and a data link transmission control module; the MAC layer module is divided into a transmitting port module and a receiving port module; the MAC address module is connected with the receiving port module; the data link scheduling module is connected with the receiving port module; the mixed data scheduling module is connected with the data link scheduling module; the descriptor cache module is connected with the data link scheduling module; the input end of the data link transmission control module is connected with the mixed data scheduling module and the descriptor caching module, and the output end of the data link transmission control module is connected with the transmission port module of the MAC layer. Compared with a commercial switch, the invention can forward time trigger data and other data, can realize the preemption of the time trigger data, can be used as a main node in time synchronization, and can realize the global time synchronization of a time trigger communication system.

Description

Time-triggered switch with expandable port

Technical Field

The invention relates to the technical field of switch equipment, in particular to a time-triggered switch with an extensible port.

Background

The high-speed development of avionics systems has higher and higher requirements on an onboard network, and high requirements are put on network bandwidth, instantaneity, reliability and the like. With the expansion and development of avionics systems, the requirements for equipment information interaction are larger and larger, and the requirements for real-time performance are higher and higher. The traditional communication mode has been gradually replaced by a new generation avionic communication mode such AS time triggered ethernet, AFDX, etc., and related time triggered ethernet protocols include AS6802, IEEE1588, etc.

The key component for realizing the time-triggered Ethernet function is a time-triggered switch which is responsible for forwarding the time-triggered data frames and the event-triggered data frames, is used as a central node in a time-triggered communication system, and also has the function of time synchronization. Compared with a common commercial switch, the time-triggered switch is compatible with a time-triggered Ethernet protocol, and the expansion of functions of the time-triggered switch makes the structure complex. The scale of the time-triggered Ethernet system is continuously enlarged and developed, and the functional complexity is obviously improved, so that when the time-triggered Ethernet technology is applied, a software and hardware platform for realizing the time-triggered Ethernet technology is required from the aspects of realization and cost, and the strong instantaneity, the high certainty and the high reliability of the time-triggered Ethernet system are ensured.

Disclosure of Invention

The invention provides a time trigger switch of an extensible port, which aims to solve the technical problem that the existing time trigger switch is compatible with a time trigger Ethernet protocol and has a complex structure.

In order to achieve the above purpose, the technical scheme of the invention is realized as follows:

the invention provides a time trigger switch of an extensible port, which comprises the following components:

the MAC layer module is used for completing the receiving and transmitting of the physical layer protocol data and is divided into a sending port module and a receiving port module;

the MAC address module is connected with the receiving port module and is responsible for recording the corresponding relation between the MAC address and the port and finishing the functions of address writing and inquiry;

the input end of the data link scheduling module is connected with the receiving port module and is used for classifying the data frames;

the input end of the mixed data scheduling module is connected with the output end of the data link scheduling module and is responsible for data caching during link channel selection;

the input end of the descriptor caching module is connected with the output end of the data link scheduling module, and the descriptor caching module is responsible for caching the descriptors transmitted by the data link scheduling module;

the input end of the data link transmission control module is respectively connected with the output ends of the mixed data scheduling module and the descriptor caching module, and the output end of the data link transmission control module is connected with the transmission port module of the MAC layer and is responsible for forwarding the data frames in the mixed data caching module;

the time synchronization control module is connected with the sending port module and is responsible for generating a local time stamp of the switch and controlling the sending time of the time synchronization frame, and the time stamp is packaged into the time synchronization frame in the sending port module and sent.

Further, the receiving port module in the MAC layer module includes:

the receiving processing module mac_rx is used for receiving the Ethernet data frames from other terminal nodes and extracting the destination MAC address, the source MAC address and the frame type information in the Ethernet header according to the Ethernet frame format;

the computing module RX_CRC is connected with the receiving processing module mac_rx and is used for computing CRC check codes and transmitting the computed CRC check codes to the receiving processing module mac_rx so as to check the correctness of data frame transmission;

the address inquiry module search is connected with the receiving and processing module mac_rx and is used for inquiring the destination port number according to the destination MAC address transmitted by the receiving and processing module mac_rx; the destination port number is used for judging which port of the switch a frame of Ethernet data is forwarded from;

the input end of the address buffer module SRC_FIFO is connected with the output end of the receiving processing module mac_rx and is responsible for receiving the source MAC address from the mac_rx module, completing clock domain isolation and temporarily storing the MAC address;

the input end of the data caching module RX_RAM is connected with the output end of the receiving and processing module mac_rx and is responsible for caching a complete Ethernet data frame;

and the input end of the data frame information buffer module RX_FIFO is connected with the output end of the receiving processing module mac_rx and is responsible for recording the length, the storage starting address, the type and the destination port number information of the data frame stored in the data buffer module RX_RAM.

Further, the transmitting port module in the MAC layer module includes:

the input end of the data buffer module TX_RAM is connected with the output end of the data link transmission control module;

the input end of the descriptor module TX_FIFO is connected with the output end of the data link transmission control module;

the input end of the transmission processing module mac_tx is connected with the data caching module TX_RAM and the descriptor module TX_FIFO, and is responsible for analyzing the data frame information obtained from the descriptor module TX_FIFO and transmitting the data frame of the data caching module TX_RAM to an external terminal node;

the calculation module TX_CRC is connected with the transmission processing module mac_tx and is responsible for calculating data to be checked.

Further, in the forwarding process, if the time synchronization frame collides with the transmission of other data frames, the transmission port module in the MAC layer module performs preemptive transmission on the time synchronization frame, and retransmits the preempted data frame after the transmission is completed, so as to ensure global clock synchronization;

the transmitting port module and the receiving port module in the MAC layer module adopt an Ethernet communication clock of 125MHz, the receiving processing module mac_rx and the transmitting processing module mac_tx adopt 200MHz clocks, and the interaction is realized between the two clock domains of 125MHz clocks and 200MHz clocks by adopting a real dual-port RAM structure so as to reduce the forwarding processing delay of the time-triggered switch.

Further, the MAC address module includes:

the input end of the MAC address writing control module is connected with the receiving port module;

n first RAM blocks are connected with the output end of the MAC address writing control module, and are provided with an A port and a B port, wherein the A port is used for learning and accessing an address table, and the B port is used for inquiring the address.

Further, the number of the sending port modules and the receiving port modules in the MAC layer module is set to be N;

the number of the data link scheduling modules and the number of the data link transmission control modules are N;

the input end of the mixed data scheduling module is connected with N receiving port modules in the MAC layer module through N data link scheduling modules;

the output end of the mixed data scheduling module is connected with N transmitting port modules in the MAC layer module through N data link transmitting control modules.

Further, the N first RAM blocks are respectively bound with the N receiving port modules, when the first RAM blocks receive the destination MAC address from the receiving port modules, traversing inquiry access is carried out on the address table, and unicast, multicast and broadcast forwarding of the data frames are realized according to the inquired port numbers;

before data is written into the first RAM blocks, traversing access is carried out on the plurality of first RAM blocks, and when all read data are inconsistent, MAC addresses are directly written into all the first RAM blocks so as to prevent inconsistent data information of each first RAM block.

Further, the hybrid data scheduling module includes:

the input ends of the N condition judgment logic modules CL are respectively connected with the N data link scheduling modules;

N ² the method comprises the steps of dividing the real dual-port RAMs into N groups, sequentially sequencing each group of the real dual-port RAMs from 1to N, respectively connecting the output ends of N condition judgment logic modules CL with the N groups of the real dual-port RAMs, and respectively controlling N data link scheduling modules by the N condition judgment logic modules CL so as to write the data of the N data link scheduling modules into the corresponding real dual-port RAMs;

n selection link logic modules SL for controlling N ² And the data output of the transmitting ports of the true dual-port RAM is carried out, N selection link logic modules SL are sequentially ordered from 1to N, and the input ends of the N selection link logic modules SL are respectively connected with the true dual-port RAM with the same serial number as the transmitting port module.

Further, the true dual-port RAM is divided into three storage spaces, namely an ET data storage address field, a TT data storage address field and an OF other data frame data storage address field, wherein the address range OF the ET data field is 0-0 x7fff, the address range OF the TT data field is 0x 8000-0 xbfff, and the address range OF the BF data field is 0xc 000-0 xffff.

Further, the descriptor caching module includes:

the input end of the write-in control combination logic module is connected with the output end of the data link scheduling module;

2N ² the input ends of the first-in first-out (FIFO) are connected with the output end of the write-in control combination logic module, and the write-in control combination logic module is used for storing the initial address and the data length information of the data frames stored in the mixed data scheduling module into the corresponding FIFO;

read-out control combination logic module, input end and 2N respectively ² The output ends of the FIFOs are connected and are responsible for selecting a route and outputting the route to the data link transmission control module for processing.

The invention has the beneficial effects that:

1. the MAC address module in the invention can manage and learn the MAC address of the equipment connected with each switch port; the port number and the MAC address are bound, and when the destination MAC address from the receiving port is received, the address table is traversed, inquired and accessed, so that unicast, multicast and broadcast forwarding of the data frame can be realized. In order to meet the requirement that all ports can access the same MAC address module at the same time, a management mode of writing the MAC address into a plurality of address tables is adopted, and before writing, traversing access is carried out on the plurality of address tables, when all read data are inconsistent, the MAC address is directly written into all the address tables, and the inconsistent data information of each MAC address module is prevented. The capacity of the MAC address module can be extended according to the communication port requirements.

2. In order to ensure the strong real-time performance of time-triggered Ethernet communication, the invention uses a time synchronization frame preemption transmission mechanism to realize the rapid convergence of time synchronization, and adopts a rapid clock to drive all forwarding processing modules in the forwarding processing process. And when the time synchronization frame collides with the transmission of other data frames at the MAC transmission layer of the transmission port module, the time synchronization frame performs preemptive transmission, and the preempted data frame is retransmitted after the transmission is finished, so that the global clock synchronization is effectively ensured. The transmitting port module and the receiving port module adopt Ethernet communication clocks of 125MHz, the receiving processing module mac_rx and the transmitting processing module mac_tx both adopt 200MHz clocks, and a true dual-port RAM structure is adopted between the two clock domains of 125MHz clocks and 200MHz clocks to realize interaction, so that the forwarding processing delay of the time-triggered switch is reduced, and the overall complexity of the switch is reduced.

Drawings

FIG. 1 is a schematic diagram of the structure of the present invention;

FIG. 2 is a schematic diagram of a receiving port module;

FIG. 3 is a schematic diagram of a transmit port module;

FIG. 4 is a schematic diagram of a MAC address module;

FIG. 5 is a schematic diagram of a hybrid data cache module;

FIG. 6 is a schematic diagram of the internal memory partition of the second RAM;

fig. 7 is a schematic diagram of a descriptor cache module.

Detailed Description

In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many other different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

It should be further noted that, in the embodiments of the present application, the same reference numerals denote the same components or the same parts, and for the same parts in the embodiments of the present application, reference numerals may be given to only one of the parts or the parts in the drawings by way of example, and it should be understood that, for other same parts or parts, the reference numerals are equally applicable.

Referring to fig. 1, an embodiment of the present application provides a time triggered switch with expandable ports, which is described below as a time triggered switch with 8 ports, including:

Each port of the time trigger switch adopts a data link scheduling module, and various data frames from the receiving port are stored in a corresponding storage body in cooperation with the mixed data scheduling module. The high two bits of the memory address bus are used for dividing the memory spaces of time trigger data frames, event trigger data frames and other data frames. The data link scheduling module analyzes the data frame description information and temporarily stores the data frame into a corresponding storage space.

The specific process of data processing of the time-triggered switch is as follows:

1. the receiving port module receives the Ethernet data frames from other terminal nodes and analyzes and receives the data frames. If the Ethernet data frame is ARP type, storing the source MAC address into the MAC address module and binding the source port; and if the Ethernet data frame is of other types, inquiring the MAC address module according to the destination MAC address to obtain the data forwarding destination port. And no matter what the data type is, caching the Ethernet data frame of the receiving port module into a data caching module RX_RAM in the receiving port module, recording the storage start address, the data length, the destination port number and the data type information of the Ethernet data frame, and delivering the data frame to a data link scheduling module for processing.

2. And the data link scheduling module transmits the corresponding data frames to the mixed data scheduling module from the buffer memory according to the type of the Ethernet data frames and the forwarding destination port. Parameters of the description information such as a destination port number, a data length and a storage start address of the Ethernet data frame are stored in a data descriptor buffer module.

3. And the data link transmission control module transmits the data from the mixed data scheduling module to the transmission port module according to the transmission sequence of the TT data frame, the ET data frame and other data frames according to the information of the descriptor. The module designs a TT data frame preemption other data frame sending mechanism, and resends the preempted data frame after the TT data frame is sent.

4. The transmitting port module transmits the data transmitted from the data link transmission control module to the terminal node, and in addition, in the module, in order to ensure time synchronization of the time triggered communication system, the time synchronization data frame is transmitted every 10ms, the time synchronization data frame preempts all other data frames for transmission, and then the preempted data frame is retransmitted.

In some embodiments, the receiving port module in the MAC layer module includes:

Specifically, as shown in fig. 2, the structure of the receiving port module is composed of a receiving processing module mac_rx, a data buffer module rx_ram, a data frame information buffer module rx_fifo, a MAC address inquiry module search, a source MAC address buffer module src_fifo, and a CRC calculation module rx_crc.

The Ethernet data is received and processed in the receiving and processing module mac_rx according to the Ethernet data frame protocol, the data to be checked is transmitted to the computing module RX_CRC, after the CRC check code is computed, the data is returned to the receiving and processing module mac_rx, and whether the data frame is transmitted error is judged by comparing the computed check code with the check code in the data frame. The address inquiry module search receives the destination MAC address transmitted by the receiving and processing module mac_rx, inquires a destination port number, and the destination port number is used for judging that one frame of Ethernet data is forwarded from a certain port of the switch. The address buffer module src_fifo receives the source MAC address from the receiving processing module mac_rx, which is used to complete clock domain isolation and temporary store the MAC address for binding the MAC address and the switch port number. The data caching module RX_RAM is responsible for caching a complete Ethernet data frame; the data frame information buffer module rx_fifo is responsible for buffering descriptors, which are information of length, storage start address, type and destination port number of the data frame stored in the data buffer module rx_ram.

The receiving processing module mac_rx extracts the destination MAC address, the source MAC address and the frame type information in the ethernet header according to the ethernet frame format, wherein the frame type is a field for distinguishing the ethernet data frame, and corresponding exchange processing is performed according to different frame types, and in the universal ethernet protocol, the ethernet data frame type comprises an IP protocol frame (frame type is 0x 0800) and an ARP (frame type is 0x 0806) protocol frame. In the time triggered Ethernet switch, two definition frames are added, namely TT data protocol frames, and the type field is 0x0808; the time sync data frame has a type field of 0x8888. The destination MAC address is transmitted to an address inquiry module search, the destination port of the data frame forwarding is inquired, and the destination port number is transmitted to a receiving processing module mac_rx for analysis processing; the source MAC address judges whether the source MAC address is given to the MAC address learning module according to the frame type field, if the source MAC address is an ARP protocol frame, the source MAC address and the receiving port number are bound, and the MAC address learning module records information to the MAC address module.

The address inquiry module search inquires a port number corresponding to a destination MAC address by accessing information in an address table, and outputs the port number to the receiving and processing module mac_rx to complete the destination MAC address inquiry function. If the corresponding port number is not obtained yet after a round of access is performed on the whole space of the address table during the query, the receiving port module needs to be informed that the data frame should be broadcasted; when the destination MAC address is a broadcast address, indicating that the received data frame is a broadcast data frame; to sum up, both frames are broadcast, and the broadcast port number is output to the receiving processing module mac_rx. A handshake signal is given to the receiving processing module mac_rx while the port number is being transported, indicating that the MAC address lookup is complete.

In some embodiments, the number of transmit port modules and receive port modules in the MAC layer module is set to 8; the 8 transmitting port modules correspond to the transmitting port module 1to the starting port module 8 in fig. 1, respectively; the 8 receiving port modules correspond to the receiving port module 1to the receiving port module 8 in fig. 1, respectively;

the number of the data link scheduling modules and the number of the data link transmission control modules are set to 8;

the input end of the mixed data scheduling module is connected with 8 receiving port modules in the MAC layer module through 8 data link scheduling modules;

the output end of the mixed data scheduling module is connected with 8 sending port modules in the MAC layer module through 8 data link sending control modules.

In some embodiments, the transmit port module in the MAC layer module includes:

Specifically, as shown in fig. 3, the configuration of the transmission port module is divided into a transmission processing module mac_tx, a data buffer module tx_ram, a descriptor module tx_fifo, and a CRC calculation module tx_crc.

The data buffer module TX_RAM and the descriptor module TX_FIFO receive the data transmitted from the data link transmission control module; the transmission processing module mac_tx parses the data frame information obtained from the descriptor module tx_fifo and transmits the data frame of the data buffer module tx_ram to the terminal.

The time synchronization data frame performs preemptive transmission on other data, the transmission processing module mac_tx encapsulates the time stamp timestamp, simultaneously records descriptor information of the preempted data frame, transmits data to be checked to the calculation module TX_CRC for calculation, and transmits the generated check code to the transmission processing module mac_tx for transmission. And after the time synchronization data frames are sent, the data frames which are preempted are read and sent from the data buffer module TX_RAM again according to the recorded descriptor information.

In some embodiments, in the forwarding process, if the time synchronization frame collides with the transmission of other data frames, the transmission port module in the MAC layer module performs preemptive transmission on the time synchronization frame, and retransmits the preempted data frame after the transmission is completed, so as to ensure global clock synchronization;

the transmitting port module and the receiving port module in the MAC layer module adopt an Ethernet communication clock of 125MHz, the receiving processing module mac_rx and the transmitting processing module mac_tx adopt 200MHz clocks, and a true dual-port RAM structure is adopted between the two clock domains of 125MHz clocks and 200MHz clocks to realize interaction so as to reduce the forwarding processing delay of the time-triggered switch.

In some embodiments, the MAC address module comprises:

the 8 first RAM blocks are connected with the output end of the MAC address writing control module, the 8 first RAM blocks are provided with an A port and a B port, the A port is used for learning and accessing an address table, and the B port is used for inquiring the address.

In some embodiments, the 8 first RAM blocks are respectively bound with the 8 receiving port modules, when the first RAM blocks receive the destination MAC address from the receiving port modules, the first RAM blocks perform traversal inquiry access to the address table, and unicast, multicast and broadcast forwarding of the data frame are implemented according to the inquired port number;

Specifically, the maclut module is a MAC address module, whose address table information is shown in table 1, where the data width of the first RAM block is set to 52 bits, the upper 48 bits are MAC addresses, and the lower 4 bits are switch port numbers, for matching the MAC addresses and ports. The address bus bit width of the first RAM block is set to 6, i.e. the entire switch can learn to record 64 MAC addresses. The number of MAC address storage can be appropriately enlarged according to the application.

Table 1 address table mapping

The structure of the MAC_LUT module is shown in fig. 4, and the working clock adopts 200Mhz, so that the access processing speed of the address table is improved. An address table is represented by a first RAM block whose a port is used for learning access to the address table and whose B port is used for address lookup. To satisfy 8 ports of the switch for simultaneous address lookup access, 8 identically configured first RAM blocks are used for address table management. The address inquiry module search of each receiving port module of the switch inquires the address table corresponding to each port and gives the obtained port information data to the inquiry module for processing. When learning MAC addresses, MAC addresses and port information are written into the 8 first RAM blocks at the same time, and the MAC addresses and port information in the figure are branched and connected to the 8 first RAM blocks, so that all address tables are ensured to be in an information synchronization state. The MAC address writing module uniformly controls the input of the MAC address and the port information, and whether the MAC address and the port information exist in an address table or not is required before the input. The MAC address writing control module (corresponding to the MAC address writing control in fig. 4) accesses the address table information through the a ports of the 8 first RAM blocks, and when the 8 read address table information data are consistent, performs MAC address repetition judgment, if the address and the port are repeated, the MAC address and the port information are not written, otherwise, the related information is written. When the address table information data are inconsistent, the MAC address and port information are directly written into all address tables.

Specifically, the data link scheduling module is responsible for reading data frame information in the data frame information caching module rx_fifo in the receiving port module, and according to the data frame length, the storage start address, the type and the destination port, performing link selection on ethernet data frames corresponding to the information of the data caching module rx_ram, storing the ethernet data frames in the hybrid data scheduling module, recording the data frame storage start address and the descriptor information, and storing the data frame storage start address and the descriptor information in the descriptor caching module.

In some embodiments, the hybrid data scheduling module comprises:

the input ends of the 8 condition judgment logic modules CL are respectively connected with the 8 data link scheduling modules;

the 64 true dual-port RAMs are divided into 8 groups in total, each group of 8 true dual-port RAMs is orderly sequenced from 1to 8, the output ends of the 8 condition judgment logic modules CL are respectively connected with the 8 groups of true dual-port RAMs, and the 8 condition judgment logic modules CL are used for respectively controlling the 8 data link scheduling modules so as to write the data of the 8 data link scheduling modules into the corresponding true dual-port RAMs;

and 8 selection link logic modules SL for controlling the data output of the 64 true dual-port RAM transmitting ports, wherein 8 selection link logic modules SL are sequentially ordered from 1to 8, and the input ends of the 8 selection link logic modules SL are respectively connected with the true dual-port RAM with the same serial number of the transmitting port module.

In some embodiments, the true dual port RAM is divided into three storage spaces, which are respectively an ET data storage address field, a TT data storage address field, and an OF other data frame data storage address field, where the ET data field address range is 0 to 0x7fff, the TT data field address range is 0x8000 to 0xbfff, and the bf data field address range is 0xc000 to 0xffff.

Specifically, the hybrid data scheduling module manages the storage of different types of data frames from different ports, the structure of which is shown in fig. 5. The (Time-Trigger Ethernet, TTE) Time triggered switch is designed with 8 ports, namely 8 transmit port modules and 8 receive port modules, in which 64 true dual port RAMs are used for cache management of data. Data received by one switch port may be forwarded to 8 ports (including its local port), and one switch port may send data forwarded by 8 ports. Data is written into the port A of the true dual-port RAM, and the data is read out from the port B. Before data is written into the true dual-port RAM, a condition judgment logic module CL is used for controlling a data link scheduling module N (N is 1,2,3, … and 8) to write the data link into the corresponding true dual-port RAM; the data are read from the true dual port RAM and the data output of the transmit port module is controlled by the select link logic module SL. Every time a port is added to the switch, a true dual-port RAM is added to the module to complete port function expansion.

Each real dual-port RAM in the ram_matrix module can buffer 64KB of data, and the real dual-port RAM is divided into three storage spaces according to the data frame type. As shown in fig. 6, the memory space is divided into an ET data memory address field, a TT data memory address field, and an OF (other data frame) data memory address field, the ET data field address range is 0 to 0x7fff, the TT data field address range is 0x8000 to 0xbfff, and the bf data field address range is 0xc000 to 0xffff. The write address bus width is 16 bits, the address OF the storage data frame type address segment is distinguished by the address higher by 2 bits, 2'b00 and 2' b01 denote ET data storage address segments, 2'b10 denote TT data storage address segments, and 2' b11 denote OF data storage address segments. The lower 14-bit address bus represents the write address of the data. The address bus signal and the destination port signal are processed by the condition judgment logic module CL, and the control data frame is written into the corresponding real dual-port RAM. The selective link logic module SL receives the read signal of the data link transmission control module and controls the data reading and forwarding of each real dual-port RAM.

Specifically, the data link transmission control module is responsible for deciding the forwarding of the data frame in the hybrid data buffer module. When a data request is sent to a certain port in the descriptor cache module, information in the descriptor cache module is read, and after analysis, a data frame corresponding to the descriptor information in the mixed data cache module is read. In order to ensure the real-time property of TT data frame transmission, when the TT data frame has a transmission requirement, a channel is occupied by ET data frame transmission, the TT data frame is required to be subjected to preemption treatment, the transmission of the TT data frame is processed, and the preempted ET data frame is restarted to be retransmitted.

Specifically, the time synchronization control module is applied to a time synchronization function. The method generates local time stamp information of a switch and adopts a master-slave synchronization method to perform time synchronization. And sending time synchronization data frames outwards from all ports of the switch every 10ms period, performing time synchronization on terminal nodes in other time-triggered Ethernet, and performing periodic data communication according to time information by the synchronized time-triggered Ethernet system. The time synchronization control module realizes the generation of the local time stamp of the switch and controls the sending time of the time synchronization frame, and packages the time stamp into the time synchronization frame in the sending processing module mac_tx and sends the time synchronization frame.

In some embodiments, the descriptor caching module comprises:

128 FIFOs, the input ends of which are connected with the output ends of the write-in control combination logic module (corresponding to the write-in control combination logic in fig. 7), wherein the write-in control combination logic module is used for storing the initial address and the data length information of the data frames stored in the mixed data scheduling module into the corresponding FIFOs;

the input ends of the read-out control combination logic module (corresponding to the read-out control combination logic in fig. 7) are respectively connected with the output ends of the 128 FIFOs, and are responsible for selecting the route and outputting to the data link transmission control module for processing.

Specifically, the descriptor cache module des_fifo is composed of 128 FIFOs, and the structure is shown in fig. 7. Its FIFO designation takes the form OF et_1to2, representing either an ET data frame or an OF frame sent from port 1to port 2, tt_2to3 representing a TT data frame sent from port 2to port 3. The descriptor buffer module is used for resolving the descriptor transmitted by the data link scheduling module through the write-in control combination logic, and storing the initial address and the data length information of the data frame stored in the mixed data scheduling module into the corresponding FIFO. The empty signal of the FIFO triggers the lower module to start working, the descriptor FIFO of the module is subjected to data reading, and the data read by the FIFO is output to the data link transmission control module for processing through the output combination logic circuit for selecting a route. Through the combination logic management of the modules, the connection lines between the modules are reduced, and the multiplexing rate of the input and output buses is improved.

Compared with a commercial switch, the time trigger switch with the expandable port can forward time trigger data and other data, can realize the preemption of the time trigger data, can be used as a main node in time synchronization, and can realize the global time synchronization of a time trigger communication system. The time trigger switch is designed by combining the FPGA resource structure characteristics, so that the complexity of the time trigger switch is effectively reduced.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Moreover, the technical solutions of the embodiments of the present invention may be combined with each other, but it is necessary to be based on the fact that those skilled in the art can implement the embodiments, and when the technical solutions are contradictory or cannot be implemented, it should be considered that the combination of the technical solutions does not exist, and is not within the scope of protection claimed by the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A time triggered switch for an extensible port, comprising:

the MAC address module is connected with the receiving port module and is responsible for recording the corresponding relation between the MAC address and the port and finishing the address writing and inquiring functions;

2. The time triggered switch of claim 1, wherein the receive port module in the MAC layer module comprises:

3. The time triggered switch of claim 2, wherein the transmit port module in the MAC layer module comprises:

4. A time triggered switch as claimed in claim 3, wherein the transmission port module in the MAC layer module performs preemptive transmission if the time synchronization frame collides with other data frame transmission during the forwarding process, and retransmits the preempted data frame after the transmission is completed to ensure global clock synchronization;

5. The time triggered switch of claim 1, wherein the MAC address module comprises:

n first RAM blocks are connected with the output end of the MAC address writing control module, each of the N first RAM blocks is provided with an A port and a B port, the A port is used for learning and accessing an address table, and the B port is used for inquiring the address.

6. The time triggered switch of claim 5, wherein the number of transmit port modules and receive port modules in the MAC layer module is set to N;

7. The time triggered switch of claim 6, wherein N first RAM blocks are respectively bound to N receiving port modules, and when the first RAM blocks receive a destination MAC address from a receiving port module, traversing the address table for query access, and implementing unicast, multicast, and broadcast forwarding of the data frame according to the queried port number;

8. The time triggered switch of claim 6, wherein the hybrid data scheduling module comprises:

9. The time triggered switch OF claim 8, wherein the true dual port RAM is divided into three memory spaces, an ET data memory address field, a TT data memory address field, and an OF other data frame data memory address field, respectively, the ET data field address range is 0-0 x7fff, the TT data field address range is 0x 8000-0 xbfff, and the bf data field address range is 0xc 000-0 xffff.

10. The time triggered switch of claim 1, wherein the descriptor caching module comprises: