CN102798582A - Proportional photon correlator based on digital signal processor (DSP) annular buffer area - Google Patents

Proportional photon correlator based on digital signal processor (DSP) annular buffer area Download PDF

Info

Publication number
CN102798582A
CN102798582A CN2012101601571A CN201210160157A CN102798582A CN 102798582 A CN102798582 A CN 102798582A CN 2012101601571 A CN2012101601571 A CN 2012101601571A CN 201210160157 A CN201210160157 A CN 201210160157A CN 102798582 A CN102798582 A CN 102798582A
Authority
CN
China
Prior art keywords
photon
chip circuit
module
dsp
buffer circle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2012101601571A
Other languages
Chinese (zh)
Inventor
刘伟
陆文玲
申晋
王雅静
谭博学
孙贤明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong University of Technology
Original Assignee
Shandong University of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shandong University of Technology filed Critical Shandong University of Technology
Priority to CN2012101601571A priority Critical patent/CN102798582A/en
Publication of CN102798582A publication Critical patent/CN102798582A/en
Pending legal-status Critical Current

Links

Images

Abstract

The invention relates to the technical field of photon correlation spectroscopy granulometry, in particular to a photon correlator. A proportional photon correlator based on a digital signal processor (DSP) annular buffer area comprises a field programmable gate array (FPGA) chip circuit, a DSP chip circuit and a computer, wherein the DSP chip circuit is respectively connected with the FPGA chip circuit and the computer; the FPGA chip circuit comprises a sampling time setting module, a reset module and a photon counting module; and the DSP chip circuit comprises a correlation channel delay time computation module, an annular buffer area and a correlation operation module. By adoption of the technical scheme, a DSP and an FPGA chip are combined together, the size of the correlator is reduced, and the cost of the correlator is reduced.

Description

Ratio photon correlator based on the DSP buffer circle
Technical field
The present invention relates to photon correlation spectroscopy method granulometry technical field, be specifically related to a kind of photon correlator.
Background technology
In the suspending liquid of sub-micron and nano particle, particle is among the motion that does not stop owing to carrying out the continuous bump of the fluid molecule of Brownian movement around receiving, and particle is more little, and motion Shaoxing opera is strong.This motion makes particle scattering light frequency produce Doppler shift with respect to incident light; Show as under certain scattering angle; Scattered light intensity is fluctuation constantly in time; This coherence stack by the scattering light field that each particle sends causes, and the dynamic fluctuation situation of this scattered light is called dynamic light scattering, and photon correlation spectroscopy particle sizing method is obtained particle grain size and distributed intelligence thereof through studying this wave phenomenon.
Photon correlation spectroscopy method nano particles measurement mechanism is as shown in Figure 1, and measurement mechanism is made up of input path and measurement light path.Input path is made up of laser instrument 11, attenuator 12 and condenser lens 13, and the incident light that laser instrument 11 sends passes attenuator 12, through behind the condenser lens 13, shines on the particulate samples of sample cell 14.Measure light path and mainly be made up of aperture 15, photomultiplier 16 and photon correlator 17, irradiated particle produces scattered light, and scattered light gets into photomultiplier 16 through small holes 15.The effect of aperture 15 is to guarantee the scattered light of reception from coherence area, the parasitic light around removing simultaneously.Scattered light is received by photomultiplier 16, and signal amplification and amplitude discriminator through subsequent conditioning circuit become the constant amplitude pulse signal.These pulse signals are admitted to photon correlator 17, in photon correlator 17, accomplish counting and multiply accumulating operation, obtain autocorrelation function.Utilize the size-grade distribution inversion algorithm at last, calculate particle grain size and distribution thereof by computing machine 18.
In the experiment of photon correlation spectroscopy particle sizing, photon correlator 17 needs enough big dynamic range, just can make autocorrelation function decay to baseline, obtains stable measurement result.Dynamic range is defined as τ l/ τ, wherein, τ is the time delay of first passage, τ lBe the time delay of last passage.For the linear dependence device, increase with linear rule interchannel time delay, and be the time delay of k linear passageway so: τ k=k τ, the corresponding linear dependence passage of each k value.The dynamic range of linear dependence device equates with port number, when the dynamic range of needs is big, will need the related channel program of equal number, and this is difficult to realize on hardware designs.If will reach required great dynamic range with limited related channel program, then must reduce SF, in the lengthening sampling time, cause temporal resolution to descend greatly.
The light intensity autocorrelation function is a curve by the index law decay; Different delay time has the different time resolution requirement to correlation curve, promptly needs short time delay at the initial several interchannels of correlator; To keep time enough resolution; And after curve decayed to baseline, the interchannel delay time will prolong as far as possible, to guarantee the enough dynamic ranges of correlator.The linear dependence device is with related channel program mean allocation time delay, and correlation curve changes slow part and causes the channel resource waste, and correlation curve is decayed fast and partly received the port number quantitative limitation, and temporal resolution is not high.Therefore, can adopt the ratio correlator, the ratio correlator has changed the rule of interchannel delay time by linear increment, makes it proportionally to concern τ k=τ R K-1Increase progressively; In the formula, R is the adjacency channel ratio of time delay, increases according to linear rule in the The initial segment of related function; Increasing along with the related channel program sequence number; Increase interchannel time delay according to a certain percentage, reached bigger dynamic range with limited related channel program, and the The initial segment at correlation curve is keeping higher temporal resolution simultaneously.
But owing to can't confirm channel delay time of ratio correlator in advance, make and the difficult problem that is designed to of photon count value delay cell hindered the realization of ratio photon correlator.
Summary of the invention
The objective of the invention is to, the ratio photon correlator based on the DSP buffer circle is provided, solve above technical matters.
The technical matters that the present invention solved can adopt following technical scheme to realize:
Ratio photon correlator based on the DSP buffer circle is characterized in that, comprises a fpga chip circuit, a dsp chip circuit, a computing machine, and said dsp chip circuit connects said fpga chip circuit, said computing machine respectively;
Said fpga chip circuit comprises that a sampling time is provided with module, a reseting module, a photon counting module;
Said dsp chip circuit comprises related channel program computing module time delay, a buffer circle, a related operation module;
Said fpga chip circuit produces sampled clock signal, and photon pulse is counted;
Said dsp chip circuit is realized the function of shift register through said buffer circle; According to the adjacency channel ratio R of time delay; The delay time of each passage is set, and, realizes the computing of related function through said related operation module; And sending related function to said computing machine, said computing machine obtains the size-grade distribution of particle through inversion algorithm.
Sampling time module of the present invention is provided with the SI; The photon counting module realizes the counting to photomultiplier constant amplitude photon pulse signal; And count value is transferred to the related operation module, the related operation module is carried out the multiply accumulating computing to photon count value, obtains the correlation function value of each passage; Then the result is sent to computing machine, utilize inversion algorithm to calculate grain graininess and distribution thereof.The present invention is based on DSP and fpga chip circuit; Utilize buffer circle realization ratio passage related operation in the dsp chip circuit; Use less passage to realize bigger dynamic range, satisfy the demand of nanometer and submicron particles granulometry fully, reduced the cost of photon correlator.
The said sampling time is provided with module and comprises code translator, trigger, counter and comparer; The said sampling time is provided with module through the system clock frequency division is obtained sampled clock signal: the system clock frequency that the sampling clock frequency equals to import is divided by divide ratio; Said computing machine calculates divide ratio according to user's setting; And send to the dsp chip circuit; The dsp chip circuit is provided with module with the sampling time that divide ratio writes the fpga chip inside circuit again, through counter system clock is counted, and is compared with divide ratio; Realization is to the frequency division of system clock, the sampled clock signal that can obtain expecting.
Said reseting module comprises code translator and trigger, and said reseting module is used to produce systematic reset signal, when reset signal is high level, empties the count value of said photon counting module; When reset signal was low level, said photon counting module was counted photon pulse.
Said photon counting module comprises two counters, two latchs and multi-channel data selector; Under the driving of sampled clock signal, two said counter alternate runs are realized exporting to said dsp chip circuit to the seamless counting of photon pulse and with count results.
Said related channel program computing module time delay in the said dsp chip circuit is dynamic range and the port number that utilizes photon correlator, calculates the adjacency channel ratio R of time delay, then according to τ k=τ R K-1Calculate the time delay of each passage, τ is the time delay of the 1st passage.
Said buffer circle in the said dsp chip circuit has been realized the function of shift register, and said dsp chip circuit deposits said buffer circle in after reading the photon count value of said photon counting module output; The capacity of buffer circle is L, deposits the 0th photon count value n (0) in from the start element of buffer circle, and subsequent count values deposits the follow-up unit of buffer circle successively in; When count value is increased to n (L-1); Buffer circle is filled with, and next count value n (L) deposits the start element of storage n (0) in, and count value n (0) is override; By that analogy, realize circulation.
Said related operation module in the said dsp chip circuit according to the said related channel program computing module time delay precalculated channel delay time, is extracted the photon count value of corresponding units storage in the said buffer circle; Utilize hardware multiplier; Carry out multiplying with the New count value, add up again, obtain the correlation function value of each passage; And convert the result to 32 floating-point format numbers; Be transferred to said computing machine through USB interface, said computing machine obtains the size-grade distribution of particle through inversion algorithm.
Said related operation module is the core of photon correlator, and the function that it is realized is that the photon count value of photon counting module output is carried out real-time auto-correlation computation.The ultimate principle of preceding k passage auto-correlation computation is following:
First passage: G (τ)=n 0n 1+ n 1n 2+ ... + n N-1n N
Second channel: G (2 τ)=n 0n 2+ n 1n 3+ ... + n N-2n N
Third channel: G (3 τ)=n 0n 3+ n 1n 4+ ... + n N-3n N
Four-way: G (4 τ)=n 0n 4+ n 1n 5+ ... + n N-4n N
The k passage: G ( Kτ ) = Σ i = 0 N - k n i n i + k
Each passage auto-correlation computation of the present invention is realized according to above-mentioned ultimate principle.
The basic functional principle of photon correlator is following: in photon correlation spectroscopy method nano particles measurement mechanism, also comprise photomultiplier, amplifying circuit, discriminator circuit usually; At first said photomultiplier converts the scattered light signal that receives into constant amplitude photon pulse signal; Utilize said amplifying circuit to amplify then; Send into the counter of said photon counting module after screening through discriminator circuit again; Said counter is counted the photon pulse in the sampling time, sends into shift register then.Buffer circle among the present invention is as shift register.After sampling is accomplished each time; Under the control of sampled clock signal; Counter is sent count results into the first order of shift register, and when the rising edge of next sampling clock arrived, the original content of the shift register first order was moved into the second level; The original content in the second level is moved into the third level, by that analogy.The content of shift register moves to right under the control of sampling clock successively in proper order, has formed the count value of different time delays, and each grade shift register is equivalent to a linear passageway of correlator.Between sampling period, current count value n iWith k channel counts value n I+kMultiply each other, the storer of then multiplied result being sent into the k passage adds up, and the accumulated value that obtains is auto-correlation function value G (k τ).
Beneficial effect: the present invention compared with prior art has the following advantages:
1) related operation module of the present invention adopts buffer circle to realize the function of shift register, and can be set flexibly the time delay of required ratio passage, realizes the design of ratio photon correlator with lower hardware cost;
2) the present invention can select linear passageway or ratio channel algorithm according to different measuring requirements.During employing ratio related algorithm, under the situation of limited passage, both can guarantee that related function had sufficiently high temporal resolution, can obtain enough big dynamic range again;
3) photon counting module of the present invention adopts fpga chip to realize, has realized seamless counting through two photon counter alternations, has guaranteed the accuracy of photon counting;
4) the present invention is based on dsp chip, realize the calculating of related function, can under the prerequisite that does not change hardware, optimize related algorithm, improve the extendability of system;
5) the present invention combines DSP and fpga chip, has dwindled the volume of correlator, has reduced the cost of correlator.
Description of drawings
Fig. 1 is a photon correlation spectroscopy method nano particles measurement mechanism block diagram;
Fig. 2 is the structural representation of photon correlator of the present invention;
Fig. 3 connects synoptic diagram for the integrated circuit of photon correlator of the present invention;
Fig. 4 is provided with the structural representation of module for the sampling time of the present invention;
Fig. 5 is the structural representation of reseting module of the present invention;
Fig. 6 is the structural representation of photon counting module of the present invention;
Fig. 7 is the schematic diagram of related operation module of the present invention;
Fig. 8 is a related channel program delay time calculation flow chart of the present invention;
Fig. 9 is a related function calculation flow chart of the present invention.
Embodiment
For technological means, creation characteristic that the present invention is realized, reach purpose and effect and be easy to understand and understand, further set forth the present invention below in conjunction with concrete diagram.
With reference to Fig. 2, Fig. 3, based on the ratio photon correlator of DSP buffer circle, comprise fpga chip circuit, dsp chip circuit, computer PC, the dsp chip circuit connects fpga chip circuit, computer PC respectively.The fpga chip circuit comprises that the sampling time is provided with module SampleTime, reseting module Reset, photon counting module Counter.The dsp chip circuit comprises related channel program computing module time delay, buffer circle, related operation module.The fpga chip circuit produces sampled clock signal, and photon pulse is counted.The dsp chip circuit is realized the function of shift register through buffer circle; According to the adjacency channel ratio R of time delay; The delay time of each passage is set, and, realizes the computing of related function through the related operation module; And sending related function to computer PC, computer PC obtains the size-grade distribution of particle through inversion algorithm.
With reference to Fig. 2; In photon correlation spectroscopy method nano particles measurement mechanism, also comprise photomultiplier, amplifying circuit, discriminator circuit usually; At first photomultiplier converts the scattered light signal that receives into constant amplitude photon pulse signal, utilizes amplifying circuit to amplify then, sends into the counter of photon counting module Counter after screening through discriminator circuit again; Counter is counted the photon pulse in the sampling time, sends into shift register then.Buffer circle among the present invention is as shift register.After sampling is accomplished each time; Under the control of sampled clock signal; Counter is sent count results into the first order of shift register, and when the rising edge of next sampling clock arrived, the original content of the shift register first order was moved into the second level; The original content in the second level is moved into the third level, by that analogy; The content of shift register moves to right under the control of sampling clock successively in proper order, has formed the count value of different time delays, and each grade shift register is equivalent to a linear passageway of correlator.Between sampling period, current count value n iWith k channel counts value n I+kMultiply each other, the storer of then multiplied result being sent into the k passage adds up, and the accumulated value that obtains is auto-correlation function value G (k τ).
With reference to Fig. 4, the sampling time in the fpga chip circuit is provided with module SampleTime through to clock signal of system CLK_SYS frequency division, obtains sampled clock signal CLK, and inserts photon counting module Counter.Photon pulse is by CIN pin input photon counting module Counter.The reset signal CLR of the reseting module Reset output in the fpga chip circuit is connected to photon counting module Counter; When CLR is low level; Under the driving of sampled clock signal CLK, photon counting module Counter counts photon pulse, and count value is exported; When CLR is high level, empty the count value of photon counting module.
With reference to Fig. 3, sampled clock signal CLK inserts the external interrupt pin EXINT of dsp chip circuit simultaneously, in the rising edge triggering dsp chip circuit interruption of CLK.The dsp chip circuit reads the count value of photon counting module Counter in interrupt function; Count value is write buffer circle, and, read the count value of buffer circle corresponding units storage according to each channel delay time that related channel program computing module time delay calculates; Hardware multiplier by the dsp chip circuit is accomplished multiplying; Add up again, obtain correlation function value, accomplish the related operation of each passage.The dsp chip circuit is connected with the fpga chip circuit through parallel interface, realizes the read-write control to the fpga chip circuit.ECE is the outside chip selection signal of dsp chip circuit, and EAWE and EARE are the read-write control signal of dsp chip circuit, and EA [21:0] is the address wire of dsp chip circuit, and ED [15:0] is the data line of dsp chip circuit.The dsp chip circuit is transferred to computer PC through USB interface with the correlation function value of each passage.
Each module of the present invention specifically comprises following device:
1) with reference to Fig. 4, the sampling time is provided with module SampleTime and comprises code translator Decoder, trigger FD, counter COUNT and comparator C omparator.According to predefined address; Produce chip selection signal ctl_div by code translator Decoder; Insert the input end of clock mouth C of trigger FD, at the rising edge of signal ctl_div, the dsp chip circuit writes trigger FD through data line ED [15:0] with divide ratio; Divide ratio inserts the input end B [15:0] of comparator C omparator through output port DIV [15:0] output.Counter COUNT counts clock signal of system CLK_SYS, and count results inserts the input end A [15:0] of comparator C omparator through output port Q [15:0] output.Comparator C omparator compares the numerical value of input end A [15:0] and B [15:0]; If unequal, then exporting signal EQ is low level, and this signal inserts the Enable Pin CE of trigger FD; Forbidding trigger FD; Output signal EQ inserts the clear terminal CLR of counter COUNT simultaneously, because EQ is a low level, counter COUNT continues counting.If equate that then exporting signal EQ is high level, enables trigger FD, under the triggering of system clock CLK_SYS rising edge, the output signal CLK level of trigger FD reverses, and empties counter COUNT simultaneously, counter is started from scratch count again.So periodic duty can obtain the sampled clock signal CLK of setpoint frequency.
2) with reference to Fig. 5, reseting module Reset comprises code translator Decoder and trigger FDR.According to predefined address; Produce chip selection signal ctl_clr by code translator Decoder; Insert the input end of clock mouth C of trigger FDR, at the rising edge of signal ctl_clr, the dsp chip circuit writes trigger FDR through data line ED [15:0] with data; Data are systematic reset signal CLR through output port Q output.When the dsp chip circuit passed through data line ED [15:0] write data 0, reset signal CLR became low level, and photon counting module Counter counts photon pulse.During write data 1, reset signal CLR becomes high level.Empty the count value of photon counting module Counter.
3) with reference to Fig. 6, photon counting module Counter comprises counter Counter1, counter Counter2, latch Latch1, latch Latch2, multi-channel data selector MUX2.Sampled clock signal CLK obtains clock signal clk 2 through behind the two divided-frequency; Be connected to the counting Enable Pin CE of counter Counter1, the input end of clock CLK of latch Latch2 and the selection input end S of multi-channel data selector MUX2, clock signal clk 2 is connected to the input end of clock CLK that counter Counter2 counts Enable Pin CE and latch Latch1 after connecing phase inverter.The photon pulse signal is sent into the pulse input end C of counter Counter1 and Counter2 simultaneously from input end CIN; Reset signal CLR is connected to the reset terminal CLR of counter Counter1 and Counter2, and reset signal CLR meets the reset terminal CLR that is connected to latch Latch1 and Latch2 behind the phase inverter.When reset signal CLR is a low level, when clock signal clk 2 was high level, counter Counter1 began the photon pulse signal is counted; When clock signal CLK2 was low level, counter Counter1 stopped counting, and count value latchs output by Latch1, and counter Counter2 begins the photon pulse signal is counted.When the reset terminal of counter Counter1 is high level, remove the count value of counter Counter1, restart counting when clock signal clk 2 becomes high level by the time again, so the cycle carries out.Counter Counter1 and Counter2 alternately count the photon pulse of input, after count results process latch Latch1 and Latch2 latch, through output port Q [15:0] output of multi-channel data selector MUX2.Counter Counter1 and Counter2 are 16 digit counters, and with the 1Mcps light intensity, the maximum 40ms sampling time is an example, the average photon count value be 40000 (<2 16), so counter can not overflow.
4) with reference to Fig. 2, Fig. 3, the time delay that related channel program computing module time delay is responsible for calculating each passage.The ratio correlator is pressed linear rule in the The initial segment interchannel delay time of related function and is increased, and with the increasing of related channel program sequence number, increase interchannel time delay by a certain percentage.According to the time delay of the dynamic range of setting and each passage of related channel program number calculating; Set some passage according to result of calculation and be connected with multiplier and totalizer; Other passages then do not connect multiplier and totalizer, thereby become the correlator configuration of extracting at interval in proportion.Therefore, before the related operation, at first need utilize the dynamic range and the port number N of setting, according to computes ratio R:
R = exp [ ln ( &tau; 1 / &tau; ) N - 1 ]
Then be the time delay of ratio correlator k passage: τ k=τ R K-1
But the channel delay time of calculating according to following formula in most cases is not integer; Need round it, this realizes than being easier under the bigger situation of R value, when R value than hour; The channel delay time of adopting following formula to calculate can produce repetition, and actual port number is less than the port number of setting.To this situation, can adopt the as shown in Figure 8 compute channel method of time delay, both can guarantee required port number, can obtain the desirable channel delay time again.
With reference to Fig. 8, τ is the time delay of first passage, τ lBe the time delay of last passage, the related channel program number of N for setting, L is the length of buffer circle n [], and j is the port number after merging, and result of calculation leaves among the memory block ChDelay [].
For example: set τ=20 μ s, τ l=100000 μ s, during N=64, ratio R=1.1448 then, the dynamic range of realization is 5 * 10 3, the delay that obtains passage is as shown in the table, and be τ the time delay of each passage so k=τ ChDelay [k].
Figure BDA00001668294200092
Can find out from last table; The ratio correlator channel delay time increases according to linear rule at the initial period of related function; Increase along with the related channel program sequence number; Begin to increase according to a certain percentage interchannel time delay, realized bigger dynamic range with limited port number, and the initial period at correlation curve is keeping higher temporal resolution simultaneously.
5) with reference to Fig. 7, in the rising edge triggering dsp chip circuit interruption of sampled clock signal CLK, in interrupt function; The dsp chip circuit reads the photon count value of photon counting module Counter output in the FPGA, deposits in the buffer circle n [] of dsp chip circuit, and the capacity of buffer circle is L; Deposit initial photon count value n (0) in from the start element of buffer circle; Subsequent count values deposits the follow-up unit n (k) of buffer circle successively in, and when count value was increased to n (L-1), buffer circle was filled with; Next count value n (L) deposits the start element of storage n (0) in, and count value n (0) is override.By that analogy, constantly circulation, the buffer circle in the DSP has been realized the function of shift register.
6) with reference to Fig. 7, Fig. 9; Rising edge at sampled clock signal CLK triggers the dsp chip circuit interruption, in interrupt function, after the dsp chip circuit reads in new photon count value; According to related channel program each channel delay time that time delay, computing module calculated in the dsp chip circuit; In buffer circle, extract the photon count value of having stored, utilize the hardware multiplier of dsp chip circuit, carry out multiplication mutually with new photon count value; Add up again, obtain the correlation function value of each passage.
Ultimate principle according to above-mentioned related operation; The related function calculation process is as shown in Figure 9, the related channel program number of N for setting among the figure, and L is the length of buffer circle n []; K is a sampling number; I is the related channel program of current calculating, the delay of array ChDelay [] storage channels, and array ChData [] deposits correlation function value.
In interrupt function, the dsp chip circuit is carried out this related function calculation process.At first carry out the k++ operation; And judge that whether k is greater than L-1; If greater than showing that then buffer circle is filled with; Be initialized as 0 with k this moment, and the new photon count value that the dsp chip circuit reads deposits the start element n (0) of buffer circle in, otherwise the new photon count value that the dsp chip circuit reads deposits the unit n (k) of buffer circle in.The related channel program of depositing according to array ChDelay [] then postpones; Ask for buffer circle cell position j=k-ChDelay [i]; Extract stored count value n [j], multiply each other, carry out accumulating operation again with new photon count value n [k]; Obtain the correlation function value of related channel program i, and deposit array ChData [i] in.If j 0, j+L then, if j=-1, j=L-1 so, extract count value n (L-1) this moment, multiplies each other with New count value n [k], as shown in Figure 7.Interrupt function of every execution, the computation process of above-mentioned related function will repeat N time, and i is added to N-1 from 0, obtains the correlation function value of N passage, deposits array ChData [] in.
For example, count value n (k) carries out multiplication mutually with count value n (k-1), is added on the product of n (k-1) and n (k-2) again, obtains the 1st passage correlation function value G (τ); Count value n (k) carries out multiplication mutually with n (0), is added on the product of n (k-1) and n (L-1) again, obtains the correlation function value G (k τ) of k passage.With aforementioned 64 passage ratio auto-correlation computations is example (N=64), and the loop buffer section length is L (L>5000), shown in the delay of each passage is as above shown, obtains the correlation function value of each passage.
Can find out from the aforementioned calculation process; Read new photon count value not with buffer circle in all count values of having stored carry out related operation; And the channel delay of only storing according to array ChDelay [] calculates the channel position that needs; Carry out related operation again, thereby realized the design of ratio correlator.Upward routine correlator is 5 * 10 with the dynamic range of 64 related channel programs realizations 3
For preventing to overflow, correlation function value of the present invention converts 32 floating-point format number storages to.With the 1Mcps light intensity, the maximum 40ms sampling time is an example, and the average photon count value is 4 * 10 4, be 1.6 * 10 to the maximum after count value multiplies each other 9, the maximal value that 32 floating-point format numbers can be represented is 3.4 * 10 38, before overflowing, can add up (3.4 * 10 so 38)/(1.6 * 10 9)=2.1 * 10 29Inferior, the duration reaches 2.1 * 10 29* 40ms=8.5 * 10 27S=2.4 * 10 24Hour, satisfy the demand of nanometer and submicron particles granulometry fully.
The related operation module is the core of photon correlator, and the function that is realized is that the photon count value of photon counting module Counter output is carried out real-time auto-correlation computation.The preceding k group passage computing method of related operation module are following:
First passage: G (τ)=n 0n 1+ n 1n 2+ ... + n N-1n N
Second channel: G (2 τ)=n 0n 2+ n 1n 3+ ... + n N-2n N
Third channel: G (3 τ)=n 0n 3+ n 1n 4+ ... + n N-3n N
Four-way: G (4 τ)=n 0n 4+ n 1n 5+ ... + n N-4n N
The k passage: G ( K&tau; ) = &Sigma; i = 0 N - k n i n i + k
More than show and described ultimate principle of the present invention and principal character and advantage of the present invention.The technician of the industry should understand; The present invention is not restricted to the described embodiments; That describes in the foregoing description and the instructions just explains principle of the present invention; Under the prerequisite that does not break away from spirit and scope of the invention, the present invention also has various changes and modifications, and these variations and improvement all fall in the scope of the invention that requires protection.The present invention requires protection domain to be defined by appending claims and equivalent thereof.

Claims (7)

1. based on the ratio photon correlator of DSP buffer circle, it is characterized in that comprise a fpga chip circuit, a dsp chip circuit, a computing machine, said dsp chip circuit connects said fpga chip circuit, said computing machine respectively;
Said fpga chip circuit comprises that a sampling time is provided with module, a reseting module, a photon counting module;
Said dsp chip circuit comprises related channel program computing module time delay, a buffer circle, a related operation module;
Said fpga chip circuit produces sampled clock signal, and photon pulse is counted;
Said dsp chip circuit is realized the function of shift register through said buffer circle; According to the adjacency channel ratio R of time delay; The delay time of each passage is set, and, realizes the computing of related function through said related operation module; And sending related function to said computing machine, said computing machine obtains the size-grade distribution of particle through inversion algorithm.
2. the ratio photon correlator based on the DSP buffer circle according to claim 1 is characterized in that: the said sampling time is provided with module and comprises code translator, trigger, counter and comparer; The said sampling time is provided with module through the system clock frequency division is obtained sampled clock signal: the system clock frequency that the sampling clock frequency equals to import is divided by divide ratio; Said computing machine calculates divide ratio according to user's setting; And send to the dsp chip circuit; The dsp chip circuit is provided with module with the sampling time that divide ratio writes the fpga chip inside circuit again, through counter system clock is counted, and is compared with divide ratio; Realization is to the frequency division of system clock, the sampled clock signal that can obtain expecting.
3. the ratio photon correlator based on the DSP buffer circle according to claim 2; It is characterized in that: said reseting module comprises code translator and trigger; Said reseting module is used to produce systematic reset signal; When reset signal is high level, empty the count value of said photon counting module; When reset signal was low level, said photon counting module was counted photon pulse.
4. the ratio photon correlator based on the DSP buffer circle according to claim 3 is characterized in that: said photon counting module comprises two counters, two latchs and multi-channel data selector; Under the driving of sampled clock signal, two said counter alternate runs are realized exporting to said dsp chip circuit to the seamless counting of photon pulse and with count results.
5. according to any described ratio photon correlator in the claim 1 to 4 based on the DSP buffer circle; It is characterized in that: said related channel program computing module time delay in the said dsp chip circuit is dynamic range and the port number that utilizes photon correlator; Calculate the adjacency channel ratio R of time delay, then according to τ k=τ R K-1Calculate the time delay of each passage, τ is the time delay of the 1st passage.
6. the ratio photon correlator based on the DSP buffer circle according to claim 5 is characterized in that: the said buffer circle in the said dsp chip circuit has been realized the function of shift register, after said dsp chip circuit reads the photon count value of said photon counting module output; Deposit said buffer circle in; The capacity of buffer circle is L, deposits the 0th photon count value n (0) in from the start element of buffer circle, and subsequent count values deposits the follow-up unit of buffer circle successively in; When count value is increased to n (L-1); Buffer circle is filled with, and next count value n (L) deposits the start element of storage n (0) in, and count value n (0) is override; By that analogy, realize circulation.
7. the ratio photon correlator based on the DSP buffer circle according to claim 6 is characterized in that: the said related operation module in the said dsp chip circuit, according to the said related channel program computing module time delay precalculated channel delay time; Extract the photon count value of corresponding units storage in the said buffer circle, utilize hardware multiplier, carry out multiplying with the New count value; Add up again; Obtain the correlation function value of each passage, and convert the result to 32 floating-point format numbers, be transferred to said computing machine through USB interface; Said computing machine obtains the size-grade distribution of particle through inversion algorithm.
CN2012101601571A 2012-05-22 2012-05-22 Proportional photon correlator based on digital signal processor (DSP) annular buffer area Pending CN102798582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012101601571A CN102798582A (en) 2012-05-22 2012-05-22 Proportional photon correlator based on digital signal processor (DSP) annular buffer area

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012101601571A CN102798582A (en) 2012-05-22 2012-05-22 Proportional photon correlator based on digital signal processor (DSP) annular buffer area

Publications (1)

Publication Number Publication Date
CN102798582A true CN102798582A (en) 2012-11-28

Family

ID=47197764

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012101601571A Pending CN102798582A (en) 2012-05-22 2012-05-22 Proportional photon correlator based on digital signal processor (DSP) annular buffer area

Country Status (1)

Country Link
CN (1) CN102798582A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103873042A (en) * 2012-12-17 2014-06-18 快捷半导体(苏州)有限公司 Delay method, delay circuit and integrated circuit
CN104792670A (en) * 2015-04-09 2015-07-22 华南师范大学 FPGA (field programmable gate array)-based multiplexing photon correlator
CN110857909A (en) * 2018-08-24 2020-03-03 北京世纪朝阳科技发展有限公司 System for measuring particle size of particles
CN113447406A (en) * 2021-07-07 2021-09-28 中国计量科学研究院 FPGA-based multichannel dynamic light scattering autocorrelation system and method

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1162060A (en) * 1966-12-29 1969-08-20 Int Standard Electric Corp Bilateral Transmission System in Pulse Code Modulation
JP2002296118A (en) * 2001-03-30 2002-10-09 Otsuka Denshi Co Ltd Photon correlation meter
CN1542759A (en) * 2003-04-10 2004-11-03 威腾光电股份有限公司 Clock signal regulator
CN1841978A (en) * 2005-04-01 2006-10-04 大唐电信科技股份有限公司 Method and apparatus for realizing multipath signal re-timing
CN101261129A (en) * 2008-02-22 2008-09-10 北京航空航天大学 Integrated navigation computer based on DSP and FPGA
CN101354439A (en) * 2008-08-28 2009-01-28 阮树成 Millimeter-wave time-division random code phase modulation multichannel colliding-proof radar for car
CN101534183A (en) * 2009-04-10 2009-09-16 华南理工大学 Real-time configurable digital correlator based on FPGA
US7649931B1 (en) * 2006-12-29 2010-01-19 Kiomars Anvari Equalizer filter with dynamically configurable code domain filter
CN101726452A (en) * 2009-12-08 2010-06-09 华南师范大学 Photon correlator based on field programmable gate array (FPGA)
CN102063401A (en) * 2011-01-13 2011-05-18 四川大学 TDMOW serial bus structure of distributed oscillograph and encoding method
CN201898491U (en) * 2010-11-10 2011-07-13 天津光电通信技术有限公司 Pulse width modulation generator
CN102313604A (en) * 2011-07-12 2012-01-11 华南师范大学 Adaptive photon correlator on basis of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array)
US8179161B1 (en) * 2009-05-05 2012-05-15 Cypress Semiconductor Corporation Programmable input/output circuit

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1162060A (en) * 1966-12-29 1969-08-20 Int Standard Electric Corp Bilateral Transmission System in Pulse Code Modulation
JP2002296118A (en) * 2001-03-30 2002-10-09 Otsuka Denshi Co Ltd Photon correlation meter
CN1460176A (en) * 2001-03-30 2003-12-03 大塚电子株式会社 Photon correlator
CN1542759A (en) * 2003-04-10 2004-11-03 威腾光电股份有限公司 Clock signal regulator
CN1261931C (en) * 2003-04-10 2006-06-28 威腾光电股份有限公司 Clock signal regulator
CN1841978A (en) * 2005-04-01 2006-10-04 大唐电信科技股份有限公司 Method and apparatus for realizing multipath signal re-timing
US7649931B1 (en) * 2006-12-29 2010-01-19 Kiomars Anvari Equalizer filter with dynamically configurable code domain filter
CN101261129A (en) * 2008-02-22 2008-09-10 北京航空航天大学 Integrated navigation computer based on DSP and FPGA
CN101354439A (en) * 2008-08-28 2009-01-28 阮树成 Millimeter-wave time-division random code phase modulation multichannel colliding-proof radar for car
CN101534183A (en) * 2009-04-10 2009-09-16 华南理工大学 Real-time configurable digital correlator based on FPGA
US8179161B1 (en) * 2009-05-05 2012-05-15 Cypress Semiconductor Corporation Programmable input/output circuit
CN101726452A (en) * 2009-12-08 2010-06-09 华南师范大学 Photon correlator based on field programmable gate array (FPGA)
CN201898491U (en) * 2010-11-10 2011-07-13 天津光电通信技术有限公司 Pulse width modulation generator
CN102063401A (en) * 2011-01-13 2011-05-18 四川大学 TDMOW serial bus structure of distributed oscillograph and encoding method
CN102313604A (en) * 2011-07-12 2012-01-11 华南师范大学 Adaptive photon correlator on basis of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array)

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
WEI LIU: "Design of Multiple-Tau Photon Correlation System Implemented by FPGA", 《ICESS2008》 *
WEI LIU: "The Implement of Single Input Multiple Output Shift Register for Photon Correlator", 《PHOTONICS AND OPTOELECTRONICS》 *
成艳亭: "《山东理工大学硕士学位论文》", 19 October 2009 *
马玉良: "《济南大学硕士学位论文》", 24 August 2011 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103873042A (en) * 2012-12-17 2014-06-18 快捷半导体(苏州)有限公司 Delay method, delay circuit and integrated circuit
CN103873042B (en) * 2012-12-17 2017-02-08 快捷半导体(苏州)有限公司 Delay method, delay circuit and integrated circuit
CN104792670A (en) * 2015-04-09 2015-07-22 华南师范大学 FPGA (field programmable gate array)-based multiplexing photon correlator
CN104792670B (en) * 2015-04-09 2018-04-03 华南师范大学 A kind of multiplexing photon correlator based on field programmable gate array
CN110857909A (en) * 2018-08-24 2020-03-03 北京世纪朝阳科技发展有限公司 System for measuring particle size of particles
CN110857909B (en) * 2018-08-24 2022-05-20 北京世纪朝阳科技发展有限公司 System for measuring particle size of particles
CN113447406A (en) * 2021-07-07 2021-09-28 中国计量科学研究院 FPGA-based multichannel dynamic light scattering autocorrelation system and method

Similar Documents

Publication Publication Date Title
CN102798589B (en) High-speed photon correlator with large dynamic range
CN102798582A (en) Proportional photon correlator based on digital signal processor (DSP) annular buffer area
CN101520640A (en) Time interval measuring instrument based on FPGA
CN101639499B (en) Device and method for measuring small signal harmonic distortion traced by fundamental waves
EP0086570B1 (en) Digital signal processor
CN101499791A (en) PWM control method
CN109271133A (en) A kind of data processing method and system
CN109194307A (en) Data processing method and system
CN100492026C (en) Electric energy computation circuit removing DC and circuit removing DC
US20110158259A1 (en) Apparatus and Method for Frequency Division and Filtering
JP5057922B2 (en) Correlator
CN201331680Y (en) Time interval measuring instrument based on FPGA
CN101917204B (en) Computing and digital control method of scanning control parameters of scanning frequency receiver
Asch et al. Design of an ideal digital correlation computer
CN102113215B (en) Optimizing processor operation in processing system including one or more digital filters
CN203942513U (en) Adjustable high precision fractional frequency division circuit based on FPGA
CN102866097A (en) Real-time pollution degree detection method of oil particle counter under variable flow condition
JP2002296118A (en) Photon correlation meter
EP2093558B1 (en) Correlator
CN2570775Y (en) Liquid corpuscular counter
Liu et al. Novel photon correlator with less hardware resource
RU2753822C1 (en) Statistical analyzer of time intervals (variants)
CN117889925A (en) Cross-correlation signal hardware detection circuit and automatic instrument
CN113447406B (en) Multichannel dynamic light scattering autocorrelation system and method based on FPGA
RU2242013C2 (en) Correlation analyzer of frequency properties of linear system

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20121128