CN102798582A - Proportional photon correlator based on digital signal processor (DSP) annular buffer area - Google Patents

Proportional photon correlator based on digital signal processor (DSP) annular buffer area Download PDF

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CN102798582A
CN102798582A CN2012101601571A CN201210160157A CN102798582A CN 102798582 A CN102798582 A CN 102798582A CN 2012101601571 A CN2012101601571 A CN 2012101601571A CN 201210160157 A CN201210160157 A CN 201210160157A CN 102798582 A CN102798582 A CN 102798582A
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photon
dsp
module
ring buffer
circuit
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CN2012101601571A
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刘伟
陆文玲
申晋
王雅静
谭博学
孙贤明
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山东理工大学
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Abstract

The invention relates to the technical field of photon correlation spectroscopy granulometry, in particular to a photon correlator. A proportional photon correlator based on a digital signal processor (DSP) annular buffer area comprises a field programmable gate array (FPGA) chip circuit, a DSP chip circuit and a computer, wherein the DSP chip circuit is respectively connected with the FPGA chip circuit and the computer; the FPGA chip circuit comprises a sampling time setting module, a reset module and a photon counting module; and the DSP chip circuit comprises a correlation channel delay time computation module, an annular buffer area and a correlation operation module. By adoption of the technical scheme, a DSP and an FPGA chip are combined together, the size of the correlator is reduced, and the cost of the correlator is reduced.

Description

基于DSP环形缓冲区的比例光子相关器 DSP ring buffer based on the ratio of photon correlator

技术领域 FIELD

[0001] 本发明涉及光子相关光谱法粒度测量技术领域,具体涉及一种光子相关器。 [0001] The present invention relates to the field size of the particle photon correlation spectroscopy, particularly to a photon correlator. 背景技术 Background technique

[0002] 在亚微米和纳米颗粒的悬浮液中,颗粒由于受到周围正在进行布朗运动的液体分子的不断撞击,处于不停的运动之中,颗粒越小,运动越剧烈。 [0002] In a suspension of sub-micron and nano-particles, the particles being continuously around the impact due to Brownian motion of the molecules of the liquid, it is in constant motion, the smaller the particle, the more strenuous exercise. 这种运动使得颗粒散射光的频率相对于入射光产生多普勒频移,表现为在一定的散射角下,散射光强随时间不断地涨落,这是由各个颗粒发出的散射光场的相干叠加而造成的,这种散射光的动态波动情况称为动态光散射,光子相关光谱颗粒测量方法就是通过研究这种波动现象来获取颗粒的粒径及其分布信息的。 This motion causes the particles scatter light with respect to incident light frequency Doppler shift, performance under certain scattering angle of the scattered light intensity with time and the fluctuation, which is emitted by light scattering from individual particles caused by coherent addition, the dynamic fluctuation of scattered light is called dynamic light scattering, photon correlation spectroscopy method for measuring the particle size of the particles is used to obtain the fluctuation phenomenon by studying its distribution information.

[0003] 光子相关光谱法纳米颗粒粒度测量装置如图I所示,测量装置由入射光路和测量光路组成。 [0003] Photon correlation spectroscopy of nanometer particle size measuring apparatus shown in FIG. I, by the incident light path and the measuring means measuring optical path components. 入射光路由激光器11、衰减片12和聚焦透镜13组成,激光器11发出的入射光穿过衰减片12,经过聚焦透镜13后,照射到样品池14的颗粒样品上。 Routing the incident laser 11, an attenuator 12 and a focusing lens 13 consisting of, the incident light emitted from laser 11 passes through the attenuator 12, after the focusing lens 13, is irradiated onto the sample cell 14 of the sample particles. 测量光路主要由小孔15、光电倍增管16和光子相关器17构成,受照射的颗粒产生散射光,散射光经过小孔15进入光电倍增管16。 Mainly by the measurement optical path holes 15, 16 and photomultiplier tube 17 constituting the photon correlation, illuminated light scattering particles, the scattered light 15 entering through the orifice 16 photomultiplier tube. 小孔15的作用是保证接收的散射光来自相干区,同时去除周围的杂散光。 Effect of orifice 15 is to ensure the reception of scattered light from a coherent region, while removing stray ambient light. 散射光由光电倍增管16接收,经后续电路的信号放大和幅度甄别,成为等幅脉冲信号。 Scattered light pulse signal amplitude from the photomultiplier 16 receives, via the signal amplification and subsequent amplitude discrimination circuit becomes like. 这些脉冲信号被送入光子相关器17,在光子相关器17中完成计数和乘累加操作,得到自相关函数。 These pulses are fed photon correlator 17, and the multiply-accumulate operation finishes counting, auto-correlation function of the photon correlator 17. 最后利用粒度分布反演算法,由计算机18计算出颗粒的粒径及其分布。 Finally, using the inversion algorithm particle size distribution, particle size and distribution is calculated by the computer 18.

[0004] 在光子相关光谱颗粒测量实验中,光子相关器17需要足够大的动态范围,才能使自相关函数衰减到基线,获得稳定的测量结果。 [0004] Photon correlation spectroscopy measurement experiment in the particles, photon correlation 17 is sufficiently large dynamic range, to make the autocorrelation function decays to a baseline, to obtain a stable measurement result. 动态范围定义为其中,T为第一个通道的延迟时间,^为最后一个通道的延迟时间。 Dynamic range is defined as where, T is the delay time of the first channel, ^ delay time of the last channel. 对于线性相关器,通道间的延迟时间以线性规律增加,那么第k个线性通道的延迟时间为:T k = k • T,每个k值对应一个线性相关通道。 For linear correlator, a delay time between channels increases to a linear law, the delay time of the k-th channel is linear: T k = k • T, k value of each channel corresponds to a linear correlation. 线性相关器的动态范围与通道数相等,当需要的动态范围较大时,就会需要相同数量的相关通道,这在硬件设计上难以实现。 Linear dynamic range equal to the channel number of the correlator, when a large dynamic range is required, it will require the same amount of the relevant channel, it is difficult to realize in hardware design. 若要以有限的相关通道达到所需的大动态范围,则必然要降低采样频率,加长采样时间,致使时间分辨率大大下降。 To a limited relevant channel to achieve the required large dynamic range, it is bound to reduce the sampling frequency, longer sampling time, resulting in greatly reduced time resolution.

[0005] 光强自相关函数是一条按指数规律衰减的曲线,不同的延迟时间,对相关曲线有不同的时间分辨率要求,即在相关器起始的几个通道间需要较短的延迟时间,以保持足够的时间分辨率,而当曲线衰减到基线后,通道间延迟时间要尽可能延长,以保证相关器足够的动态范围。 [0005] The intensity autocorrelation function is an exponentially decaying curve, different delay times, have different time resolution requirements of the correlation curve, i.e. a shorter delay time between the start of several channels correlators to maintain a sufficient time resolution, and when the decay curve to the base line, to extend the time delay between channels as possible to ensure a sufficient dynamic range of the correlator. 线性相关器将相关通道延迟时间平均分配,相关曲线变化缓慢部分造成通道资源浪费,相关曲线快速衰减部分受通道数量的限制,时间分辨率不高。 Linearly related to the relevant channel delay is the time average allocated, the relevant part of the curve changes slowly wasting channel resources associated rapid decay curve in part by limiting the number of channels, time resolution is not high. 因此,可以采用比例相关器,比例相关器改变了通道间延迟时间按线性递增的规律,使之按照比例关系Tk =T -RH递增,式中,R为相邻通道延迟时间的比例,在相关函数的起始段按照线性规律增长,随着相关通道序号的加大,通道间的延迟时间按一定的比例增长,用有限的相关通道达到了较大的动态范围,同时在相关曲线的起始段保持着较高的时间分辨率。 Thus, the proportion may be employed correlator, the correlator ratio change laws of the inter-channel delay time linearly increasing, so that in the ratio Tk = T -RH incremental, wherein, R is the ratio of the time delay of adjacent channels in the relevant initial segment growth function according to a linear law, associated with the increasing number of channels, the time delay between channels by a certain percentage growth, associated with limited channel achieve a large dynamic range, while at the beginning of the correlation curve segment maintained a high temporal resolution.

[0006] 但由于无法事先确定比例相关器的通道延迟时间,使得光子计数值延迟单元的设计成为难题,阻碍了比例光子相关器的实现。 [0006] However, since the ratio could not be determined in advance of the correlator delay time of the channel, so that the photon count value of the delay unit designed to become a problem, the proportion of hindering the realization of photon correlator. 发明内容 SUMMARY

[0007] 本发明的目的在于,提供基于DSP环形缓冲区的比例光子相关器,解决以上技术问题。 Objective [0007] The present invention is to provide a DSP ring buffer based on the ratio of photon correlator, to solve the above technical problem.

[0008] 本发明所解决的技术问题可以采用以下技术方案来实现: [0008] The problem addressed by the present invention technical problem is achieved by the following technical solution:

[0009] 基于DSP环形缓冲区的比例光子相关器,其特征在于,包括一FPGA芯片电路、一DSP芯片电路、一计算机,所述DSP芯片电路分别连接所述FPGA芯片电路、所述计算机; [0009] DSP ring buffer based on the ratio of photon correlation, characterized in that it comprises a circuit chip FPGA, a DSP chip circuit, a computer, the DSP circuit chip connected to the FPGA circuit chip, said computer;

[0010] 所述FPGA芯片电路包括一米样时间设置模块、一复位模块、一光子计数模块; [0010] The FPGA chip circuit comprises a time setting module rice samples, a reset module, a photon counting module;

[0011] 所述DSP芯片电路包括一相关通道延迟时间计算模块、一环形缓冲区、一相关运算模块; [0011] The DSP chip circuit comprises a correlation channel delay time calculating module, a ring buffer, a correlation calculation module;

[0012] 所述FPGA芯片电路产生采样时钟信号,并对光子脉冲进行计数; [0012] The FPGA chip circuit generates a sampling clock signal, and counting photon pulses;

[0013] 所述DSP芯片电路通过所述环形缓冲区实现移位寄存器的功能,根据相邻通道延迟时间的比例R,设置每一个通道的延时时间,并通过所述相关运算模块,实现相关函数的运算,并将相关函数传送给所述计算机,所述计算机通过反演算法获得颗粒的粒度分布。 [0013] The DSP chip via said ring buffer circuit implement the functions of the shift register, a delay time in accordance with the ratio of adjacent channels R, set the delay time for each channel, and by the correlation calculating module, associated calculating function and the correlation function is transmitted to the computer, the computer to obtain a particle size of particles distributed through the inversion algorithm.

[0014] 本发明的采样时间模块设置采样间隔,光子计数模块实现对光电倍增管等幅光子脉冲信号的计数,并将计数值传输给相关运算模块,相关运算模块对光子计数值进行乘累加运算,得到每个通道的相关函数值,然后将结果发送给计算机,利用反演算法计算出颗粒粒度及其分布。 [0014] module of the present invention, the sampling time is set sampling interval, the photon counting module for counting the pulse signal amplitude photon photomultiplier tube or the like, and the count value is transferred to the relevant computing module, photon correlation calculation module multiply adds the count value to obtain the correlation function value for each channel, and then transmits the result to the computer, and the particle size distribution is calculated using the inversion algorithm. 本发明基于DSP和FPGA芯片电路,利用DSP芯片电路内环形缓冲区实现比例通道相关运算,使用较少的通道实现较大的动态范围,完全满足纳米及亚微米颗粒粒度测量的需求,降低了光子相关器的成本。 The present invention is based on the DSP and the FPGA chip circuitry, the DSP chip circuit using a ring buffer to achieve the ratio of the channel correlation calculation, using fewer channels to achieve a large dynamic range, and fully meet the demand of nano submicron particle size measurement, the photon reducing the cost of the correlator.

[0015] 所述采样时间设置模块包括译码器、触发器、计数器和比较器;所述采样时间设置模块通过对系统时钟分频得到采样时钟信号:采样时钟频率等于输入的系统时钟频率除以分频系数,所述计算机根据用户的设置计算出分频系数,并发送给DSP芯片电路,DSP芯片电路再将分频系数写入FPGA芯片电路内部的采样时间设置模块,通过计数器对系统时钟进行计数,并与分频系数进行比较,实现对系统时钟的分频,即可得到预期的采样时钟信号。 [0015] The sampling time setting module comprises a decoder, flip-flop, a counter and a comparator; the sampling time of the system clock module to obtain a sampling clock divider signal: the system clock frequency equal to the input sampling clock frequency divided by division factor, calculated according to the computer user is provided a division factor, and sent to the DSP chip circuit, then the DSP chip division coefficient writing circuit inside the FPGA circuit chip sampling time modules for the system clock by a counter counted and compared with the division factor, to achieve frequency division of the system clock, to give the desired sampling clock signal.

[0016] 所述复位模块包括译码器和触发器,所述复位模块用于产生系统复位信号,当复位信号为高电平时,清空所述光子计数模块的计数值;当复位信号为低电平时,所述光子计数模块对光子脉冲进行计数。 [0016] The reset module comprises a decoder and a flip-flop, the reset module for generating a system reset signal when the reset signal is high, the photon counting module emptying the count value; when the reset signal is low usually, the photon counting module counts photon pulses.

[0017] 所述光子计数模块包括两个计数器、两个锁存器和多路数据选择器;在采样时钟信号的驱动下,两个所述计数器交替运行,实现对光子脉冲的无缝计数并将计数结果输出给所述DSP芯片电路。 [0017] The photon-counting module comprises two counters, two data latches and multiplexer selector; driven by a sampling clock signal, said counter two alternate operation, seamless photon pulses and counting the counted result output circuit to the DSP chip.

[0018] 所述DSP芯片电路中的所述相关通道延迟时间计算模块是利用光子相关器的动态范围和通道数,计算相邻通道延迟时间的比例R,然后依据Tk= T .RH计算出每个通道的延迟时间,T为第I通道的延迟时间。 [0018] The DSP chip in the relevant channel circuit delay time calculation module is the dynamic range and the number of channels using photon correlation unit calculates the ratio R channel delay time is adjacent, and each calculated based on Tk = T .RH channels delay time, T is the delay time of the I-channel.

[0019] 所述DSP芯片电路中的所述环形缓冲区实现了移位寄存器的功能,所述DSP芯片电路读取所述光子计数模块输出的光子计数值后,存入所述环形缓冲区,环形缓冲区的容量为L,从环形缓冲区的起始单元存入第0个光子计数值n (0),后续计数值依次存入环形缓冲区的后续单元,当计数值增加到n (LI)时,环形缓冲区存满,下一个计数值n (L)存入存储n(0)的起始单元,将计数值n (O)覆盖掉,以此类推,实现循环。 [0019] The ring buffer circuit in the DSP chip to realize the function of a shift register, said DSP chip circuit reads the count value of photons output by the photon counting module, stored in said ring buffer, capacity of the ring buffer is L, the stored first count value 0 photons n (0) from the start of the circular buffer unit, subsequent count values ​​successively stored in the ring buffer subsequent unit, when the count value increases to n (LI ), the ring buffer is full, the next count value n (L) stored in the memory n (0) of the starter unit, the count value n (O) overwritten, and so on, to achieve circulation.

[0020] 所述DSP芯片电路内的所述相关运算模块,按照所述相关通道延迟时间计算模块预先计算的通道延迟时间,提取所述环形缓冲区内相应单元存储的光子计数值,利用硬件乘法器,与新计数值进行乘法运算,再进行累加, 得到每个通道的相关函数值,并将结果转换成32位浮点格式数,通过USB接口传输给所述计算机,所述计算机通过反演算法,得到颗粒的粒度分布。 Photon count value stored in the respective ring buffer unit [0020] The correlation calculation module within the DSP chip circuit, a pre-computed path calculation module according to the correlation time of the channel delay time, the extraction using the hardware multiplier , a new count value with the multiplication, and then accumulates the obtained correlation function value for each channel, and converts the result into a 32-bit floating point formats, USB interface to transfer to the computer, the computer through inversion algorithm, a particle size distribution of the particles.

[0021] 所述相关运算模块是光子相关器的核心,它实现的功能是对光子计数模块输出的光子计数值进行实时自相关运算。 The [0021] photon correlation calculation module is the core of the correlator, it is the function of the count value of photons output by photon counting module for real-time autocorrelation. 前k个通道自相关运算的基本原理如下: The first k channels from the basic principles of correlation calculation is as follows:

[0022]第一通道:G ( T ) =Hon^n1Ii2+*•• ; [0022] First passage: G (T) = Hon ^ n1Ii2 + * ••;

[0023]第二通道:G (2 T ) =¾¾+]^¾+…+nN_2nN ; [0023] Second passage: G (2 T) = ¾¾ +] ^ ¾ + ... + nN_2nN;

[0024]第三通道:G(3 T ) =¾¾+]^¾+... +nN_3nN ; [0024] The third passage: G (3 T) = ¾¾ +] ^ ¾ + ... + nN_3nN;

[0025]第四通道:G(4 T )=¾¾+]^¾+…+nN_4nN ; [0025] The fourth channel: G (4 T) = ¾¾ +] ^ ¾ + ... + nN_4nN;

Nk Nk

[0026]第 k 通道:G(Jif) = V U1H , [0026] k-th channel: G (Jif) = V U1H,

1-0 1-0

[0027] 本发明各通道自相关运算依据上述基本原理实现。 [0027] The present invention each channel autocorrelation implemented according to the above basic principle.

[0028] 光子相关器的基本工作原理如下:在光子相关光谱法纳米颗粒粒度测量装置中通常还包括光电倍增管、放大电路、甄别电路,首先所述光电倍增管将接收到的散射光信号转换为等幅光子脉冲信号,然后利用所述放大电路进行放大,再通过甄别电路甄别后送入所述光子计数模块的计数器,所述计数器对采样时间内的光子脉冲进行计数,然后送入移位寄存器。 The basic principle of [0028] Photon correlation is as follows: the particle size of nanometer photon correlation spectroscopy measurement apparatus typically further comprises a photomultiplier tube, an amplifier circuit, discriminating circuit, the first photomultiplier tube converts the scattered light signal received It is the photon pulse amplitude is then amplified using the amplifier circuit, and then screened by the screening circuit of the photon counting module into a counter photon pulses counted within the sampling time, and then into the shift register. 本发明中的环形缓冲区作为移位寄存器。 The present invention is in the ring buffer as a shift register. 每一次采样完成后,在采样时钟信号的控制下,计数器将计数结果送入移位寄存器的第一级,下一个采样时钟的上升沿到来时,移位寄存器第一级原来的内容被移入到第二级,第二级原来的内容被移入到第三级,以此类推。 After the completion of each sample, under the control of a sampling clock signal, the counter counting result into a first stage of the shift register, when a rising edge of the sampling clock of arrival, the first stage of the shift register is moved to the original content a second stage, the second stage of the original content is moved to the third stage, and so on. 移位寄存器的内容在采样时钟的控制下依次顺序右移,形成了不同延迟时间的计数值,每一级移位寄存器相当于相关器的一个线性通道。 Shift register is shifted to the right in sequential order under the control of sampling clock count values ​​are formed of different delay times, each stage of the shift register corresponds to a linear channel correlator. 采样期间,当前计数值Iii与第k通道计数值ni+k进行相乘,然后将相乘结果送入第k通道的存储器进行累加,得到的累加值即为自相关函数值G (k T )。 During sampling, the current count value of the k channels Iii count value ni + k multiplies, and the multiplication result into the memory of the k-th channel accumulated, the accumulated value obtained is the value of the autocorrelation function G (k T) .

[0029] 有益效果:本发明与现有技术相比具有以下优点: [0029] The beneficial effects: the present invention and the prior art has the following advantages:

[0030] I)本发明的相关运算模块采用环形缓冲区实现了移位寄存器的功能,可以灵活的设置所需比例通道的延迟时间,以较低的硬件成本实现比例光子相关器的设计; [0030] I) of the present invention is related to the arithmetic module implemented using a ring buffer function of a shift register, a desired delay time can be flexible proportion channel disposed at a lower hardware cost proportional to achieve photon correlation Design;

[0031] 2)本发明可根据不同的测量需求,选择线性通道或比例通道算法。 [0031] 2) The present invention can be measured according to different needs, select the channel or the proportion channel linear algorithm. 采用比例相关算法时,在有限通道的情况下,既可以保证相关函数具有足够高的时间分辨率,又可以获得足够大的动态范围; With proportional correlation algorithm, in the case of limited channel, both to ensure that the correlation function has a sufficiently high temporal resolution, and can obtain a sufficiently large dynamic range;

[0032] 3)本发明的光子计数模块采用FPGA芯片实现,通过两个光子计数器交替工作实现了无缝隙计数,保证了光子计数的准确性; [0032] 3) photon counting module of the invention using FPGA chip, working alternately by two photon counter counts to achieve a seamless, to ensure the accuracy of the photon counting;

[0033] 4)本发明基于DSP芯片,实现相关函数的计算,可以在不改变硬件的前提下优化相关算法,提高系统的扩展性; [0033] 4) The present invention is based on the DSP chip, calculating the correlation function, correlation algorithm can be optimized without changing the hardware of the premise of improving the scalability of the system;

[0034] 5)本发明将DSP和FPGA芯片组合在一起,缩小了相关器的体积,降低了相关器的成本。 [0034] 5) The present invention is a combination of a DSP and FPGA chip together, reducing the volume of the correlator, the correlator reduces the cost. 附图说明 BRIEF DESCRIPTION

[0035] 图I为光子相关光谱法纳米颗粒粒度测量装置框图; [0035] Figure I a block diagram of apparatus for the measuring of nanometer particle size by photon correlation spectroscopy;

[0036] 图2为本发明光子相关器的结构示意图; Structure [0036] FIG. 2 is a schematic view of the invention, the photon correlator;

[0037] 图3为本发明光子相关器的整体电路连接示意图; Overall circuit [0037] FIG. 3 is an schematic photon correlation is connected;

[0038] 图4为本发明采样时间设置模块的结构示意图; [0038] Fig 4 a schematic structural diagram of a sampling time setting module of the present invention;

[0039] 图5为本发明复位模块的结构示意图; [0039] FIG. 5 is a schematic structural diagram of the present invention, the reset module;

[0040] 图6为本发明光子计数模块的结构示意图; [0040] Fig 6 a schematic view of the structure of the present invention, the photon counting module;

[0041] 图7为本发明相关运算模块的原理图; [0041] Figure 7 is a schematic diagram of the invention related to the arithmetic module;

[0042] 图8为本发明相关通道延时时间计算流程图; [0042] FIG 8 channel delay time calculating flowchart related to the present invention;

[0043] 图9为本发明相关函数计算流程图。 [0043] FIG. 9 is a flowchart illustrating calculation of correlation function invention.

具体实施方式 Detailed ways

[0044] 为了使本发明实现的技术手段、创作特征、达成目的与功效易于明白了解,下面结合具体图示进一步阐述本发明。 [0044] In order to achieve the technical means of the present invention, the creation of features, to achieve the purpose and effect readily apparent understood as specifically illustrated below with reference to further illustrate the present invention.

[0045] 参照图2、图3,基于DSP环形缓冲区的比例光子相关器,包括FPGA芯片电路、DSP芯片电路、计算机PC,DSP芯片电路分别连接FPGA芯片电路、计算机PC。 [0045] Referring to FIG. 2, FIG. 3, are connected to the FPGA chip DSP ring buffer circuit based on the ratio of photon correlator circuit comprises a FPGA chip, DSP chip circuits, the PC computer, DSP chip circuitry, computer PC. FPGA芯片电路包括采样时间设置模块SampleTime、复位模块Reset、光子计数模块Counter。 FPGA chip time setting circuit includes a sampling module SampleTime, reset module Reset, the photon counting module Counter. DSP芯片电路包括相关通道延迟时间计算模块、环形缓冲区、相关运算模块。 DSP chip circuit comprises a correlation channel delay time calculating module, a ring buffer, correlation calculation module. FPGA芯片电路产生采样时钟信号,并对光子脉冲进行计数。 FPGA chip circuit generates a sampling clock signal, and the photon pulses are counted. DSP芯片电路通过环形缓冲区实现移位寄存器的功能,根据相邻通道延迟时间的比例R,设置每一个通道的延时时间,并通过相关运算模块,实现相关函数的运算,并将相关函数传送给计算机PC,计算机PC通过反演算法获得颗粒的粒度分布。 DSP chip circuit function realized by a ring buffer shift register, a delay time in accordance with the ratio of adjacent channels R, set the delay time for each channel, and by correlation calculation module, calculating the correlation function, and an associated transfer function to the computer PC, PC computer size particles obtained by inversion algorithm distribution.

[0046] 参照图2,在光子相关光谱法纳米颗粒粒度测量装置中通常还包括光电倍增管、放大电路、甄别电路,首先光电倍增管将接收到的散射光信号转换为等幅光子脉冲信号,然后利用放大电路进行放大,再通过甄别电路甄别后送入光子计数模块Counter的计数器,计数器对采样时间内的光子脉冲进行计数,然后送入移位寄存器。 [0046] Referring to FIG 2, in the spectrum of nanometer photon correlation particle size measuring apparatus typically further comprises a photomultiplier tube, an amplifier circuit, discriminating circuits, the first photomultiplier tube converts the received scattered light signal to signal amplitude photon pulses, is then amplified using an amplifier circuit, and then into the screening by the screening circuit of the photon counting module counter counter, counter photon pulses counted within the sampling time, and then into the shift register. 本发明中的环形缓冲区作为移位寄存器。 The present invention is in the ring buffer as a shift register. 每一次采样完成后,在采样时钟信号的控制下,计数器将计数结果送入移位寄存器的第一级,下一个采样时钟的上升沿到来时,移位寄存器第一级原来的内容被移入到第二级,第二级原来的内容被移入到第三级,以此类推;移位寄存器的内容在采样时钟的控制下依次顺序右移,形成了不同延迟时间的计数值,每一级移位寄存器相当于相关器的一个线性通道。 After the completion of each sample, under the control of a sampling clock signal, the counter counting result into a first stage of the shift register, when a rising edge of the sampling clock of arrival, the first stage of the shift register is moved to the original content a second stage, the second stage of the original content is moved to the third stage, and so on; the contents of shift registers in sequential order under the control of right shift the sampling clock, the count value are formed of different delay times, one for each shift bit registers corresponds to a linear channel correlator. 采样期间,当前计数值Ili与第k通道计数值ni+k进行相乘,然后将相乘结果送入第k通道的存储器进行累加,得到的累加值即为自相关函数值G(k T )。 During sampling, the current count value of the k-th channel and Ili count value ni + k multiplies, and the multiplication result into the memory of the k-th channel accumulated, the accumulated value obtained is the value of the autocorrelation function G (k T) .

[0047] 参照图4,FPGA芯片电路内的采样时间设置模块SampleTime通过对系统时钟信号CLK_SYS分频,得到采样时钟信号CLK,并接入光子计数模块Counter。 [0047] Referring to Figure 4, the sampling time is provided in the FPGA chip circuit module SampleTime CLK_SYS by dividing the system clock signal, to obtain the sampling clock signal CLK, the photon counting module and the access Counter. 光子脉冲由CIN引脚输入光子计数模块Counter。 CIN photon pulses from the photon counting module pin Counter. FPGA芯片电路内的复位模块Reset输出的复位信号CLR连接到光子计数模块Counter,当CLR为低电平时,在采样时钟信号CLK的驱动下,光子计数模块Counter对光子脉冲进行计数,并将计数值输出;当CLR为高电平时,清空光子计数模块的计数值。 Reset module reset signal CLR resets the output circuit is connected to the FPGA chip Counter photon counting module, when CLR is low, the driving of the sampling clock signal CLK, the photon counting module Counter photon pulse counting, the count value output; when CLR is high, clear the count value of the photon counting module.

[0048] 参照图3,采样时钟信号CLK同时接入DSP芯片电路的外部中断引脚EXINT,在CLK的上升沿触发DSP芯片电路中断。 [0048] Referring to FIG 3, the sampling clock signal CLK while the external access DSP chip circuit EXINT interrupt pin, the rising edge of CLK DSP chip trigger circuit interruption. DSP芯片电路在中断函数里读取光子计数模块Counter的计数值,将计数值写入环形缓冲区,并依据相关通道延迟时间计算模块计算的各通道延迟时间,读出环形缓冲区相应单元存储的计数值,由DSP芯片电路的硬件乘法器完成乘法运算,再进行累加,得到相关函数值,完成各通道的相关运算。 DSP chips circuit reads the interrupt function in the photon counting module Counter count value, the count value is written to the ring buffer, and calculates each channel module calculates a delay time based on the relevant channel delay time, reads out the corresponding unit stored in the ring buffer count value, done by the hardware multiplier of the multiplication circuit DSP chip, then accumulated to obtain the correlation function values, the correlation calculation is completed for each channel. DSP芯片电路通过并行接口与FPGA芯片电路连接,实现对FPGA芯片电路的读写控制。 DSP chip via a parallel interface circuit and connecting circuit FPGA chip, read and write control circuitry of the FPGA chip. ECE为DSP芯片电路的外部片选信号,EAffE和EARE为DSP芯片电路的读写控制信号,EA[21:0]为DSP芯片电路的地址线,ED[15:0]为DSP芯片电路的数据线。 ECE external circuit chip for the DSP chip select signal, EAffE EARE and read-write control signal DSP circuit chip, EA [21: 0] is the address lines DSP chip circuit, ED [15: 0] data for the DSP chip circuit line. DSP芯片电路通过USB接口将各个通道的相关函数值传输给计算机PC。 DSP chip USB interface circuit via a correlation function value of the transmission of each channel to the computer PC.

[0049] 本发明的各模块,具体包括如下器件: [0049] Each module of the present invention, comprises the following components:

[0050] I)参照图4,采样时间设置模块SampleTime包括译码器Decoder、触发器FD、计数器COUNT和比较器Comparator。 [0050] I) Referring to Figure 4, the sampling time comprises a decoder module SampleTime Decoder, the FD flip-flop, a counter and a comparator COUNT Comparator. 根据预先设定的地址,由译码器Decoder产生片选信号ctl_div,接入触发器FD的时钟输入端口C,在信号ctl_div的上升沿,DSP芯片电路通过数据线ED[15:0]将分频系数写入触发器FD,分频系数通过输出端口DIV[15:0]输出,接A比较器Comparator的输入端B [15:0]。 According to the address set in advance, produced by the decoder ctl_div Decoder chip select signal, the clock input of the access trigger FD Port C, ctl_div rising edge of the signal, the DSP chip circuit via a data line ED [15: 0] will be divided frequency coefficient writing trigger the FD, the frequency division factor via the output port DIV [15: 0] output, connected to the a input of comparator comparator B [15: 0]. 计数器COUNT对系统时钟信号CLK_SYS进行计数,计数结果通过输出端口Q[15:0]输出,接入比较器Comparator的输入端A [15:0]。 Counter COUNT for counting the system clock signal CLK_SYS counting result via the output port Q [15: 0] output, the access comparator Comparator input terminal A [15: 0]. 比较器Comparator对输入端A[15:0]和B [15:0]的数值进行比较,若不相等,则输出信号EQ为低电平,该信号接入触发器FD的使能端CE,禁用触发器FD,输出信号EQ同时接入计数器COUNT的清零端CLR,由于EQ为低电平,计数器COUNT持续计数。 Comparator comparator input terminal A [15: 0] and B: the value [150] is compared, if not equal, a low level output signal EQ, the trigger signal is FD access enable terminal CE, disabling triggers the FD, the output signal EQ at the same time access to clear terminal CLR of counter cOUNT, since EQ is low, the counter cOUNT continues counting. 若相等,则输出信号EQ为高电平,使能触发器FD,在系统时钟CLK_SYS上升沿的触发下,触发器FD的输出信号CLK电平发生反转,同时清空计数器COUNT,使计数器从零开始重新计数。 If equal, the output signal EQ is high, enabling the flip-flop FD, triggered by the rising edge of the system clock CLK_SYS, the output signal CLK of the flip-flop FD level reversed, while empty counter COUNT, the counter from zero start counting again. 如此周期运行,即可得到设定频率的采样时钟信号CLK。 Thus operating cycle, the sampling clock signal to obtain a set frequency CLK.

[0051] 2)参照图5,复位模块Reset包括译码器Decoder和触发器FDR。 [0051] 2) Referring to Figure 5, a decoder reset module comprises a Reset Decoder and triggers FDR. 根据预先设定的地址,由译码器Decoder产生片选信号ctl_clr,接入触发器FDR的时钟输入端口C,在信号ctl_clr的上升沿,DSP芯片电路通过数据线ED [15:0]将数据写入触发器FDR,数据通过输出端口Q输出,即为系统复位信号CLR。 According to the address set in advance, produced by the decoder ctl_clr Decoder chip select signal, the access FDR flop clock input Port C, ctl_clr rising edge of the signal, the DSP chip circuit via a data line ED [15: 0] Data writing trigger FDR, the data output by the Q output port, is the system reset signal CLR. 当DSP芯片电路通过数据线ED [15:0]写数据0时,复位信号CLR变为低电平,光子计数模块Counter对光子脉冲进行计数。 When the DSP chip circuit via a data line ED [15: 0] Write data is 0, the reset signal CLR goes low, the photon counting module counts the pulses Counter photons. 写数据I时,复位信号CLR变为高电平。 Write data I, the reset signal CLR goes high. 清空光子计数模块Counter的计数值。 Empty photon counting of the count value Counter module.

[0052] 3)参照图6,光子计数模块Counter包括计数器Counterl、计数器Counter2、锁存器Latchl、锁存器Latch2、多路数据选择器MUX2。 [0052] 3) Referring to FIG. 6, the photon counting module comprises a counter Counter Counterl, Counter2 counter, latch Latchl, LATCH2 latch, data selector multiplexer MUX2. 采样时钟信号CLK经过二分频后得到时钟信号CLK2,连接到计数器Counterl的计数使能端CE、锁存器Latch2的时钟输入端CLK和多路数据选择器MUX2的选择输入端S,时钟信号CLK2接反相器后连接到计数器Counterf计数使能端CE和锁存器Latchl的时钟输入端CLK。 After the sampling clock signal CLK is divided by two to obtain clock signal CLK2, is connected to the count of the counter Counterl enable terminal CE, a clock input CLK and a latch Latch2 multiplexer MUX2 is data selector selects the input terminal S, the clock signal CLK2 followed by an inverter connected to the counter to make the count Counterf Latchl clock input enable terminal CE and a latch CLK. 光子脉冲信号从输入端CIN同时送入计数器Counterl和Counter2的脉冲输入端C,复位信号CLR连接到计数器Counterl和Counter2的复位端CLR,复位信号CLR接反相器后连接到锁存器Latchl和Latch2的复位端CLR。 Photon pulse signal fed at the counter and Counter2 Counterl pulse input from the input terminal C of CIN, the reset signal CLR is connected to the reset terminal CLR of the counter Counterl and Counter2, followed by the reset signal CLR is connected to the inverters and latch Latchl Latch2 the reset terminal CLR. 当复位信号CLR为低电平,时钟信号CLK2为高电平时,计数器Counterl开始对光子脉冲信号进行计数;当时钟信号CLK2为低电平时,计数器Counterl停止计数,计数值由Latchl锁存输出,计数器Counter2开始对光子脉冲信号进行计数。 When the reset signal CLR is low, the clock signal CLK2 to the high level, the counter starts Counterl photon counting pulse signal; when the clock signal CLK2 is low, Counterl counter stops counting, the count value output from the latch Latchl counter Counter2 start pulse signal photon counts. 当计数器Counterl的复位端为高电平时,清除计数器Counterl的计数值,等到时钟信号CLK2变为高电平时再重新开始计数,如此周期进行。 When the reset terminal of counter Counterl is high, it clears the count value of the counter Counterl, when the clock signal CLK2 to the high level until the count starts again, so cycle. 计数器Counterl和Counter2交替对输入的光子脉冲进行计数,计数结果经过锁存器Latchl和Latch2锁存后,通过多路数据选择器MUX2的输出端口Q[15:0]输出。 And after the counter Counterl Counter2 alternately photon counting pulse input, counting result via latches Latchl Latch2 and latched by data selector multiplexer MUX2 output port Q [15: 0] output. 计数器Counterl和Counter2均为16位计数器,以IMcps光强,最大40ms采样时间为例,平均光子计数值为40000 «216),所以计数器不会溢出。 Counterl counters are 16-bit counter and Counter2 to IMcps light intensity, a maximum sampling time 40ms as an example, an average of 40,000 photon count value «216), the counter will not overflow.

[0053] 4)参照图2、图3,相关通道延迟时间计算模块负责计算每个通道的延迟时间。 [0053] 4) Referring to FIG. 2, FIG. 3, the relevant channel delay time calculation module is responsible for calculating the delay time for each channel. 比例相关器在相关函数的起始段通道间延迟时间按线性规律增长,随相关通道序号的加大,通道间的延迟时间按一定比例增长。 Correlation between the ratio of the initial segment delay passage of time correlation function according to a linear law of growth, increase the number of channels associated with, the time delay between channels increase by a certain percentage. 根据设定的动态范围及相关通道数计算每个通道的延迟时间,依据计算结果设定某些通道连接有乘法器和累加器,其他通道则不连接乘法器和累加器,从而成为按比例间隔提取的相关器结构。 The dynamic range of the set delay time and the relevant channel number of each channel is calculated, based on the calculation result to set certain channel multiplier and accumulator is connected, the other channels are not connected multiplier and accumulator, thus becoming proportionally spaced extracted correlation structure. 因此,相关运算之前,首先需要利用设定的动态范围及通道数N,按照下式计算比例R : Thus, before the correlation operation, we need to use the first set of channels and the dynamic range of the number N, in accordance with the calculated ratio R:

[0054] i? 二exp H [0054] i? Two exp H

LN — \ _·[0055] 则比例相关器第k通道的延迟时间为= Tk=T* RH LN - \ _ · [0055] k is delay time of the channel is related to the ratio = Tk = T * RH

[0056] 但依据上式计算的通道延迟时间大多数情况下不是整数,需要对其取整,这在R值较大的情况下比较容易实现,可是当R值较小时,采用上式计算出的通道延迟时间会产生重复,实际的通道数小于设定的通道数。 [0056] However, based on the calculated channel delay time in most cases is not an integer, rounding need thereof, it is easier to achieve in a large R value, but when the R value is small, is calculated using the formula channel delay time can result in duplicate, the actual number of channels is less than the set number of channels. 针对这种情况,可以采用如图8所示的计算通道延迟时间的方法,既可以保证所需的通道数,又可以得到理想的通道延迟时间。 For this case, the calculation method shown in FIG. 8 channel delay time can be employed, both to ensure that the required number of channels, and can be an ideal channel delay time.

[0057] 参照图8, T为第一个通道的延迟时间,T i为最后通道的延迟时间,N为设定的相关通道数,L为环形缓冲区n[]的长度,j为合并后的通道数,计算结果存放在存储区ChDelay []中。 After [0057] Referring to FIG. 8, T is the delay time of the first channel, T i is the delay time of the last channel, N being the number of channel-related settings, L is a n-ring buffer [] of length, j is combined the number of channels, the calculation result is stored in the storage area ChDelay [] in.

[0058] 例如:设定T =20 U s, T ^lOOOOOu s, N=64时,贝丨」比例R=L 1448,实现的动态范围为5X IO3,得到通道的延迟如下表所示,那么每个通道的延迟时间为Tk =T • ChDelay [k]。 [0058] For example: set T = 20 U s, T ^ lOOOOOu s, N = 64, Shu shell "the ratio R = L 1448, to achieve a dynamic range of 5X IO3, channel delay obtained in the table below, then delay time of each channel is Tk = T • ChDelay [k].

[0059] [0059]

相关通道 线性通道延迟 比例通道延迟 Channel delay related channel linear proportion channel delay

1__ChDelay 丨01=I__ChDelay 丨Ol=I_ 01 = I__ChDelay 1__ChDelay Shu Shu Ol = I_

2 ChDelayf 11=2 ChDelavn 1=2 2 ChDelayf 11 = 2 ChDelavn 1 = 2

3 — ChDelayf21=3__ChDelay[21=3_ 3 - ChDelayf21 = 3__ChDelay [21 = 3_

_4__ChDelavI 31=4__CliUelay|31=4_ _4__ChDelavI 31 = 4__CliUelay | 31 = 4_

5 ChDelav[41=5 CliDe!av[41=5 5 ChDelav [41 = 5 CliDe! Av [41 = 5

6 ChDelay『51=6__ChDeiayr51=6_ 6 ChDelay "51 = 6__ChDeiayr51 = 6_

_7__ChDe1ay[61=7__C'hDelay[61=7_ _7__ChDe1ay [61 = 7__C'hDelay [61 = 7_

_8__ChDelavj~71=8__ChDelay[71=8_ _8__ChDelavj ~ 71 = 8__ChDelay [71 = 8_

9 — ChDelav『引=9__ChDehy「81=9_ 9 - ChDelav "lead = 9__ChDehy" 9_ 81 =

_K)__ChDelayj^Q 1=10__ChDeiaylc)]= 10_ _K) __ ChDelayj ^ Q 1 = 10__ChDeiaylc)] = 10_

_IJ__ChDelavjIOl=I I__ChDelav[101=i I_ _IJ__ChDelavjIOl = I I__ChDelav [101 = i I_

12 一ChDelavH I i=12__ChDelavn IJ=I 3_ 12 a ChDelavH I i = 12__ChDelavn IJ = I 3_

13 — ChDelavM 21= 13__ChDelavli 21= 15_ 13 - ChDelavM 21 = 13__ChDelavli 21 = 15_

61 一ChDelav[601=61 一ChDda.v「()01=3540 61 a ChDelav [601 = 61 ChDda.v a "(01 = 3540)

62 — ChDelayfe 11=62__ChDelay『611=3815_ 62 - ChDelayfe 11 = 62__ChDelay "611 = 3815_

63 一ChDelav 丨621=63__ChDelay『621=3972_ 63 621 = 63__ChDelay a ChDelav Shu "621 = 3972_

64 ChDeiav[631-64 ChDelay [631-5 000 64 ChDeiav [631-64 ChDelay [631-5 000

[0060] 从上表可以看出,比例相关器通道延迟时间在相关函数的起始阶段按照线性规律增长,随着相关通道序号的增加,通道间的延迟时间开始按一定的比例增长,用有限的通道数实现了较大的动态范围,同时在相关曲线的起始阶段保持着较高的时间分辨率。 [0060] As can be seen from the table, the proportion of the relevant channel delay time according to a linear law of growth in the initial stage of the correlation function, associated with the increase of the channel number, the time delay between channel starts a certain percentage of growth, with limited number of channels to achieve a large dynamic range, while maintaining a high time resolution in the initial stage of the correlation curve. [0061] 5)参照图7,在采样时钟信号CLK的上升沿触发DSP芯片电路中断,在中断函数里,DSP芯片电路读取FPGA内光子计数模块Counter输出的光子计数值,存入DSP芯片电路的环形缓冲区n[]内,环形缓冲区的容量为L,从环形缓冲区的起始单元存入起始光子计数值n(0),后续计数值依次存入环形缓冲区的后续单元n(k),当计数值增加到n (LI)时,环形缓冲区存满,下一个计数值n (L)存入存储n(0)的起始单元,将计数值n(0)覆盖掉。 [0061] 5) Referring to FIG. 7, the rising edge of the sampling clock signal CLK DSP chip trigger circuit interrupt, the interrupt function Lane, DSP chip circuit reads the count value of the photon counting module FPGA photon Counter output circuit is stored in DSP chips n the ring buffer [] within the capacity of the ring buffer is L, the cell count value stored in the initial photons n (0) starting from the ring buffer, the subsequent count value is sequentially stored in the ring buffer of the subsequent n units (K), when the count value increases to n (LI), the ring buffer becomes full, the next count value n (L) stored in the memory n (0) of the starter unit, the count value n (0) overwrite . 以此类推,不断循环,DSP内的环形缓冲区实现了移位寄存器的功能。 So, continuous cycle, the ring buffer within the DSP realizes the functions of the shift register.

[0062] 6)参照图7、图9,在采样时钟信号CLK的上升沿触发DSP芯片电路中断,在中断函数里,DSP芯片电路读入新的光子计数值后,按照DSP芯片电路内相关通道延迟时间计算模块计算出的每个通道延迟时间,从环形缓冲区内提取已存储的光子计数值,利用DSP芯片电路的硬件乘法器,与新的光子计数值进行相乘运算,再进行累加,得到每个通道的相关函数值。 After [0062] 6) Referring to FIG 7, FIG 9, the sampling clock signal CLK on the rising edge of the trigger circuit chip DSP interrupt, the interrupt function Lane, DSP chip circuit reads the count value of new photons according to the DSP chip circuitry associated channel each channel delay time calculating module calculates the delay time, the count value of photons extracted from the stored ring buffer using a DSP chip hardware multiplier circuit for multiplication with the new photon count value, and then accumulates, obtained correlation function value for each channel.

[0063] 根据上述相关运算的基本原理,相关函数计算流程如图9所示,图中N为设定的相关通道数,L为环形缓冲区n[]的长度,k为采样次数,i为当前计算的相关通道,数组ChDelay []存放通道的延迟,数组ChData[]存放相关函数值。 [0063] According to the principle of the correlation calculation, correlation function calculation process shown in FIG. 9, FIG set N is the number of the relevant channel, L is a n-ring buffer [] of length, k is the sample number, i is currently calculated channel correlation array ChDelay [] storage channel delay array ChData [] stored correlation function values.

[0064] 在中断函数里,DSP芯片电路执行该相关函数计算流程。 [0064] In the interrupt function Lane, DSP chip circuit for performing the correlation function calculation process. 首先执行k++操作,并判断k是否大于LI,若大于则表明环形缓冲区已存满,此时将k初始化为0,DSP芯片电路读取的新的光子计数值存入环形缓冲区的起始单元n(0),否则DSP芯片电路读取的新的光子计数值存入环形缓冲区的单元n(k)。 K ++ operation is performed first, and determines whether k is greater than LI, if greater than the ring buffer becomes full it indicates that, at this time k is initialized to 0, a new photon count value is read into the DSP chip circuit ring buffer start unit n (0), otherwise the new photonic chip DSP circuit reads the count value stored in the ring buffer means n (k). 然后依据数组ChDelay[]存放的相关通道延迟,求取环形缓冲区单元位置j = k_ChDelay[i],提取已存储计数值n[j],与新的光子计数值n[k]相乘,再进行累加运算,得到相关通道i的相关函数值,并存入数组ChData[i]。 Then based on the array ChDelay [] stored in the associated channel delay, the ring buffer unit obtains the position j = k_ChDelay [i], extracts the stored count value n [j], and the new count value of photons [k] is multiplied by n, then accumulate operations performed to obtain correlation value of the correlation function of the channel i, and stored in the array ChData [i]. 若j〈0,则j+L,假如j = -1,那么j = LI,此时提取计数值n (LI),与新计数值n[k]相乘,如图7所示。 If j <0, the j + L, if j = -1, then j = LI, this time to extract the count value n (LI), and the new count value n [k] is multiplied by, as shown in FIG. 每执行一次中断函数,上述相关函数的计算过程就要重复N次,i从0加到NI,得到N个通道的相关函数值,存入数组ChData []。 Each time an interrupt function, a function of the correlation calculation process is repeated N times is necessary, the NI I 0 was added, to obtain the correlation function values ​​of the N channels, into an array ChData [].

[0065] 例如,计数值n(k)与计数值n(kl)进行相乘运算,再累加到n(k_l)与n(k_2)的乘积上,得到第I通道相关函数值G(T);计数值n(k)与n(0)进行相乘运算,再累加到n(kl)与n(Ll)的乘积上,得到第k通道的相关函数值G(kO。以前述64通道比例自相关运算为例(N=64),环形缓冲区长度为L(L>5000),每个通道的延迟如上表所示,得到每个通道的相关函数值。 [0065] For example, the count value n (k) with the count value n (kl) for multiplication, the product is applied to the tired n (k_l) and n (k_2) to obtain a first I-channel correlation function G (T) ; count value n (k) for multiplication with n (0), tired was added n (kl) and the product of n (Ll), the obtained correlation function G (kO ratio of the k-th channel to the channel 64 Example autocorrelation (N = 64), an annular buffer of length L (L> 5000), the delay of each channel as shown in table, to obtain the correlation function value for each channel.

[0066] 从上述计算过程可以看出,读取新的光子计数值并没有与环形缓冲区内所有已存储的计数值进行相关运算,而只按照数组ChDelay []存储的通道延迟计算出需要的通道位置,再进行相关运算,从而实现了比例相关器的设计。 [0066] As can be seen from the above calculation process, reads the new value and does not count a photon correlation calculation all count values ​​stored in the ring buffer only in accordance with the array ChDelay [] stored in the calculated desired channel delay channel position, then the correlation operation, in order to achieve a ratio related to the design. 上例相关器以64个相关通道实现的动态范围为5X103。 In the embodiment of the correlator 64 implemented relevant channel dynamic range 5X103.

[0067] 为防止溢出,本发明的相关函数值转换成32位浮点格式数存储。 [0067] In order to prevent overflow of the present invention, the correlation function value is converted into 32-bit floating point format number is stored. 以IMcps光强,最大40ms采样时间为例,平均光子计数值为4X104,计数值相乘后最大为1.6X109,32位浮点格式数能表示的最大值为3.4X 1038,那么在溢出前,可以累加(3.4X 1038)/(I. 6X IO9) =2. IX IO29 次,持续时间达2. lX 1029X40ms=8. 5X 1027s=2. 4X 1024 小时,完全满足纳米及亚微米颗粒粒度测量的需求。 In IMcps light intensity, a maximum sampling time 40ms as an example, the average photon count value 4X104, the maximum count value is multiplied by the maximum number 1.6X109,32 bit floating point format can be represented as 3.4X 1038, then before the overflow, may be accumulated (3.4X 1038) / (I. 6X IO9) = 2. IX IO29 times, duration of 2. lX 1029X40ms = 8. 5X 1027s = 2. 4X 1024 hours to fully satisfy nm and submicron particles of a particle size measurement demand.

[0068] 相关运算模块是光子相关器的核心,所实现的功能是对光子计数模块Counter输出的光子计数值进行实时自相关运算。 [0068] photon correlation calculation module is the core of the correlator function is implemented photon counting photon count value Counter output module for real-time autocorrelation. 相关运算模块的前k组通道计算方法如下:[0069]第一通道:G ( T ) =Hon^n1Ii2+-•• ; K calculated before the set channel correlation calculation module are as follows: [0069] a first channel: G (T) = Hon ^ n1Ii2 + - ••;

[0070]第二通道:G (2 T ) =¾¾+]^¾+…+nN_2nN ; [0070] Second passage: G (2 T) = ¾¾ +] ^ ¾ + ... + nN_2nN;

[0071]第三通道:G(3 T ) ^ong+n!^+*** +nN_3nN ; [0071] The third passage: G (3 T) ^ ong + n ^ + *** + nN_3nN;!

[0072]第四通道:G(4 T )=¾¾+]^¾+…+nN_4nN ; [0072] The fourth channel: G (4 T) = ¾¾ +] ^ ¾ + ... + nN_4nN;

Nk Nk

[0073]第 k 通道:(:;(々r) = y. IIiHi,, [0073] k-th channel: (:;. (々R) = y IIiHi ,,

i-0 i-0

[0074] 以上显示和描述了本发明的基本原理和主要特征和本发明的优点。 [0074] The above description and the basic principles and features of this invention and the main advantages of the invention. 本行业的技术人员应该了解,本发明不受上述实施例的限制,上述实施例和说明书中描述的只是说明本发明的原理,在不脱离本发明精神和范围的前提下,本发明还会有各种变化和改进,这些变化和改进都落入要求保护的本发明范围内。 The industry the art will appreciate, the present invention is not limited to the above embodiment, the above-described examples and embodiments described in the specification are only illustrative of the principles of the present invention, without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, changes and modifications which fall within the scope of the claimed invention. 本发明要求保护范围由所附的权利要求书及其等效物界定。 The scope of the invention as claimed by the appended claims and their equivalents.

Claims (7)

1.基于DSP环形缓冲区的比例光子相关器,其特征在于,包括一 FPGA芯片电路、一DSP芯片电路、一计算机,所述DSP芯片电路分别连接所述FPGA芯片电路、所述计算机; 所述FPGA芯片电路包括一采样时间设置模块、一复位模块、一光子计数模块; 所述DSP芯片电路包括一相关通道延迟时间计算模块、一环形缓冲区、一相关运算模块; 所述FPGA芯片电路产生采样时钟信号,并对光子脉冲进行计数; 所述DSP芯片电路通过所述环形缓冲区实现移位寄存器的功能,根据相邻通道延迟时间的比例R,设置每一个通道的延时时间,并通过所述相关运算模块,实现相关函数的运算,并将相关函数传送给所述计算机,所述计算机通过反演算法获得颗粒的粒度分布。 1. The DSP ring buffer based on the ratio of photon correlation, characterized in that it comprises a circuit chip FPGA, a DSP chip circuit, a computer, the DSP circuit chip connected to the FPGA circuit chip, said computer; the FPGA chip circuit comprises a sampling time setting module, a reset module, a photon counting module; DSP chips of the channel correlation circuit comprises a delay time calculating module, a ring buffer, a correlation calculation module; FPGA chip circuit generates the sampling clock signal, and counting photon pulses; the DSP chip via said ring buffer circuit implement the functions of the shift register, a delay time in accordance with the ratio of adjacent channels R, set the delay time for each channel, and by the said correlation calculation module, calculation of the correlation function and the correlation function is transmitted to the computer, the computer to obtain a particle size of particles distributed through the inversion algorithm.
2.根据权利要求I所述的基于DSP环形缓冲区的比例光子相关器,其特征在于:所述采样时间设置模块包括译码器、触发器、计数器和比较器;所述采样时间设置模块通过对系统时钟分频得到采样时钟信号:采样时钟频率等于输入的系统时钟频率除以分频系数,所述计算机根据用户的设置计算出分频系数,并发送给DSP芯片电路,DSP芯片电路再将分频系数写入FPGA芯片电路内部的采样时间设置模块,通过计数器对系统时钟进行计数,并与分频系数进行比较,实现对系统时钟的分频,即可得到预期的采样时钟信号。 The DSP ring buffer based on the ratio of the photon correlator as claimed in claim I, wherein: the sampling time module comprises a decoder, flip-flop, a counter and a comparator; the sampling time module dividing the system clock of the sampling clock signal obtained: system clock frequency equal to the input sampling clock frequency divided by the division factor, the computer calculates the division factor according to user settings, and sent to the DSP chip circuit, then the DSP chip circuit division coefficient writing circuit inside the FPGA chip sampling time setting module, the system clock counting by the counter, and compared with the division factor, to achieve frequency division of the system clock, to give the desired sampling clock signal.
3.根据权利要求2所述的基于DSP环形缓冲区的比例光子相关器,其特征在于:所述复位模块包括译码器和触发器,所述复位模块用于产生系统复位信号,当复位信号为高电平时,清空所述光子计数模块的计数值;当复位信号为低电平时,所述光子计数模块对光子脉冲进行计数。 The DSP ring buffer based on the ratio of the photon correlator as claimed in claim 2, wherein: said module comprises a decoder and reset flip-flop, the reset module for generating a system reset signal when the reset signal is high, the count value of emptying the photon counting module; when the reset signal is low, the photon counting module counts photon pulses.
4.根据权利要求3所述的基于DSP环形缓冲区的比例光子相关器,其特征在于:所述光子计数模块包括两个计数器、两个锁存器和多路数据选择器;在采样时钟信号的驱动下,两个所述计数器交替运行,实现对光子脉冲的无缝计数并将计数结果输出给所述DSP芯片电路。 The DSP ring buffer based on the ratio of photon correlator according to claim 3, wherein: the photon counting module comprises two counters, latches and two multiplexed data selector; sampling clock signal under the driving, two alternate operation of the counter, and outputs the count seamlessly count result of photon pulses to the DSP chip circuit.
5.根据权利要求I至4中任意一项所述的基于DSP环形缓冲区的比例光子相关器,其特征在于:所述DSP芯片电路中的所述相关通道延迟时间计算模块是利用光子相关器的动态范围和通道数,计算相邻通道延迟时间的比例R,然后依据Tk=T .RH计算出每个通道的延迟时间,τ为第I通道的延迟时间。 According to claim I to 4 based on the ratio of photon DSP ring buffer according to any one correlator, wherein: said DSP chip in the relevant channel circuit delay time calculation module using photon correlator the dynamic range and the number of channels, adjacent channels calculated delay time ratio R, and based on the calculated Tk = T .RH delay time for each channel, the delay time [tau] of the I-channel.
6.根据权利要求5所述的基于DSP环形缓冲区的比例光子相关器,其特征在于:所述DSP芯片电路中的所述环形缓冲区实现了移位寄存器的功能,所述DSP芯片电路读取所述光子计数模块输出的光子计数值后,存入所述环形缓冲区,环形缓冲区的容量为L,从环形缓冲区的起始单元存入第O个光子计数值η (O),后续计数值依次存入环形缓冲区的后续单元,当计数值增加到n (LI)时,环形缓冲区存满,下一个计数值n (L)存入存储η (O)的起始单元,将计数值η (O)覆盖掉,以此类推,实现循环。 The DSP ring buffer based on the ratio of the photon correlator as claimed in claim 5, wherein: said ring buffer circuit in the DSP chip to realize the function of a shift register, a read circuit of the DSP chips after taking the count value of photons of the photon counting module output, stored in said ring buffer, the ring buffer capacity is L, the unit stores the count value of photons [eta] O (O) from the beginning of the ring buffer, subsequent count value is sequentially stored in the ring buffer subsequent unit, when the count value increases to n (LI), the ring buffer becomes full, the next starting cell count value n (L) stored in the storage η (O), and the count value of η (O) overwritten, and so on, to achieve circulation.
7.根据权利要求6所述的基于DSP环形缓冲区的比例光子相关器,其特征在于:所述DSP芯片电路内的所述相关运算模块,按照所述相关通道延迟时间计算模块预先计算的通道延迟时间,提取所述环形缓冲区内相应单元存储的光子计数值,利用硬件乘法器,与新计数值进行乘法运算,再进行累加,得到每个通道的相关函数值,并将结果转换成32位浮点格式数,通过USB接口传输给所述计算机,所述计算机通过反演算法,得到颗粒的粒度分布。 The DSP ring buffer based on the ratio of the photon correlator as claimed in claim 6, wherein: the correlation calculation module within the DSP chip circuit, the calculation module according to a pre-computed path to the associated channel time delay delay time, extracting the photon count value stored in the respective ring buffer units, using the hardware multiplier, multiplied with the new counter value, and then accumulates the obtained correlation function value for each channel, and converts the result into a 32 bit floating point formats, USB interface to transfer to the computer, the computer through inversion algorithm, a particle size distribution of the particles.
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WEI LIU: "Design of Multiple-Tau Photon Correlation System Implemented by FPGA", 《ICESS2008》 *
WEI LIU: "The Implement of Single Input Multiple Output Shift Register for Photon Correlator", 《PHOTONICS AND OPTOELECTRONICS》 *
成艳亭: "《山东理工大学硕士学位论文》", 19 October 2009 *
马玉良: "《济南大学硕士学位论文》", 24 August 2011 *

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103873042A (en) * 2012-12-17 2014-06-18 快捷半导体(苏州)有限公司 Delay method, delay circuit and integrated circuit
CN103873042B (en) * 2012-12-17 2017-02-08 快捷半导体(苏州)有限公司 Delay method, delay circuit and integrated circuit
CN104792670A (en) * 2015-04-09 2015-07-22 华南师范大学 FPGA (field programmable gate array)-based multiplexing photon correlator
CN104792670B (en) * 2015-04-09 2018-04-03 华南师范大学 A kind of multiplexing photon correlator based on field programmable gate array

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