CN1835125A - 恢复硬件的设备和方法 - Google Patents
恢复硬件的设备和方法 Download PDFInfo
- Publication number
- CN1835125A CN1835125A CNA2006100595008A CN200610059500A CN1835125A CN 1835125 A CN1835125 A CN 1835125A CN A2006100595008 A CNA2006100595008 A CN A2006100595008A CN 200610059500 A CN200610059500 A CN 200610059500A CN 1835125 A CN1835125 A CN 1835125A
- Authority
- CN
- China
- Prior art keywords
- hardware
- fuse
- deletion
- reorientation
- abist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
- G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0407—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals on power on
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1208—Error catch memory
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Retry When Errors Occur (AREA)
Abstract
Description
Claims (22)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/079,816 | 2005-03-14 | ||
US11/079,816 US7529997B2 (en) | 2005-03-14 | 2005-03-14 | Method for self-correcting cache using line delete, data logging, and fuse repair correction |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1835125A true CN1835125A (zh) | 2006-09-20 |
CN1835125B CN1835125B (zh) | 2011-08-31 |
Family
ID=36970697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2006100595008A Active CN1835125B (zh) | 2005-03-14 | 2006-03-13 | 在具有高速缓存的smp计算机系统中恢复硬件的方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7529997B2 (zh) |
JP (1) | JP5030443B2 (zh) |
CN (1) | CN1835125B (zh) |
TW (1) | TWI387972B (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103745752A (zh) * | 2014-01-09 | 2014-04-23 | 上海华虹宏力半导体制造有限公司 | 存储器内建自测方法以及存储器错误检查方法 |
CN104516832A (zh) * | 2013-10-08 | 2015-04-15 | 国际商业机器公司 | 操作数据处理系统的方法、数据处理系统以及处理器 |
CN104572335A (zh) * | 2014-05-22 | 2015-04-29 | 上海兆芯集成电路有限公司 | 多核数据阵列功率选通恢复机制 |
CN105427893A (zh) * | 2014-09-11 | 2016-03-23 | 爱思开海力士有限公司 | 存储器件及包括存储器件的存储系统 |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7312396B1 (en) * | 2004-03-13 | 2007-12-25 | Protectconnect, Inc. | Universal electrical wiring component |
US20070022250A1 (en) * | 2005-07-19 | 2007-01-25 | International Business Machines Corporation | System and method of responding to a cache read error with a temporary cache directory column delete |
US20090031090A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Apparatus and method for fast one-to-many microcode patch |
US20090031109A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Apparatus and method for fast microcode patch from memory |
US20090031108A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Configurable fuse mechanism for implementing microcode patches |
US20090031110A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Microcode patch expansion mechanism |
US20090031103A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Mechanism for implementing a microcode patch during fabrication |
US20090031121A1 (en) * | 2007-07-24 | 2009-01-29 | Via Technologies | Apparatus and method for real-time microcode patch |
GB2497030B (en) | 2010-09-22 | 2018-07-25 | Hewlett Packard Development Co | Method and system for performing system maintenance in a computing device |
US20150058564A1 (en) * | 2013-08-21 | 2015-02-26 | Via Technologies, Inc. | Apparatus and method for extended cache correction |
US9223715B2 (en) | 2013-08-21 | 2015-12-29 | Via Alliance Semiconductor Co., Ltd. | Microprocessor mechanism for decompression of cache correction data |
US9348690B2 (en) | 2013-08-21 | 2016-05-24 | Via Alliance Semiconductor Co., Ltd. | Correctable configuration data compression and decompression system |
TWI552068B (zh) * | 2013-08-21 | 2016-10-01 | 上海兆芯集成電路有限公司 | 組態資料的處理裝置及方法 |
US9524241B2 (en) | 2014-05-22 | 2016-12-20 | Via Alliance Semiconductor Co., Ltd. | Multi-core microprocessor power gating cache restoral mechanism |
US9665490B2 (en) * | 2014-05-22 | 2017-05-30 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method for repairing cache arrays in a multi-core microprocessor |
US9606933B2 (en) | 2014-05-22 | 2017-03-28 | Via Alliance Semiconductor Co., Ltd. | Multi-core apparatus and method for restoring data arrays following a power gating event |
KR20160091688A (ko) * | 2015-01-26 | 2016-08-03 | 에스케이하이닉스 주식회사 | 포스트 패키지 리페어 장치 |
US9916195B2 (en) | 2016-01-12 | 2018-03-13 | International Business Machines Corporation | Performing a repair operation in arrays |
US9983261B2 (en) | 2016-06-01 | 2018-05-29 | International Business Machines Corporation | Partition-able storage of test results using inactive storage elements |
US11150971B1 (en) | 2020-04-07 | 2021-10-19 | International Business Machines Corporation | Pattern recognition for proactive treatment of non-contiguous growing defects |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07182238A (ja) * | 1993-11-01 | 1995-07-21 | Sgs Thomson Microelectron Inc | 欠陥データ無効化回路及び方法 |
JP3235418B2 (ja) * | 1995-07-28 | 2001-12-04 | 株式会社日立製作所 | 記憶制御装置 |
US6832329B2 (en) * | 2001-02-08 | 2004-12-14 | International Business Machines Corporation | Cache thresholding method, apparatus, and program for predictive reporting of array bit line or driver failures |
CN1380605A (zh) | 2001-04-11 | 2002-11-20 | 英属维京群岛盖内蒂克瓦耳有限公司 | 以错误分布的分割表格修补记忆体的架构及方法 |
US7047466B2 (en) * | 2002-06-03 | 2006-05-16 | International Business Machines Corporation | Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing |
JP4001516B2 (ja) * | 2002-07-05 | 2007-10-31 | 富士通株式会社 | 縮退制御装置及び方法 |
JP3931757B2 (ja) * | 2002-07-26 | 2007-06-20 | 日本電気株式会社 | 共有キャッシュメモリ障害処理方式 |
-
2005
- 2005-03-14 US US11/079,816 patent/US7529997B2/en active Active
-
2006
- 2006-03-07 TW TW095107648A patent/TWI387972B/zh not_active IP Right Cessation
- 2006-03-10 JP JP2006066476A patent/JP5030443B2/ja not_active Expired - Fee Related
- 2006-03-13 CN CN2006100595008A patent/CN1835125B/zh active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104516832A (zh) * | 2013-10-08 | 2015-04-15 | 国际商业机器公司 | 操作数据处理系统的方法、数据处理系统以及处理器 |
CN103745752A (zh) * | 2014-01-09 | 2014-04-23 | 上海华虹宏力半导体制造有限公司 | 存储器内建自测方法以及存储器错误检查方法 |
CN104572335A (zh) * | 2014-05-22 | 2015-04-29 | 上海兆芯集成电路有限公司 | 多核数据阵列功率选通恢复机制 |
CN105427893A (zh) * | 2014-09-11 | 2016-03-23 | 爱思开海力士有限公司 | 存储器件及包括存储器件的存储系统 |
Also Published As
Publication number | Publication date |
---|---|
JP5030443B2 (ja) | 2012-09-19 |
JP2006260562A (ja) | 2006-09-28 |
US7529997B2 (en) | 2009-05-05 |
US20060203578A1 (en) | 2006-09-14 |
TW200705451A (en) | 2007-02-01 |
TWI387972B (zh) | 2013-03-01 |
CN1835125B (zh) | 2011-08-31 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20171206 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171206 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |