CN1830017A - Delay time correction circuit, video data processing circuit, and flat display device - Google Patents
Delay time correction circuit, video data processing circuit, and flat display device Download PDFInfo
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Abstract
The present invention is applied to, for example, a liquid crystal display device having a driving circuit integrally formed on an insulating substrate, and makes it possible to effectively avoid a variation in delay time in a logical circuit using TFTs or the like by inserting dummy data (DD) into input data (D1) and forcedly switching the logical level of the input data (D1) at a predetermined timing during a quiescent period (T2) in which the input data is held at a constant logical level.
Description
Technical field
The present invention relates to a kind of time delay of correcting circuit, video data treatment circuit and panel display apparatus, it can be applicable to for example have the liquid crystal indicator that is integrally formed in the driving circuit on the insulated substrate.The present invention is by will empty data (dummy data) inserting in the input data and forcing to switch the logic level of input data, can avoid using change the time delay in the logical circuit of TFT etc.
Background technology
In recent years, it is whole integrated and be configured in liquid crystal indicator on the glass substrate to have proposed a kind of driving circuit that will be used for display panels, wherein glass substrate is for constituting the insulated substrate of display panels, and described liquid crystal indicator is as the panel display apparatus that is used for such as the portable terminal of mobile phone and PDA.
More specifically, this liquid crystal indicator has: by the display part that the pixel that is arranged in matrix form forms, each pixel is made up of liquid crystal cells; Low temperature polycrystalline silicon TFT (thin film transistor (TFT)), it is the switchgear of liquid crystal display; And memory capacitance.Described liquid crystal indicator is configured to drive this display part by a plurality of driving circuits that utilization is arranged on peripheral place, this display part and assigns to show various images.
This liquid crystal indicator be configured to import in succession according to raster scan order, represent that the gradation data of each pixel grey scale (gradation) is separated into the gradation data that for example is used for odd-numbered line and even number line, and utilization is separately positioned on above the described display part and the following horizontal drive circuit that is used for odd-numbered line and even number line, drive this display part according to these gradation datas that are used for odd-numbered line and even number line, thereby layout line pattern effectively in this display part, and pixel is arranged in meticulous pattern.
In order in each horizontal drive circuit, gradation data to be handled, a plurality of inventions of arrangement about the gradation data of input liquid crystal indicator have been proposed, for example Japanese Patent Application Publication No.Hei 10-17371 and Hei 10-177368.
This logical circuit that is applied to the use low temperature polycrystalline silicon TFT of liquid crystal indicator has following problem: if input value remains on the L level for a long time, then along with the rising of logic level subsequently, time delay is elongated, thereby becomes according to the length near the logic level of front time delay.
More specifically, in this logical circuit, as shown in figs. 1 and 2, therein during the period T 1 of the logic level of gradation data D1 with the dutycycle switching of 50 (%), if be transfused in the level shifter 1 with the synchronous input data D1 (Fig. 2 (B)) of major clock MCK (Fig. 2 (A)) so that convert the input data D1 of 0 to 3 (V) amplitude the output of to 0 to 6 (V), then time delay tD approximate be constant.On the contrary, shown in period T 2, if the logic level of gradation data D1 remains on the L level for a long time, td1 time delay so following closely grows (Fig. 2 (C)) than td time delay in the period T 1.
Therefore, as shown in Figure 3, in the situation that each level shift (Fig. 3 (B1) and 3 (B2)) with gradation data D1 also latchs by period of the day from 11 p.m. to 1 a.m clock SCK (Fig. 3 (A)), if gradation data is the data that provide with high transmission speed, then during the period T 1 that each the logic level of gradation data D1 is switched with the dutycycle of 50 (%) therein, can pass through period of the day from 11 p.m. to 1 a.m clock SCK (Fig. 3 (B1) and 3 (C1)) the output data D2A of latch level shift unit 1 correctly, but follow closely after the vertical blanking cycle VBL, for example the output data D2 of latch level shift unit 1 (Fig. 3 (B2) and 3 (C2)) correctly.
In the situation of correct latch data, in liquid crystal indicator, if gradation data is separated into even number line and odd-numbered line so that drive high-resolution display part as described above, then follow closely after the vertical blanking cycle, pixel will be driven by wrong gray scale partly.In addition, if for example will show the white portion with window shape under black background, then when beginning to scan white portion, same pixel also can be driven by wrong gray scale.In addition, in liquid crystal indicator, for example according to the corresponding 6 bit parallel form input gray level data D1 of the number of grey levels of display part, thereby in each of gradation data, all change time delay.Thereby misdata only might be latched specific for gradation data, thereby the image that will show becomes and visually obviously do not meet needs.
Summary of the invention
In view of said circumstances proposes the present invention, the invention is intended to propose: a kind of time delay correcting circuit, it can avoid using change the time delay in the logical circuit of TFT etc. effectively; A kind of video data treatment circuit that uses this of correcting circuit time delay; And a kind of panel display apparatus that uses this video data treatment circuit.
In order to solve described problem, apply the present invention to correcting circuit time delay that is used for data processing circuit, this data processing circuit is used for processing and has the input data of quiescent period (quiescentperiod), during described quiescent period, the input data are to keep constant logic level in the constant cycle is during constant, and in this correcting circuit, the predetermined instant during described quiescent period will have the empty data of the logic level opposite with this constant level and insert in the input data time delay.
According to structure of the present invention, if the present invention is applied to correcting circuit time delay that is used for data processing circuit, then compare with the situation of not inserting empty data at all, can make the change of the time delay in the logic level subsequently shorter, thereby can avoid using change the time delay in the logical circuit of TFT etc. effectively, wherein said data processing circuit is used to handle the input data with quiescent period, during described quiescent period, the input data are to keep constant logic level in the constant cycle is during constant, and in this correcting circuit, the predetermined instant during described quiescent period will have the empty data of the logic level opposite with this constant level and insert in the input data time delay.
In addition, the present invention is applied to a data processing circuit that is used to handle the input data, wherein said input data have quiescent period, during described quiescent period, the input data are to keep constant logic level in the constant cycle is during constant, and in this data processing circuit, the predetermined instant during described quiescent period will have the empty data of the logic level opposite with described constant logic level and insert in the input data.
According to structure of the present invention, can avoid using change the time delay in the logical circuit of TFT etc. effectively, thereby can when carrying out data processing, avoid effectively because of changing the multiple influence that causes time delay.
In addition, the present invention is applied to a panel display apparatus, thus by the predetermined instant during the horizontal blanking cycle of gradation data will have with the described horizontal blanking cycle during the empty data of the opposite logic level of logic level insert in the gradation data to come gradation data is handled.
According to structure of the present invention, can avoid using change the time delay in the logical circuit of TFT etc. effectively, thereby can when showing required image, avoid effectively because of changing the multiple influence that causes time delay.
According to the present invention, a kind of video data treatment circuit and panel display apparatus can be provided, the two can both avoid using change the time delay in the logical circuit of TFT etc. effectively.
Description of drawings
Fig. 1 explains block scheme used when changing time delay.
Fig. 2 explains sequential chart used when changing time delay.
Sequential chart shown in Figure 3 is represented the relation between vertical blanking cycle and time delay.
Fig. 4 is for explaining according to the time delay of the present invention of used block scheme during correction principle.
Employed sequential chart when Fig. 5 is a correction principle shown in the key drawing 4.
Sequential chart shown in Figure 6 is represented the relation between vertical blanking cycle and time delay.
Sequential chart shown in Figure 7 is used to explain the change of the situation following time delay that reduces in time delay.
Block scheme shown in Figure 8 is represented the liquid crystal indicator according to the embodiment of the invention 1.
String in the liquid crystal indicator shown in the block scheme presentation graphs 8 shown in Figure 9 arrives and change-over circuit and peripheral structure.
String shown in the wiring diagram presentation graphs 9 shown in Figure 10 to and change-over circuit in latch cicuit.
String shown in the wiring diagram presentation graphs 9 shown in Figure 11 to and change-over circuit in downconverter.
Used synoptic diagram when Figure 12 changes for explaining time delay among the embodiment 2.
Figure 13 explains sequential chart used when change the time delay shown in Figure 12.
Embodiment
Below, describe embodiments of the invention with reference to the accompanying drawings in detail.
(1) time delay correction principle
Fig. 4 is different from Fig. 1 the time delay of the present invention of used block scheme during correction principle for explaining.According to this correction principle, in to the data processing circuit of handling with the input data that keep constant logic level in the constant cycle is during constant, the predetermined instant during incoming level keeps the cycle of constant logic level will have the empty data of the logic level opposite with described constant logic level and insert in the input data.In addition, the input data are the cycles of not carrying out the mass data transmission therebetween with the cycle that keeps constant logic level in the constant cycle is during constant, such as the horizontal blanking cycle in the video data.Below, as required, this cycle is called quiescent period.
More specifically, if described data processing circuit for example is the level shifter 1 shown in Fig. 5, then will insert from the empty data DD that logic L level raises the gradation data D1 during horizontal blanking period T 2 (wherein gradation data D1 is to keep constant logic level in the constant cycle is during constant), the input data D1 (from 0 to 3 (V) amplitude correction to 0 is to 6 (V) amplitude) that wherein said level shifter 1 is proofreaied and correct and major clock MCK (Fig. 5 (A)) is synchronous also exports output data D2 (Fig. 5 (B) and 5 (D)).Thereby, by for example OR circuit 4 (Fig. 5 (C)), will insert among the gradation data D1 based on the reset pulse HDrst of empty data DD.
Therefore, according to this correction principle, compare with the situation of not inserting empty data DD at all, make the time delay dt1 when rising shorter, thereby solved the problem that become with the length near the logic level of front time delay near the logic level of horizontal blanking period T back.More specifically, if insert empty data DD in this manner, then can force the logic level of input data to be switched, and compare with the situation of not inserting empty data DD at all, can make the logic level of importing data therebetween keep the cycle of logic L level shorter, thereby can reduce to import the change of the time delay in the serial data of data D1.Therefore, can avoid effectively latching of misdata or the like.
More specifically, as with as shown in Fig. 6 of Fig. 3 contrast, in the situation of this logical circuit output being sampled with period of the day from 11 p.m. to 1 a.m clock SCK (Fig. 6 (A)), insert empty data DD during the horizontal blanking cycle in vertical blanking cycle VBL, the time delay of the output data D2 when thereby the logic level that can make vertical blanking cycle VBL back rises is shorter, and can similarly sample to output data D2 constantly with the situation in effective video cycle and latch (Fig. 6 (B1) is to 6 (C2)).Thereby, may with the rising of vertical blanking cycle VBL correspondingly with correct gray scale display pixel.In addition, continue several lines and be elevated in the situation of white level, perhaps in the situation that a certain certain bits after remaining on several lines of L level continuously, in the multidigit raises, can correctly latch input data D1 at black level.Therefore, liquid crystal indicator is suitable for correctly showing the gray scale of each pixel.
In conjunction with in Fig. 2 change of described time delay,, then in the decline of the logic level that has raise, can postpone in the above if logic level raises immediately after input data D1 keeps logic L level for a long time.But, studying in great detail of the logic level rising moment shown, if input data D1 keeps logic L level for a long time, then compare with Fig. 3, as shown in Figure 7, become shorter, this and descend opposite (Fig. 7 (A) is to 7 (C2)) constantly in the time delay constantly of rising.Thereby, if import the moment of the sampling instant of data D1 before being set to switch near logic level, and if the phase margin that is used to sample less, deal with data correctly under situation about changing with the delay associated time constantly of rising then.
But, even if in the situation relevant with this set, if during quiescent period, insert empty data according to correction principle, then may be along the change of the correction for direction time delay that reduces with the described rising delay associated time, thus for example liquid crystal indicator is suitable for correctly proofreading and correct the gray scale of each pixel.
(2) structure of embodiment 1
Block scheme shown in Figure 8 is represented the liquid crystal indicator according to the embodiment of the invention 1.In liquid crystal indicator 11, driving circuit shown in Fig. 8 is integrally formed on the glass substrate, this glass substrate is the insulated substrate of display part 12, and the TFT that is made by low temperature polycrystalline silicon forms the following driving circuit that will describe, such as horizontal drive circuit and timing generator.
Display part 12 has the pixel that formed by liquid crystal cells respectively, as the TFT and the memory capacitance of the switchgear of liquid crystal cells, and have rectangular shape, wherein these pixels are arranged in matrix form.
Vertical drive circuit 13 drives the gate line of display part 12 in response to each timing signal of timing generator 14 output, thereby is arranged on pixel in the display part 12 with the selection of behavior unit sequence ground.Horizontal drive circuit 15O and 15E be separately positioned on the top of display part 12 and below, and will by go here and there also the gradation data Dod that is used for odd-numbered line and even number line of (SP) change-over circuit 16 output and Dev sequentially circulate latch after, each is latched output combine digital-analog-converted, and use the drive signal that is produced to drive the corresponding signal line of display part 12.In this manner, horizontal drive circuit 15O and 15E drive the odd number signal wire and the even signal line of display part 12 respectively, and based on gradation data Dod and Dev and each pixel of selecting by vertical drive circuit 13 is set to certain gray scale.
Each reference signal that timing generator 14 provides according to the last stage arrangement from liquid crystal indicator 11 produces and exports necessary each timing signal of operation of liquid crystal indicator 11.The gradation data D1 that this is gone here and there and change-over circuit 16 will be exported from the last stage arrangement of liquid crystal indicator 11 is separated into gradation data Dod and the Dev that is used for odd-numbered line and even number line, and output gray level data Dod and Dev.Gradation data D1 is the data of the gray scale of each pixel of expression, and is formed by video data, and described video data is made up of continuous red, the blue and green data of the raster scan order of arranging corresponding to the pixel in the display part 12.
Block scheme shown in Figure 9 is represented to go here and there and change-over circuit 16 and relative structure.This is gone here and there and change-over circuit 16 utilizes level shifter 21 amplitude of gradation data D1 from 0 to 3 (V) to be converted to the amplitude of 0 to 6 (V), the gradation data D1 that latch cicuit 22 and 23 is alternately latched obtained is so that be separated into gradation data D1 gradation data Dod and the Dev that is used for odd-numbered line and even number line, utilize downconverter 24 and 25 to recover original amplitude, and export gradation data Dod and the Dev that is generated.In this way, this is gone here and there and change-over circuit 16 amplifies and handle the amplitude of gradation data D1 by the level shift that is undertaken by level shifter 21, thereby will be separated into the gradation data that is used for two systems reliably with the gradation data D1 that high transfer rate provides.
In the processing of relevant gradation data D1, go here and there and change-over circuit 16 is provided with OR circuit 27 at the output stage place of level shifter 21, and during the horizontal blanking cycle of gradation data D1, empty data DD is inserted among the gradation data D1 by OR circuit 27.Thereby liquid crystal indicator 11 is suitable for preventing the time delay because of gradation data D1 keeps the L level to cause for a long time from changing, thereby can correctly gradation data D1 be latched in the latch cicuit 22 and 23 of back.In addition, liquid crystal indicator 11 is configured to insert empty data DD in the output stage of level shifter 21 in this manner, this is because gradation data D1 can be only because do not change just latching by mistake the time delay of taking place in level shifter 21.
Thereby, be configured to during each horizontal blanking cycle timing generator (TG) 14 to 27 outputs of OR circuit and a reset pulse HDrst is provided, by this reset pulse HDrst rising signal level.
Wiring diagram shown in Figure 10 is represented latch cicuit 22.Latch cicuit 22 and 23 is similarly designed, except be provided for controlling their the sampling pulse sp and xsp that latch timing respectively from timing generator 14.Below, will only relate to the structure of latch cicuit 22, and omit description latch cicuit 23.In addition, express reset pulse rst, but omit description it.
In latch cicuit 22, sampling pulse sp is imported in the phase inverter 31, thereby produces the inversion signal of sampling pulse sp.In latch cicuit 22, with gradation data D1 input inverter 32, this phase inverter 32 links to each other with negative supply VSS with positive supply VDD respectively with N-channel MOS transistor Q2 by P channel MOS transistor Q1, wherein this P channel MOS transistor Q1 switches to ON (conducting) state in response to sampling pulse sp, and this N-channel MOS transistor Q2 switches to the ON state in response to the inversion signal of the latch pulse sp that exports from phase inverter 31.The output terminal of phase inverter 32 is connected with the output terminal of phase inverter 33, phase inverter 33 is connected to positive supply VDD and negative supply VSS by P channel MOS transistor Q3 and N-channel MOS transistor Q4 respectively, wherein this P channel MOS transistor Q3 switches to the ON state in response to the inversion signal of sampling pulse sp, this N-channel MOS transistor Q4 switches to the ON state in response to sampling pulse sp, these phase inverters 33 are connected with phase inverter 34 with 32 output, and the input end of phase inverter 34 is connected with the input end of phase inverter 33 is public.In this manner, latch cicuit 22 constitutes a latch units, thereby latchs gradation data D1 in response to sampling pulse sp.
In addition, in latch cicuit 22, the output of phase inverter 34 is provided for phase inverter 35, this phase inverter 35 is connected with negative supply VSS with positive supply VDD with N-channel MOS transistor Q6 by P channel MOS transistor Q5 respectively, wherein this P channel MOS transistor Q5 switches to the ON state in response to the inversion signal of sampling pulse sp, and this N-channel MOS transistor Q6 switches to the ON state in response to sampling pulse sp.In addition, the output terminal of phase inverter 35 is connected with the output terminal of phase inverter 36, phase inverter 36 is connected with negative supply VSS with positive supply VDD with N-channel MOS transistor Q8 by P channel MOS transistor Q7 respectively, wherein this P channel MOS transistor Q7 switches to the ON state in response to sampling pulse sp, this N-channel MOS transistor Q8 switches to the ON state in response to the inversion signal of sampling pulse sp, and these phase inverters 35 are connected with the output terminal of phase inverter 37 with 36 output terminal, and the input end of phase inverter 37 is connected with the input end of phase inverter 36 is public.In latch cicuit 22, the output of phase inverter 37 is output by impact damper 38.In this manner, latch cicuit 22 output is gradation data Dod1 and the Dev1 of 0 to 6 (V) by gradation data D1 being separated into the amplitude that odd-numbered line and even number line form respectively.
Wiring diagram shown in Figure 11 is represented downconverter 24. Downconverter 24 and 25 is configured in the same manner, except their handled data differences.Below, will only relate to the structure of latch cicuit 24, and omit description latch cicuit 25.
Particularly, level shifter 42 is configured to: make P channel MOS transistor Q11 be connected with-3 (V) negative supply VSS2 with 6 (V) positive supply VDD2 respectively with the series circuit of N-channel MOS transistor Q14, and the drain electrode output terminal of P channel MOS transistor Q11 and Q13 is connected respectively with the grid of N-channel MOS transistor Q14 and Q12 with series circuit and the P channel MOS transistor Q13 of N-channel MOS transistor Q12.In addition, the output of phase inverter 41 is directly inputted to P channel MOS transistor Q11, and is imported into another P channel MOS transistor Q13 via phase inverter 47.Level shifter 42 is by the drain electrode output of impact damper 48 output P channel MOS transistor Q13, thereby output is in level the gradation data Dod and the Dev of displaced condition.
(3) operation of embodiment 1
According to said structure, in liquid crystal indicator 11 (Fig. 8), by going here and there and change-over circuit 16, to be separated into gradation data Dod and the Dev that is used for even number line and odd-numbered line according to the gradation data D1 of raster scan order input, and, drive the signal wire of the even number line and the odd-numbered line of display part 12 respectively by horizontal drive circuit 15O and 15E according to the gradation data Dod and the Dev that are used for even number line and odd-numbered line.In response to the corresponding timing signal of gradation data D1, drive the gate line of display part 12 by vertical drive circuit 13, thereby with the pixel of its signal wire in the selection display part 12, behavior unit sequence ground by horizontal drive circuit 15O and 15E driving, therefore on display part 12, show image based on gradation data D1, layout line pattern effectively in display part 12 is so that be arranged in meticulous pattern with pixel.
In liquid crystal indicator 11, during gradation data D1 being separated into the gradation data Dod that is used for two systems and Dev (Fig. 9), amplitude by level shifter 21 amplification gradation data D1, and gradation data D1 is separated into the data that are used for two systems, thereby is separated into gradation data Dod and the Dev that is used for two systems reliably with the gradation data D1 that provides with the corresponding high transfer rate of the resolution of display part 12.
During this is handled, in liquid crystal indicator 11, because latch cicuit 22 and 23 alternately latchs gradation data D1 gradation data D1 is separated into gradation data Dod and the Dev that is used for two systems, and owing to comprise and going here and there and the driving circuit of change-over circuit 16 is integrally formed on the glass substrate (this glass substrate is the insulated substrate of display part 12 and is made by low temperature polycrystalline silicon), so if each of gradation data remains on the L level for a long time, when then after logic level rising subsequently, descending, increase time delay, thereby latch cicuit 22 and 23 becomes and can not correctly latch gradation data D1.On the contrary, reduce time delay when logic level rises, and in this case, latch cicuit 22 and 23 also becomes and can not correctly latch gradation data D1, and this depends on actual conditions.
For this reason, in the present embodiment, the gradation data (importing data during the described quiescent period) that has the input data of quiescent period for conduct to keep constant logic level in the constant cycle is during constant, as the predetermined instant during the horizontal blanking cycle of this quiescent period, the empty data DD that the OR circuit 27 (Fig. 5 and 6) at the output stage place by being arranged on level shifter 21 will have the logic level opposite with the constant logic level of gradation data inserts among the gradation data D1.
Thereby, in liquid crystal indicator 11, compare with the situation of not inserting empty data DD at all, change the time delay the when logic level after can the elimination of level blanking cycle rises, thus can guarantee time delay with therebetween with the anti-phase periodic group of the dutycycle that is different from 50 (%) seemingly with logic level.Thereby present embodiment can avoid using change the time delay in the logical circuit of TFT etc. effectively.In addition, as the liquid crystal indicator that is used for the data processing circuit of video data, can effectively avoid based on the demonstration that changes the wrong gray scale that causes because of time delay.
More specifically, in liquid crystal indicator 11, when the logic level after vertical blanking raises, the switching delay associated time that can proofread and correct and enter the gradation data D1 of latch cicuit 22 and 23 changes, thereby latch cicuit 22 and 23 can according to the situation in the effective video cycle gradation data D1 that similarly regularly samples, and gradation data D1 correctly is separated into gradation data Dod and the Dev that is used for two systems.Thereby, can with the rising of vertical blanking cycle VBL correspondingly with correct gray scale display pixel.In addition, continue to count row and be elevated in the situation of white level at black level, and in the situation of the rising after the capable maintenance of consecutive numbers L level of a certain certain bits in multidigit, can correctly latch input data D1, thereby this liquid crystal indicator is suitable for correctly showing the gray scale of each pixel.
In the trimming process of relevant time delay, can in time-axis direction, amplify the processing nargin of the latch among each horizontal drive circuit 15O and the 15E, thereby liquid crystal indicator 11 can stably operate so that show required image reliably.
(4) advantage of embodiment 1
According to said structure,, can avoid using change the time delay in the logical circuit of TFT effectively by empty data DD being inserted into as among the gradation data D1 of input data and force the logic level of gradation data D1 to be switched.Thereby, the described processing of video data is suitable for processing video data correctly, thereby liquid crystal indicator can show required image with correct gray scale.
In addition, when handling as the gradation data of video data, by during each horizontal blanking cycle, inserting empty data DD, change that can the time in corrective delay, and when the back to back logic level of vertical blanking week after date rises and after logic level descends cycle of several row processing video data correctly during back to back logic level rising.
(5) embodiment 2
Viewpoint according to changing by the time delay of inserting during quiescent period in the logical circuit that empty data can prevent to use TFT is configured to the foregoing description 1 to prevent to increase with the logic level decline delay associated time of horizontal blanking cycle back by insert empty data during the horizontal blanking cycle.
On the contrary, as in conjunction with time delay correction principle described, for the logic level in the logical circuit that uses TFT that raises, the situation that descends with logic level is opposite, utilize a kind of like this structure (when wherein before the logic level of input data is rising, keeping constant value in the back to back constant cycle, reduce time delay and during quiescent period, insert empty data) to prevent and reduce the delay associated time this time delay and change.
In order to check advantage, in structure shown in Figure 9, by stopping to provide reset pulse HDrst to stop to insert empty data, so that in black surround, show square white according to the structure of embodiment 1 based on this understanding.At this moment, shown in the arrow A among Figure 12, with square white portion of state demonstration of an outstanding pixel on the horizontal direction of scanning beginning one side.
In addition, when the waveform that utilizes the sampling pulse sp trigger during this state to the output data D27 of OR circuit 27 examines, observe and stretch out a locations of pixels place in the horizontal direction, the rising of logic level shifts to an earlier date constantly, therefore former should being latched during the logic H of back to back pixel level in the pixel that latchs during the logic L level.
According to this discovery, when when switching input data D1, observing waveform, confirm as shown in Figure 13, if the logic level of input data keeps constant value for a long time, then only have with the rising of the corresponding logic level of next pixel j+1 in advance constantly, but it descends and changes (Figure 13 (B1) is to 13 (C2)) constantly.In Figure 13, symbol 2sp (Figure 13 (A)) expression is used for the generation reference signal of latch pulse sp and xsp, and its cycle is the twice in the cycle of each the latch pulse sp of input latch circuit 22 and 23 and xsp.
Thereby, find that the structure shown in Fig. 9 is a kind of like this structure: it inserts empty data during quiescent period, and prevent to use change the time delay in the logical circuit of TFT, change wherein said time delay no thanks to decline delay associated time with logic level increases and produces, but owing to the rising delay associated time with logic level reduces to produce.
Thereby, according to present embodiment, verified as above face in conjunction with time delay correction principle described like that, even can prevent change time delay that reduces to cause owing to the rising delay associated time reliably with logic level.
(6) other embodiment
In the description to each embodiment, relate to the situation of inserting empty data at the output stage place of level shifter in front, but the invention is not restricted to this example.Thereby, also can insert empty data at the input side of level shifter even when under with much higher speed, handling the change of time delay in the gradation data level shifter and becoming a problem.
In the description to each embodiment, relate to the situation of during the horizontal blanking cycle, inserting window pulse, but the invention is not restricted to this example in front, can also during the vertical blanking cycle, insert window pulse as required.
In front in the description to each embodiment, relate to that the present invention is applied to liquid crystal indicator so as during gradation data to be handled the situation of time in corrective delay, but the invention is not restricted to this example, but can be applied even more extensively in the multiple treatment circuit that is used for video data.
In front in the description to each embodiment, relate to the situation that the present invention is applied to be used for the treatment circuit of video data, but the invention is not restricted to this example, but can be applied even more extensively the situation of proofreading and correct time delay in the several data treatment circuit, carrying out.
In front in the description to each embodiment, relate to the situation that the present invention is applied to use the liquid crystal indicator of the active device of being made by low temperature polycrystalline silicon, but the invention is not restricted to this example, but can be applied even more extensively in plurality of liquid crystals display device (, perhaps using the liquid crystal indicator of the active device of making by CGS (discontinuous crystal grain silicon)) and multiple panel display apparatus (such as EL (electroluminescence) display device) and can be applicable to multiple logical circuit such as the liquid crystal indicator that uses the active device of making by high temperature polysilicon.
Commercial Application
The present invention can be used for for example having the liquid that is integrally formed in the drive circuit on the insulated substrate Crystal device.
Claims (6)
- One kind time delay correcting circuit, it is characterized in that, for the data processing circuit that is used for the input data with quiescent period are handled, predetermined instant during described quiescent period inserts empty data in the described input data, wherein in described input data during the described quiescent period keeping constant logic level in the constant cycle is during constant, and described empty data have and the opposite logic level of described constant logic level.
- 2. one kind is used for data processing circuit that the input data with quiescent period are handled, wherein import data during the described quiescent period to keep constant logic level in the constant cycle is during constant, it is characterized in that the predetermined instant during described quiescent period will have the empty data of the logic level opposite with described constant logic level and insert in the described input data.
- 3. data processing circuit according to claim 2 is characterized in that:Described input data are video data; WithDescribed quiescent period is horizontal blanking cycle or vertical blanking cycle.
- 4. panel display apparatus comprises:A display part, it has the pixel that is arranged in matrix form;A vertical drive circuit is used for sequentially selecting by gate line the pixel of this display part; AndA horizontal drive circuit, be used for by the gradation data of expression pixel grey scale sequentially being sampled and converting described gradation data to simulating signal, thereby and drive selected pixel by described gate line by the signal wire that drives this display part with described simulating signalIt is characterized in that, by the predetermined instant during the horizontal blanking cycle of described gradation data will have with the described horizontal blanking cycle during the empty data of the opposite logic level of logic level insert in the described gradation data, described gradation data is handled.
- 5. panel display apparatus according to claim 4 is characterized in that, is formed for handling the active device of gradation data by low temperature polycrystalline silicon.
- 6. panel display apparatus according to claim 4 is characterized in that, is formed for handling the active device of gradation data by CGS.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003280583 | 2003-07-28 | ||
| JP280583/2003 | 2003-07-28 | ||
| JP347803/2003 | 2003-10-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1830017A true CN1830017A (en) | 2006-09-06 |
| CN100442347C CN100442347C (en) | 2008-12-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004800221047A Expired - Fee Related CN100442347C (en) | 2003-07-28 | 2004-07-27 | Delay time correction circuit, video data processing circuit, and flat display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100442347C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345016B (en) * | 2007-07-09 | 2012-07-18 | 瑞萨电子株式会社 | Flat panel display device and data processing method for video data |
| CN110073176A (en) * | 2019-03-15 | 2019-07-30 | 深圳市汇顶科技股份有限公司 | Correcting circuit and coherent signal processing circuit and chip |
| CN111756364A (en) * | 2019-03-26 | 2020-10-09 | 拉碧斯半导体株式会社 | Logic circuit |
| US11677608B1 (en) * | 2018-12-26 | 2023-06-13 | Cable Television Laboratories, Inc. | Systems and methods for transmitting data via a cable |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0594156A (en) * | 1991-10-03 | 1993-04-16 | Hitachi Ltd | Liquid crystal display device |
| JP3379289B2 (en) * | 1995-07-03 | 2003-02-24 | 松下電器産業株式会社 | Television receiver |
| JP3318667B2 (en) * | 1996-02-06 | 2002-08-26 | シャープ株式会社 | Liquid crystal display |
| JP2001027887A (en) * | 1999-05-11 | 2001-01-30 | Toshiba Corp | Method for driving plane display device |
| JP2001109438A (en) * | 1999-10-12 | 2001-04-20 | Toshiba Corp | Driving method of planar display device |
| JP2002009594A (en) * | 2000-06-26 | 2002-01-11 | Ando Electric Co Ltd | Delay time stabilizing circuit |
| JP2002189456A (en) * | 2000-12-20 | 2002-07-05 | Fujitsu Ltd | Liquid crystal display device |
-
2004
- 2004-07-27 CN CNB2004800221047A patent/CN100442347C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345016B (en) * | 2007-07-09 | 2012-07-18 | 瑞萨电子株式会社 | Flat panel display device and data processing method for video data |
| US11677608B1 (en) * | 2018-12-26 | 2023-06-13 | Cable Television Laboratories, Inc. | Systems and methods for transmitting data via a cable |
| CN110073176A (en) * | 2019-03-15 | 2019-07-30 | 深圳市汇顶科技股份有限公司 | Correcting circuit and coherent signal processing circuit and chip |
| CN110073176B (en) * | 2019-03-15 | 2020-11-27 | 深圳市汇顶科技股份有限公司 | Correction circuit and related signal processing circuit and chip |
| CN111756364A (en) * | 2019-03-26 | 2020-10-09 | 拉碧斯半导体株式会社 | Logic circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100442347C (en) | 2008-12-10 |
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