CN1828715A - Drive circuit chip and display device - Google Patents

Abstract

A source driver according to an aspect of the present invention is a source driver for outputting image signals to an image-signal output terminal, and outputs image signals to an image-signal output terminal with a plurality of timings including a first timing and a second timing, which is different from the first timing, in response to a plurality of image-output control signals including a first and a second image-output control signals which are supplied from the outside during the same horizontal period.

Description

Drive circuit chip and display device

Technical field

The present invention relates to the drive circuit chip of display device and use the display device of this drive circuit chip.Particularly, the present invention relates to the sequential control of drive circuit chip.

Background technology

In recent years, more and more increased importance towards the increasingly extensive application of the high development of the society of video/information and multimedia system such as flat-panel monitors such as liquid crystal indicators.Liquid crystal indicator has multiple advantage, comprises low-power consumption, thin and in light weight.This makes LCD be widely used for such as display device such as mobile terminal apparatus.

So far, passive matrix liquid crystal indicator and active matrix liquid crystal display apparatus are commonly referred to as liquid crystal indicator (referring to Japanese kokai publication hei 01-200396,07-104707 and 10-301536 communique).As shown in figure 12, active matrix liquid crystal display apparatus 10 comprise active matrix liquid crystal display panel 11, be used for the driven sweep line gate drivers 12, multiple source driver 13 that each is used for driving data lines, be used to provide the controller 14 of video data XDn and various clock signal (XCLK, XSTB etc.).

Display panels 11 comprises thin film transistor (TFT) (TFT) array base palte, relative (counter) substrate and seizing on both sides by the arms at tft array substrate and the liquid crystal between the substrate relatively.On tft array substrate, form a plurality of sweep traces (gate lines G L), a plurality of data line (source electrode line SL), pixel electrode and TFT.Sweep trace becomes clathrate to arrange with data line.Pixel electrode becomes matrix arrangements.TFT is the on-off element that is connected to source electrode line SL and pixel electrode.

The outgoing side of gate drivers 12 is connected to the gate lines G L of display panels 11.The outgoing side of source electrode driver 13 is connected to the source electrode line SL of display panels 11.Video data is input to controller 14 from the external host such as PC, and the outgoing side of controller 14 is connected to gate drivers 12 and element driver 13.

Chip size by the restriction that comes from manufacturing to gate drivers 12 and source electrode driver 13 applies restriction.This has also limited the gate drivers 12 that constitutes from single chip and has outputed to the quantity of signal of gate lines G L and the quantity that outputs to the signal of source electrode line SL from the source electrode driver 13 that single chip constitutes.For this reason, under the bigger situation of display panels 11, need to arrange a plurality of gate drivers (chip) 12 and multiple source driver (chip) 13.Figure 12 shows the situation that provides two source electrode drivers 13 (source electrode driver A13a and source electrode driver B13b).

In situation about showing, be imported into controller 14 such as the various clock signals of vertical synchronizing signal Vsync and horizontal-drive signal Hsync by liquid crystal indicator 10.Clock signal is input to gate drivers 12 with the strobe pulse signal slave controller 14 that is used for select progressively gate lines G L.In addition, various clock signals and being used for indicate video data slave controller 14 with each corresponding gray shade scale of source electrode line SL to be sent in the source electrode driver 13 each.In the source electrode driver 13 each produces grayscale voltage by the video data that has obtained is used the D/A conversion, and this grayscale voltage is outputed to corresponding source electrode line as picture signal.

The sweep signal of impulse form offers each gate lines G L from gate drivers 12.When the sweep signal that offers gate lines G L is in " conducting " level, be connected to all conductings of all TFT of this gate lines G L.The picture signal that from source electrode driver 13 one offers source electrode line SL offers pixel electrode by the TFT of conducting.Subsequently, when TFT ends when become " ending " level at sweep trace after, the pixel voltage that obtains respectively by by the feedthrough of TFT the picture signal that provides being added offset voltage is maintained in liquid crystal capacitance or the auxiliary capacitor, provides sweep signal up to the gate lines G L to next frame.Then, order provides sweep signal to each gate lines G L.Thus, the predetermined picture signal is offered all pixel electrodes.By each frame period is rewritten picture signal, can display image.

Yet, be used for providing the source electrode driver 13 of picture signal to have following problem to display panels 11.To describe the problem of conventional source electrode driver 13 with reference to Figure 13.In each source electrode driver 13, the input of video data holding unit 15 is connected to controller 14, and the outgoing side of video data holding unit 15 is connected to latch cicuit 16.The outgoing side of latch cicuit 16 is connected to D/A transducer 17, and the outgoing side of D/A transducer 17 is connected to impact damper 18.In addition, image output control signal (XSTB) slave controller 14 is input to latch cicuit 16 and impact damper 18.

Each all has in the situation of previous constructions at source electrode driver 13, at first, in source electrode driver A13a shown in Figure 12, the video data that is input to pixel electrode is input to video data holding unit 15 in proper order, and wherein said pixel electrode is connected to a source electrode line GL among the regional A (half) of display panels 11.Video data holding unit 15 launches and keeps the video data of order input.The video data that will be input to the gate lines G L among the regional A that is kept is latched in the moment that presentation video output control signal (XSTB) rises by latch cicuit 16, and the parallel simultaneously D/A transducer 17 that outputs to.Subsequently, in the moment that presentation video output control signal (XSTB) descends, shows signal outputs to source electrode line SL from impact damper 18.At this moment, all output signals of the single gate line among the regional A are source electrode driver 13 outputs from being made of single chip simultaneously, as shown in figure 14.This has caused the big peak point current of instantaneous appearance in the source electrode driver 13 that is made of single chip.Therefore, this has caused the problem of the electromagnetic interference (EMI) noise that appearance is big in source electrode driver 13.

Summary of the invention

One aspect of the present invention is the drive circuit chip that is used for to picture signal outlet terminal output image signal.The a plurality of image output control signals that comprise first and second images output control signal that this drive circuit chip response provides from the outside during same horizontal cycle, comprising a plurality of moment of first moment, to picture signal outlet terminal output image signal with second moment that was different from for first moment.If drive circuit chip has this structure, then make it possible to reduce the quantity of the signal of exporting simultaneously from this drive circuit chip.Therefore, in the driving circuit that single chip constitutes by this, can reduce peak point current, and can reduce the EMI noise thus.

Description of drawings

Fig. 1 is the synoptic diagram that illustrates according to the example of the structure of the display device of first embodiment.

Fig. 2 is the synoptic diagram that illustrates according to the example of the structure of the driving circuit of first embodiment.

Fig. 3 is the synoptic diagram that illustrates according to the example of the output buffer unit of the driving circuit of first embodiment.

The sequential chart that Fig. 4 provides when being to use according to the driving circuit of first embodiment.

Fig. 5 is the oscillogram of explanation by the operation of carrying out according to the driving circuit of first embodiment.

Fig. 6 is the synoptic diagram that illustrates according to the example of the structure of the driving circuit of second embodiment.

Fig. 7 is the synoptic diagram that illustrates according to the example of the sampling hold circuit of the driving circuit of second embodiment.

Fig. 8 is the sequential chart of explanation by the operation of carrying out according to the driving circuit of the 3rd embodiment.

Fig. 9 is the synoptic diagram that illustrates according to the example of the structure of the driving circuit of the 4th embodiment.

Figure 10 is the synoptic diagram that illustrates according to the example of the output buffer unit of the driving circuit of the 4th embodiment.

The sequential chart that Figure 11 provides when being to use according to the driving circuit of the 4th embodiment.

Figure 12 is the figure that the structure of conventional liquid crystal indicator is shown.

Figure 13 is the figure that the structure of conventional driving circuit is shown.

Figure 14 is the figure of explanation by the operation of conventional driving circuit execution.

The sequential chart that Figure 15 provides when being to use conventional driving circuit.

Embodiment

(first embodiment)

Describe with reference to 1 pair of display device of figure according to first embodiment of the invention.At this, describe with the example of transmission-type active matrix liquid crystal display apparatus as display device.Fig. 1 is the synoptic diagram according to the liquid crystal indicator 100 of present embodiment.Liquid crystal indicator 100 comprises: the display panels 101 that is used for display image; The scan line driver (to call " gate drivers " in the following text) 102 that is used for driven sweep line (to call " gate lines G L " in the following text); Each all is used for the datawire driver 103 of driving data lines (to call " source electrode line SL " in the following text).The figure shows the example that is furnished with two source electrode drivers 103.Figure 1 illustrates source electrode driver A103a and source electrode driver B103b.In the source electrode driver 103 each all is fabricated to semi-conductor chip.In addition, liquid crystal indicator 100 comprises controller 104, power supply (not shown) or the like, and controller 104 is used to provide the video data of digital signal form, and various clock signals are provided.

Display panels 101 comprises the viewing area that is made of a plurality of pixels.Display panels 101 has a kind of like this structure, has wherein seized liquid crystal on both sides by the arms, described relative substrate and described tft array substrate positioned opposite between thin film transistor (TFT) (TFT) array base palte (not shown) and relative substrate (not shown).On tft array substrate, gate lines G L forms along the horizontal direction among Fig. 1, and source electrode line SL forms along the vertical direction among Fig. 1.Near each point of crossing between gate lines G L and the source electrode line SL, provide active component, for example TFT.Between gate line and source electrode line, form a plurality of pixel electrodes, make that these a plurality of pixel electrodes become arranged.The grid of each is connected to one of gate lines G L among the TFT, and an electrode in each source/drain is connected to one of source electrode line SL, and another electrode in each source/drain is connected to one of pixel electrode.

Simultaneously, on relative substrate, form public electrode, color filter R (red), color filter G (green) and color filter B (indigo plant).Public electrode is the transparency electrode that forms in the actual mode relative with pixel electrode of this public electrode on the almost whole surface of relative substrate.From gate drivers 102 sweep signal of impulse form is offered gate lines G L.When the sweep signal that offers gate lines G L is in " conducting " level, all conductings of all TFT that link to each other with this gate lines G L.The picture signal that offers source electrode line SL from source electrode driver 103 offers pixel electrode by the TFT of conducting.If TFT ends in response to sweep signal becomes " ending " level subsequently, kept by liquid crystal capacitance and auxiliary capacitor by adding offset voltage to pixel voltage that the picture signal that provided obtains so, provide sweep signal up to the gate lines G L in next frame by the feedthrough of TFT.Then, by the sweep signal order is offered gate lines G L, respectively the predetermined picture signal is offered all pixel electrodes.Rewriting makes it possible to display image to picture signal with the frame period.

The orientation of the liquid crystal in pixel electrode between each and the public electrode is in response to each pixel voltage and the difference between the voltage of public electrode and changing in the pixel electrode.This change control is from the transit dose of the light of (not shown) incident backlight.In the pixel of display panels 101 each shows various tones by means of the demonstration with the corresponding color saturation of the light quantity that sees through and R, G, B color.What suitable band was mentioned is in monochrome demonstration situation, not provide color filter.

Notable feature of the present invention is source electrode driver 103.Below with reference to Fig. 2 source electrode driver 103 is elaborated.What suitable band was mentioned is that source electrode driver A103a is equipped with identical circuit structure with source electrode driver B103b.At first, be, video data outputed to D/A transducer 107 from data-latching circuit 106 in a plurality of moment according to each the difference in each and the conventional source electrode driver 13 shown in Figure 13 in the source electrode driver 103 of present embodiment.Secondly, be according to each the difference in each and the conventional source electrode driver 13 shown in Figure 13 in the source electrode driver 103 of present embodiment, in a plurality of moment picture signal is outputed to picture signal outlet terminal 109 from output buffer unit 108 respectively, and output time differs from one another.Here, to describe following situation, promptly the inside of each provides two data latch cicuits 106 in source electrode driver 103, the control signal of these two data latch cicuits 106 differs from one another, thereby these two data latch cicuits 106 are exported video data in the moment separately that differs from one another, and the inside of each provides two output buffer unit 108 in source electrode driver 103, and the control signal of these two output buffer unit 108 differs from one another.Be in order to make explanation simple, will come source electrode driver 103 is described along what band was mentioned by the pixels that in the source electrode driver 103 each drives 4 row * 1 row in a horizontal direction.

As shown in Figure 2, comprise video data holding unit 105, the first latch cicuit A106a, the second latch cicuit B106b, D/A transducer 107, output buffer unit 108 and picture signal outlet terminal 109 according in the source electrode driver 103 of present embodiment each.About output buffer unit 108, output (by D/A transducer 107) from the first latch cicuit A106a is imported into the first output buffer unit 108a, output (by D/A transducer 107) from the second latch cicuit B106b is imported into the second output buffer unit 108b, and the first output buffer unit 108a and the second output buffer unit 108b are provided for each of source electrode driver 103.In the situation of example shown in Figure 2, the first output buffer unit 108a handle with display panels 101 in the corresponding signal of odd number source electrode line SL (picture signal outlet terminal 109a), the corresponding signal of even number source electrode line SL (picture signal outlet terminal 109b) in second output buffer unit 108b processing and the display panels 101.

The input of video data holding unit 105 is connected to controller 104, and the outgoing side of video data holding unit 105 is connected to the first latch cicuit A106a and the second latch cicuit B106b.Each outgoing side of latch cicuit 106 is connected to D/A transducer 107.The outgoing side of D/A transducer 107 is connected to output buffer unit 108.Source electrode driver 103 is connected with the source electrode line SL of display panels 101 by a plurality of picture signal outlet terminals 109.The picture signal of 108 outputs offers the source electrode line SL of display panels 101 by picture signal outlet terminal 109 from the output buffer unit.

Video data holding unit 105 launches and keeps the video data of slave controller 104 order inputs, and with the video data and the line output that keep.The first latch cicuit A106a and the second latch cicuit B106b latched from the video data of video data holding unit 105 and line output in their moment of latching separately, and the video data that latchs is outputed to D/A transducer 107.D/A transducer 107 will be transformed into the grayscale voltage that depends on this video data from the video data of the first latch cicuit A106a and second latch cicuit B106b output.The grayscale voltage that the first output buffer unit 108a and the second output buffer unit 108b will be input to first and second buffer units outputs to the source electrode line SL of display panels 101 as picture signal at their output times separately.

Fig. 3 illustrates the example of one structure in the output buffer unit 108.In the output buffer unit 108 each comprises output buffer 110 and switch 111.The input of output buffer 110 is connected to D/A transducer 107, and the outgoing side of output buffer 110 is connected to switch 111.Output buffer 110 is transformed into picture signal by the grayscale voltage that will import from D/A transducer 107 grayscale voltage application impedance conversion, and exports this picture signal.Image output control signal in response to slave controller 104 inputs is connected switch 111, and thus the picture signal that provides from output buffer 110 is outputed to one corresponding the picture signal outlet terminal 109a.

At this, be elaborated to driving the operation of carrying out in the situation of display panels 101 by one in the use source electrode driver 103, each in the wherein said source electrode driver 103 all has foregoing structure.At first, will be input to controller 104 from video data (video data) and various clock signal (for example vertical synchronizing signal Vsync and horizontal-drive signal Hsync) such as external hosts such as PC.Slave controller 104 is to gate drivers 102 input clock signals and the strobe pulse signal that is used for select progressively gate lines G L.According to clock signal, gate drivers 102 each output scanning signal in gate lines G L, order transmits the strobe pulse signal of input simultaneously.

On the other hand, slave controller 104 each input in source electrode driver 103 comprises first image output control signal and the output control signal of second image output control signal and the video data that is used to indicate gray shade scale.When having selected gate line by sweep signal, each in the source electrode driver 103 offers picture signal each in the pixel that is connected to selected gate line.

Slave controller 104 is to video data holding unit 105 input strobe pulse signal XSP and clock signal XCLK.Video data holding unit 105 comprises shift register and input data latching piece, and in input data latching piece, a plurality of latchs are vertically connected to one another.Strobe pulse signal XSP is imported into shift register, and transmits rearward one-level (one stage) with clock signal XCLK synchronizing sequence.

Latch corresponding video data by the input data latch of selecting from the output of the trigger of shift register with each source electrode line SL.Like this, video data holding unit 105 launches and keeps the video data of slave controller 104 order inputs.

Image output control signal 1 (XSTB1) slave controller 104 as first image output control signal is input to the first latch cicuit A106a.The first latch cicuit A106a latchs from the video data of video data holding unit 105 and line output at the rising edge of image output control signal 1 (XSTB1), and this rising edge represents the 3rd constantly.In addition, the parallel D/A transducer 107 that outputs to of the first latch cicuit A106a video data that will latch thus (in this example with two corresponding signals of odd number source electrode line SL).According to the video data of importing thus, 107 pairs of a plurality of grayscale voltages that produced by the grayscale voltage generating circuit (not shown) of D/A transducer are used the D/A conversion, and the grayscale voltage of expectation is outputed to output buffer unit 108.

Picture output signal 1 (XSTB1) also is imported into the switch 111 of the first output buffer unit 108a.The switch 111 of the first output buffer unit 108a disconnects at the rising edge of image output control signal 1 (XSTB1), and this rising edge represents the 3rd constantly, and therefore presents high impedance from the output of the first output buffer unit 108a.When the output of the first output buffer unit 108a presented high impedance, the D/A conversion was used in 107 pairs of numeral outputs from the first latch cicuit A106a of D/A transducer.Subsequently, the output buffer 110 that offers the first output buffer unit 108a is transformed into picture signal by the grayscale voltage that will import from D/A transducer 107 grayscale voltage application impedance conversion, and exports this picture signal.After this, switch 111 is connected at the negative edge of image output control signal 1 (XSTB1), and this negative edge represents first constantly, and will output to picture signal outlet terminal 109a by the picture signal that this conversion obtains thus.

After the first latch cicuit A106a, the second latch cicuit B106b begins to latch and export shows signal.Image output control signal 2 (XSTB2) slave controller 104 as second image output control signal is input to the second latch cicuit B106b.The second latch cicuit B106b latchs from the video data of video data holding unit 105 and line output at the rising edge of image output control signal 2 (XSTB2), and this rising edge represents the 4th constantly.In addition, the parallel D/A transducer 107 that outputs to of the second latch cicuit B106b video data that will latch thus (in this example with two corresponding signals of even number source electrode line SL).According to the video data of importing thus, 107 pairs of a plurality of grayscale voltages that produced by the grayscale voltage generating circuit (not shown) of D/A transducer are used the D/A conversion, and the grayscale voltage of expectation is outputed to output buffer unit 108.

Picture output signal 2 (XSTB2) also is imported into the switch 111 of the second output buffer unit 108b.The switch 111 of the second output buffer unit 108b disconnects at the rising edge of image output control signal 2 (XSTB2), and this rising edge represents the 4th constantly, and therefore presents high impedance from the output of the second output buffer unit 108b.When the output of the second output buffer unit 108b presented high impedance, the D/A conversion was used in 107 pairs of numeral outputs from the second latch cicuit B106b of D/A transducer.Subsequently, the output buffer 110 that offers the second output buffer unit 108b is transformed into picture signal by the grayscale voltage that will import from D/A transducer 107 grayscale voltage application impedance conversion, and exports this picture signal.After this, switch 111 is connected at the negative edge of image output control signal 2 (XSTB2), and this negative edge represents second constantly, and will output to picture signal outlet terminal 109b by the picture signal that this conversion obtains thus.

In other words, the video data of expansion and maintenance is latched in the 3rd moment and the 4th by latch cicuit A106a and latch B106b respectively constantly in video data holding unit 105, and described the 3rd moment and the 4th moment differ from one another.Subsequently, in first constantly and in second moment any one that differs from one another, picture signal is outputed to the odd number source electrode line SL and the even number source electrode line SL of display panels 101.Generally speaking, according to present embodiment, the quantity of the picture signal that each from source electrode driver is exported simultaneously is reduced to half of the picture signal quantity exported simultaneously from source electrode driver according to routine techniques.The sequential chart that Fig. 4 provides when use is shown according in the source electrode driver 103 of present embodiment each.Part among Fig. 4 (a) indicates to offer the sweep signal Gate of gate lines G L.Part among Fig. 4 (b) indicates to be input to the latch cicuit 106 of source electrode driver 103 and the image of output buffer unit 108 is exported control signal.Part among Fig. 4 (c) indicates to offer the picture signal of the pixel electrode that links to each other with the source electrode line SL of display panels 101.

Shown in the part among Fig. 4 (a), the sweep signal of impulse form is sent to the gate lines G L each from gate drivers 102.When one sweep signal in offering gate lines G L is in " conducting " level, be connected to all conductings of all TFT of this gate lines G L.When the TFT conducting, the picture signal that offers source electrode line SL from source electrode driver 103 offers pixel electrode by the TFT of conducting.After this, when sweep signal become " ending " level and TFT therefore and by the time, each in the pixel electrode and relatively the electric potential difference between the electrode of substrate be provided for pixel electrode by maintenances such as liquid crystal capacitance, auxiliary capacitors up to next picture signal.By sending the sweep signal order to gate lines G L, the predetermined picture signal is offered all pixel electrodes.Rewriting makes it possible to display image to picture signal with the frame period.

Shown in the part among Fig. 4 (b), the moment of the negative edge of image output control signal 1 (XSTB1) (first constantly) is different with the moment (second constantly) of the negative edge of image output control signal 2 (XSTB2), and this describes in the above.Import image output control signal 1 (XSTB1) afterwards, from image output control signal 1 (XSTB1) time delay in the moment Δ t moment input picture output control signal 2 (XSTB2).Owing to this reason, in the situation of this embodiment, source electrode driver 103 is to the odd number source electrode line output image signal of display panels 101, and exports this picture signal to the even number source electrode line of display panels 101 afterwards.

As mentioned above, at the negative edge (first constantly) of image output control signal 1 (XSTB1) or at negative edge (second constantly) each output image signal in source electrode line SL of image output control signal 2 (XSTB2).Therefore, shown in the part among Fig. 4 (c), export the negative edge (first constantly) of control signal 1 (XSTB1) to being connected to odd number (1,3 in response to the image shown in the part among Fig. 4 (b),, 2m-1:m is a natural number) and the pixel electrode of source electrode line SL provides picture signal.Like this, when sweep signal Gate was in " conducting " level, electric charge was accumulated in these pixel electrodes.After this, in response to the negative edge (second constantly) of the image shown in the part among Fig. 4 (b) output control signal 2 (XSTB2) to be connected to even number (2,4 ..., 2m:m is a natural number) and the pixel electrode of source electrode line SL provides picture signal.Like this, when sweep signal Gate was in " conducting " level, electric charge was accumulated in these pixel electrodes.

In addition, as shown in Figure 4, in identical horizontal cycle, these orders constantly are not limited to from the 3rd moment, first moment, were carved into second at the 4th o'clock constantly.For example, be engraved in first o'clock the 4th constantly after, also it doesn't matter before constantly second.In other words, from the 3rd constantly, the 4th constantly, to be carved into second constantly the order at first o'clock be that it doesn't matter.In addition, also it doesn't matter for order below: from the 3rd constantly, the 4th constantly, be carved into first constantly the order at second o'clock; From the 4th constantly, second constantly, be carved into first constantly the order at the 3rd o'clock; From the 4th constantly, the 3rd constantly, be carved into first constantly the order at second o'clock; From the 4th constantly, the 3rd constantly, be carved into second constantly the order at first o'clock; From the 3rd constantly constantly=the 4th, be carved into second constantly the order at first o'clock; And from the 3rd constantly constantly=the 4th, be carved into first constantly the order at second o'clock.

Fig. 5 is illustrated in the source current IDD with each consumption in the source electrode driver 103 in the situation of aforementioned manner drive source driver 103.Be shown in dotted line the peak point current that in following situation, occurs, promptly the video data that will accumulate in a gate lines G L in response to image output control signal is loaded in the latch cicuit one simultaneously, and simultaneously with the parallel D/A transducer that outputs to of the video data that loads.As can be seen from Figure 5, in each the situation according to the source electrode driver of present embodiment, the moment of the negative edge of two image output control signals differs the Δ t time each other.This makes it possible to suppress otherwise the peak point current that can occur in each of source driver chip.Therefore, this makes it possible to suppress otherwise can come from this peak point current and the electromagnetic interference (EMI) noise that occurs.

Should be noted that in the situation of present embodiment the entry terminal of the image of source electrode driver A103a output control signal links to each other by the entry terminal of distribution with the identical image output control signal of source electrode driver B103b.Owing to this reason, any one in the source electrode image output control signal is input to source electrode driver A103a and source electrode driver B103b in the identical moment.Particularly, in display panels 101, constantly a picture signal is offered all odd number source electrode line SL first, and constantly this picture signal is offered all even number source electrode line SL second.

Yet, the image that be input to the image output control signal of source electrode driver A103a and will be input to source electrode driver B103b export control signal each other the time engrave that different also it doesn't matter.In other words, be used for each image output control signal slave controller 104 being sent to two electric wires of source electrode driver A103a and being used for two electric wires that each image output control signal slave controller 104 is sent to source electrode driver B103b can be formed independently of one another.In other words, constantly picture signal is outputed to corresponding picture signal outlet terminal 109 from source electrode driver A103a first and second, and picture signal is outputed to corresponding picture signal outlet terminal 109 from source electrode driver B103b in the 5th and the 6th moment different with first and second moment, also it doesn't matter.

After above-mentioned explanation is appreciated that video data at a source electrode line is unfolded and remains in the video data holding unit 105 all source electrode drivers 103, begin output image signal according to image output control signal.Owing to this reason, the time difference Δ t between the image output control signal can be set arbitrarily.Present embodiment is not limited to respond each moment that video data is input in the source electrode driver and determines the moment of output signal, thisly determines although carried out in the situation of routine techniques.May wish that Δ t is less, for example, from the viewpoint of picture quality.On the contrary, the viewpoint of the EMI noise of each from suppress source electrode driver, Δ t need be set to sizable value.

The sequential of the image output control signal by changing slave controller 104 inputs can easily change Δ t.Provide counter by inside, can adjust Δ t controller 104.If the inside to controller 104 provides counter, then make it possible to adjust the sequential of image output control signal, for example in response to each wiring distance in the source electrode driver 103 of propagating the EMI noise in the above.Therefore, this makes it possible to more effectively reduce the EMI noise, keeps picture quality simultaneously.

Described present embodiment, provided by the n in " n that slave controller 104 provides (n: individual image output control signal natural number) " and be set to 1 and 2 examples that two images output control signals are provided.Yet, should be noted that present embodiment is not limited thereto.For example, be set to three or bigger number, three or more images output control signals can be provided by n.If three or more image output control signals are provided, have then made it possible to reduce the number of signals of exporting simultaneously from source electrode driver 103.In addition, this makes it possible to reduce peak point current, and reduces the EMI noise that produces.For example, can carry out following design: three different moment are set in one way, make these three to distinguish corresponding color R, G and B constantly, and at these three each picture signal outlet terminal output image signals from adjoining each other of the different moment.Be desirably in any picture signal in identical these three kinds of colors of moment output expression.

(second embodiment)

Describe first embodiment, provided the example that video data is a digital signal form.Yet video data can be analog signal form.In other words, the video data of analog signal form can launch and remain in the sampling hold circuit that is made of a plurality of switches and a plurality of capacitor.

Fig. 6 is the circuit diagram that illustrates according to the source electrode driver 103 of second embodiment.As shown in Figure 6, the source electrode driver 103 according to second embodiment comprises video data holding unit 105, the first sampling hold circuit A112a, the second sampling hold circuit B112b, D/A transducer 107 and output buffer 111.Make present embodiment different with first embodiment be, the first latch cicuit A106a shown in Figure 2 is replaced by the first sampling hold circuit A112a, the second latch cicuit B106b shown in Figure 2 is replaced by the second sampling hold circuit B112b.

The input of video data holding unit 105 is connected to controller 104, and the outgoing side of video data holding unit 105 is connected to the first sampling hold circuit A112a and the second sampling hold circuit B112b.Each outgoing side of sampling hold circuit 112 is connected to output buffer 110.Source electrode driver 103 links to each other with the source electrode line SL of display panels 101 respectively by a plurality of picture signal outlet terminals 109.Offer each source electrode line SL of display panels 101 by the picture signal outlet terminal 109 of correspondence from the picture signal of output buffer 110 outputs.

Fig. 7 illustrates one example in the sampling hold circuit 112.Sampling hold circuit 112 shown in Figure 7 has a sampling and keeps the structure of/one amplifier, and comprises sampling switch 113, output switch 114 and sampling capacitor 115.The simulation video data is provided for sampling switch 113.Sampling hold circuit 112 can comprise that two samplings that constitute two sampling hold circuits keep the structure of/one amplifier.

At this, will be to describing by using source electrode driver 103 to drive the operation of carrying out in the situation of display panels 101, each has foregoing structure wherein said source electrode driver.Sampled signal XSP and clock signal XCLK slave controller 104 are input to video data holding unit 105.Video data holding unit 105 comprises the shift register (not shown), and transmits rearward one-level with clock signal XCLK synchronizing sequence.

Response sample signal XSP controls the sampling switch 113 that lays respectively among sampling hold circuit A112a and the sampling hold circuit B112b.When sampling switch 113 was connected, sampling capacitor 115 kept from the simulation video data of video data holding unit 105 outputs.Thus, sampling hold circuit A112a and sampling hold circuit B112b launch and keep the video data of slave controller 104 order inputs.

Image output control signal 1 (XSTB1) slave controller 104 as first image output control signal is input to sampling hold circuit A112a.The output switch 114 of sampling hold circuit A112a is by image output control signal 1 (XSTB1) control.In addition, image output control signal 2 (XSTB2) slave controller 104 as second image output control signal is input to sampling hold circuit B112b.The output switch 114 of sampling hold circuit B112b is by image output control signal 2 (XSTB2) control.

Negative edge (this negative edge represents first constantly) in image output control signal 1 (XSTB1), sampling hold circuit A112a connects output switch 114, and the simulation video data that will remain in the sampling capacitor 115 thus outputs to output buffer 110.After this, output buffer 110 is transformed to picture signal by the video data of input is used impedance conversion with the video data of importing, and picture signal is outputed to picture signal outlet terminal 109a.

In the moment that postpones the Δ t time from moment of sampling hold circuit A112a, sampling hold circuit B112b begins sampling, and the output video data.As mentioned above, image output control signal 2 (XSTB2) slave controller 104 as second image output control signal is input to the second latch cicuit B106b.Negative edge (this negative edge represents second constantly) in image output control signal 2 (XSTB2), sampling hold circuit B112b connects output switch 114, and the simulation video data that will remain in the sampling capacitor 115 thus outputs to output buffer 110.After this, output buffer 110 is transformed to picture signal by the video data of input is used impedance conversion with the video data of importing, and picture signal is outputed to picture signal outlet terminal 109b.

Particularly, as in the situation of first embodiment, the moment by making image output control signal 1 (XSTB1) and the moment of image output control signal 2 (XSTB2) differ Δ t each other, can the different moment from output buffer 110 output image signals respectively.In other words, in first moment that differs from one another and second moment, picture signal is outputed to the odd number source electrode line SL and the even number source electrode line SL of display panels 101 respectively.Generally speaking, according to present embodiment, the quantity of the picture signal of exporting simultaneously from a source electrode driver is reduced to half of the picture signal quantity exported simultaneously from a source electrode driver according to routine techniques.This makes it possible to suppress otherwise can be at the peak point current of instantaneous appearance in each of source driver chip.Therefore, this makes it possible to suppress otherwise can come from the electromagnetic interference (EMI) noise of this peak point current.

(the 3rd embodiment)

In the situation of first embodiment and second embodiment, the moment of the moment of image output control signal 1 (XSTB1) and image output control signal 2 (XSTB2) differs Δ t each other.Picture signal is written to time ratio used in the pixel electrode that links to each other with the odd number source electrode line and is written to long Δ t in the pixel electrode that links to each other with the even number source electrode line.If can picture signal be written in the pixel electrode enough time enough, then to not influence of picture quality.If make display panel bigger and more accurate, then not only load capacity becomes bigger, and a horizontal cycle becomes shorter.

Owing to this reason, for odd number source electrode line in the display panels 101 and even number source electrode line, the columns of pixel electrodes that insufficient columns of pixel electrodes that writes of picture signal and picture signal fully write alternates.

In addition, in the situation of the liquid crystal indicator of routine, as shown in figure 15, picture signal offers display panels 11 from source electrode driver A13a, and after this, from the source electrode driver B13b output picture signal corresponding with video data.In other words, with different moment in the moment from source electrode driver A13a output image signal, source electrode driver B13b exports all output signals simultaneously to a gate line in the area B.

In the situation of this driving method, being used to provide the required time span of desired images signal is different between regional A that is driven by source electrode driver A13a and the area B by source electrode driver B13b driving, as shown in figure 15.Owing to this reason, provide picture signal early regional A and provide between the later area B of picture signal, interblock occurred and shown inhomogeneous.

Consider this point, in the situation of present embodiment, the moment of the moment of image output control signal 1 (XSTB1) and image output control signal 2 (XSTB2) puts the cart before the horse for each frame, as shown in Figure 8.In other words, picture signal being offered first and second of odd number source electrode line SL group and even number source electrode line SL group puts the cart before the horse for each frame constantly.This demonstration that makes it possible to alleviate interblock perpendicular line recited above is inhomogeneous, and therefore improves display quality.

(the 4th embodiment)

Describe with reference to 9 pairs of fourth embodiment of the present invention of figure.Fig. 9 is the synoptic diagram that illustrates according to the example of the structure of the source electrode driver 103 of the 4th embodiment.As shown in Figure 9, the source electrode driver 103 according to present embodiment comprises video data holding unit 105, latch cicuit A106a, latch cicuit B106b, anodal D/A transducer 107p, negative pole D/A transducer 107n and output buffer unit 120.Source electrode driver 103 according to present embodiment drives display panels 101 by an inversion driving system.In Fig. 9, with components identical among Fig. 1 use with Fig. 1 in identical reference marker and symbol represent, and omitted with Fig. 1 in the explanation of components identical.

Below to describing according to the source electrode driver 103 of present embodiment and difference according to the source electrode driver 103 of first embodiment.In a situation of inversion driving system, when picture signal outlet terminal 109a from the odd number line and 109c (XOUT1 and XOUT3) output cathode picture signal respectively, picture signal outlet terminal 109b from the even number line and 109d (XOUT2 and XOUT4) output negative pole picture signal respectively.In addition, when picture signal outlet terminal 109a from the odd number line and 109c (XOUT1 and XOUT3) output negative pole picture signal respectively, picture signal outlet terminal 109b from the even number line and 109d (XOUT2 and XOUT4) output cathode picture signal respectively.At this moment, expectation while output cathode picture signal and negative pole picture signal.

For this purpose, source electrode driver 103 according to the present invention in horizontal cycle first constantly from picture signal outlet terminal 109a and 109b (XOUT1 and XOUT2) output image signal, and with first constantly different second constantly from picture signal outlet terminal 109c and 109d (XOUT3 and XOUT4) output image signal.Otherwise, source electrode driver 103 in horizontal cycle first constantly from picture signal outlet terminal 109a and 109d (XOUT1 and XOUT4) output image signal, and in comprising first constantly the same horizontal cycle with first constantly different second constantly from picture signal outlet terminal 109b and 109c (XOUT2 and XOUT3) output image signal.

Anodal D/A transducer 107p selects anodal grayscale voltage.In addition, negative pole D/A transducer 107n selects the negative pole grayscale voltage.Anodal grayscale voltage is switched to the negative pole grayscale voltage with output buffer 120 or vice versa, and the grayscale voltage of output switching.

At this, will be elaborated to output buffer 120 with reference to Figure 10 according to present embodiment.Figure 10 is the synoptic diagram that one structure in the output buffer unit 120 is shown.Output buffer unit 120 comprise linear pattern switch 116, chiasma type switch 117, output buffer 110, output switch 111, in and switch 118 and common node 119.

As shown in Figure 9, the input of video data holding unit 105 is connected to controller 104, and the outgoing side of video data holding unit 105 is connected to latch cicuit A 106a and latch cicuit B106b.The outgoing side of each is connected to D/A transducer 107 in the latch cicuit 106.Source electrode driver 103 links to each other with the source electrode line of display panels 101 by a plurality of picture signal outlet terminals 109.The picture signal of 120 outputs offers the source electrode line SL of display panels 101 respectively by picture signal outlet terminal 109 from the output buffer unit.

When the anodal grayscale voltage from anodal D/A transducer 107p input offered odd number picture signal outlet terminal 109a and 109c (XOUT1 and XOUT3), linear pattern switch 116 was connected.In addition, when the negative pole grayscale voltage from negative pole D/A transducer 107n input offered even number picture signal outlet terminal 109b and 109d (XOUT2 and XOUT4), linear pattern switch 116 was connected.When the negative pole grayscale voltage from negative pole D/A transducer 107n input offered odd number picture signal outlet terminal 109a and 109c (XOUT1 and XOUT3), chiasma type switch 117 was connected.In addition, when the anodal grayscale voltage from anodal D/A transducer 107p input offered even number picture signal outlet terminal 109b and 109d (XOUT2 and XOUT4), chiasma type switch 117 was connected.In other words, linear pattern switch 116 and 117 counter-rotatings of chiasma type switch offer the polarity of the picture signal of odd number picture signal outlet terminal 109a and 109c (XOUT1 and XOUT3) and even number picture signal outlet terminal 109b and 109d (XOUT2 and XOUT4), and switch this polarity.At this on the one hand, linear pattern switch 116 and chiasma type switch 117 are called polarity switching circuit.

At this, will be elaborated to the operation of carrying out by source electrode driver 103 with reference to Figure 11 with structure noted earlier.In first frame, when polar signal XPOL was in " H " level, image output control signal 1 (XSTB1) was started working early than image output control signal 2 (XSTB2).Owing to this reason, about the order of the moment in first frame, what rise in presentation video output control signal 1 (XSTB1) the 3rd is first moment that presentation video output control signal 1 (XSTB1) descends after constantly, being that presentation video is exported the 4th moment that control signal 2 (XSTB2) rises afterwards, is second moment that presentation video output control signal 2 (XSTB2) descends afterwards.

Polar signal XPOL slave controller 104 is input to polarity switching circuit.When polar signal XPOL became " H " level, linear pattern switch 116 was connected, and chiasma type switch 117 disconnects.

First image output control signal (XSTB1) slave controller 104 is input to the first output buffer unit 120a.At the rising edge of first image output control signal (XSTB1) (its be the 3rd constantly), output switch 111 disconnects, in and switch 118 connect.This has neutralized at the cathode voltage at the cathode voltage at odd number picture signal outlet terminal 109a and 109c place and even number picture signal outlet terminal 109b and 109d place.In other words, by all the odd number data line DL and the even number data line DL of common node 119 short circuit display panels 101, and make the voltage equalization of data line thus.

In addition, image output control signal 1 (XSTB1) also is imported into the first latch cicuit A106a.At the rising edge of expression the 3rd image output control signal 1 (XSTB1) constantly, the first latch cicuit A106a latchs from the video data of video data holding unit 105 and line output.At this point, the first latch cicuit A106a latchs the anodal video data that will output to the first data line DL and will output to the negative pole video data of the second data line DL.

Subsequently, latch cicuit A106a is to the anodal video data that will output to first data line of anodal D/A transducer 107p output latch, and to the negative pole video data that will output to second data line of negative pole D/A transducer 107n output latch.D/ A transducer 107p and 107n use the D/A conversion to a plurality of grayscale voltages that produce by the grayscale voltage generating circuit (not shown), and according to the video data that is input to D/ A transducer 107p and 107n the grayscale voltage of expecting are outputed to the first output buffer unit 120a.

Then, the first output buffer unit 120a is by using impedance conversion to grayscale voltage, and the grayscale voltage from D/A transducer 107p or D/A transducer 107n input is transformed to picture signal, and output image signal.After this, negative edge (this negative edge represents first constantly) in image output control signal 1 (XSTB1), connect switch 111, and will output to picture signal outlet terminal 109a and 109b (XOUT1 and XOUT2) by the picture signal that conversion obtains simultaneously thus.Particularly, from picture signal outlet terminal 109a (XOUT1) the output anodal picture signal corresponding, from picture signal outlet terminal 109b (XOUT2) the output negative pole picture signal corresponding with the negative pole video data with anodal video data.

Be later than the first latch cicuit A106a, the second latch cicuit B106b begins to latch and export video data.Image output control signal 2 (XSTB2) slave controller 104 as second image output control signal is input to the second latch cicuit B106b.At the rising edge of expression the 4th image output control signal 2 (XSTB2) constantly, the second latch cicuit B106b latchs from the video data of video data holding unit 105 and line output.At this point, the second latch cicuit B106b latchs the anodal video data that will output to the 3rd data line DL and will output to the negative pole video data of the 4th data line DL.

In addition, the second latch cicuit B106b is to the anodal video data that will output to the 3rd data line of anodal D/A transducer 107p output latch, and to the negative pole video data that will output to the 4th data line of negative pole D/A transducer 107n output latch.D/ A transducer 107p and 107n use the D/A conversion to a plurality of grayscale voltages that produce by the grayscale voltage generating circuit (not shown), and according to the video data that is input to D/ A transducer 107p and 107n the grayscale voltage of expecting are outputed to the second output buffer unit 120b.

Then, the second output buffer unit 120b is by using impedance conversion to grayscale voltage, and the grayscale voltage from D/A transducer 107p or D/A transducer 107n input is transformed to picture signal, and output image signal.After this, at the negative edge of expression second image output control signal 2 (XSTB2) constantly, connect switch 111, and will output to picture signal outlet terminal 109c and 109d (XOUT3 and XOUT4) by the picture signal that conversion obtains simultaneously thus.Particularly, from picture signal outlet terminal 109c (XOUT3) the output anodal picture signal corresponding, from picture signal outlet terminal 109d (XOUT4) the output negative pole picture signal corresponding with the negative pole video data with anodal video data.

In second frame after first frame, when polar signal XPOL became " L " level, image output control signal 1 (XSTB1) was prior to image output control signal 2 (XSTB2) work.Owing to this reason, about the order of the moment in second frame, what rise in presentation video output control signal 1 (XSTB1) the 3rd is first moment that presentation video output control signal 1 (XSTB1) descends after constantly, being that presentation video is exported the 4th moment that control signal 2 (XSTB2) rises afterwards, is second moment that presentation video output control signal 2 (XSTB2) descends afterwards.

Polar signal XPOL slave controller 104 is input to polarity switching circuit.When polar signal XPOL became " L " level, linear pattern switch 116 disconnected, and chiasma type switch 117 is connected.

First image output control signal (XSTB1) slave controller 104 is input to the first output buffer unit 120a.At the rising edge of first image output control signal (XSTB1) (its be the 3rd constantly), output switch 111 disconnects, in and switch 118 connect.This has neutralized at the cathode voltage at the cathode voltage at odd number picture signal outlet terminal 109a and 109c place and even number picture signal outlet terminal 109b and 109d place.In other words, by the odd number data line DL and the even number data line DL of common node 119 short circuit display panels 101, and make the voltage equalization of data line thus.

In addition, image output control signal 1 (XSTB1) also is imported into the first latch cicuit A106a.At the rising edge of expression the 3rd image output control signal 1 (XSTB1) constantly, the first latch cicuit A106a latchs from the video data of video data holding unit 105 and line output.At this point, the first latch cicuit A106a latchs the negative pole video data that will output to the first data line DL and will output to the anodal video data of the second data line DL.

Subsequently, latch cicuit A106a is to the negative pole video data that will output to first data line of negative pole D/A transducer 107n output latch, and to the anodal video data that will output to second data line of anodal D/A transducer 107p output latch.D/ A transducer 107p and 107n use the D/A conversion to a plurality of grayscale voltages that produce by the grayscale voltage generating circuit (not shown), and according to the video data that is input to D/ A transducer 107p and 107n the grayscale voltage of expecting are outputed to the first output buffer unit 120a.

Then, the first output buffer unit 120a is by using impedance conversion to grayscale voltage, and the grayscale voltage from D/A transducer 107p or D/A transducer 107n input is transformed to picture signal, and output image signal.After this, at the negative edge (this negative edge represents first constantly) of image output control signal 1 (XSTB1), connect switch 111, and will output to picture signal outlet terminal 109a and 109b (XOUT1 and XOUT2) thus by the picture signal that conversion obtains.Particularly, from picture signal outlet terminal 109a (XOUT1) the output negative pole picture signal corresponding, from picture signal outlet terminal 109b (XOUT2) the output anodal picture signal corresponding with anodal video data with the negative pole video data.

Be later than the first latch cicuit A106a, the second latch cicuit B106b begins to latch and export video data.Image output control signal 2 (XSTB2) slave controller 104 as second image output control signal is input to the second latch cicuit B106b.At the rising edge of expression the 4th image output control signal 2 (XSTB2) constantly, the second latch cicuit B106b latchs from the video data of video data holding unit 105 and line output.At this point, the second latch cicuit B106b latchs the negative pole video data that will output to the 3rd data line DL and will output to the anodal video data of the 4th data line DL.

In addition, the second latch cicuit B106b is to the negative pole video data that will output to the 3rd data line of negative pole D/A transducer 107n output latch, and to the anodal video data that will output to the 4th data line of anodal D/A transducer 107p output latch.D/ A transducer 107p and 107n use the D/A conversion to a plurality of grayscale voltages that produce by the grayscale voltage generating circuit (not shown), and according to the video data that is input to D/ A transducer 107p and 107n the grayscale voltage of expecting are outputed to the second output buffer unit 120b.

Then, the second output buffer unit 120b is by using impedance conversion to grayscale voltage, and the grayscale voltage from D/A transducer 107p or D/A transducer 107n input is transformed to picture signal, and output image signal.After this, at the negative edge of expression second image output control signal 2 (XSTB2) constantly, connect switch 111, and will output to picture signal outlet terminal 109c and 109d (XOUT3 and XOUT4) by the picture signal that conversion obtains simultaneously thus.Particularly, from picture signal outlet terminal 109c (XOUT3) the output negative pole picture signal corresponding, from picture signal outlet terminal 109d (XOUT4) the output anodal picture signal corresponding with anodal video data with the negative pole video data.

In the 3rd frame after second frame, when polar signal XPOL became " H " level, image output control signal 2 (XSTB2) was prior to image output control signal 1 (XSTB1) work.Owing to this reason, about the order of the moment in the 3rd frame, what rise in presentation video output control signal 2 (XSTB2) the 4th is second moment that presentation video output control signal 2 (XSTB2) descends after constantly, being that presentation video is exported the 3rd moment that control signal 1 (XSTB1) rises afterwards, is first moment that presentation video output control signal 1 (XSTB1) descends afterwards.

Polar signal XPOL slave controller 104 is input to polarity switching circuit.When polar signal XPOL became " L " level, linear pattern switch 116 was connected, and chiasma type switch 117 disconnects.

Second image output control signal (XSTB2) slave controller 104 is input to the second output buffer unit 120b.At the rising edge of second image output control signal (XSTB2) (its be the 4th constantly), output switch 111 disconnects, in and switch 118 connect.This has neutralized at the cathode voltage at the cathode voltage at odd number picture signal outlet terminal 109a and 109c place and even number picture signal outlet terminal 109b and 109d place.In other words, by all the odd number data line DL and the even number data line DL of common node 119 short circuit display panels 101, and make the voltage equalization of data line thus.

In addition, image output control signal 2 (XSTB2) also is imported into the second latch cicuit B106b.At the rising edge of expression the 4th image output control signal 2 (XSTB2) constantly, the second latch cicuit B106b latchs from the video data of video data holding unit 105 and line output.At this point, the second latch cicuit B106b latchs the anodal video data that will output to the 3rd data line DL and will output to the negative pole video data of the 4th data line DL.

Subsequently, latch cicuit B106b is to the anodal video data that will output to the 3rd data line of anodal D/A transducer 107p output latch, and to the negative pole video data that will output to the 4th data line of negative pole D/A transducer 107n output latch.D/ A transducer 107p and 107n use the D/A conversion to a plurality of grayscale voltages that produce by the grayscale voltage generating circuit (not shown), and according to the video data that is input to D/ A transducer 107p and 107n the grayscale voltage of expecting are outputed to the first output buffer unit 120a.

Then, the second output buffer unit 120b is by using impedance conversion to grayscale voltage, and the grayscale voltage from D/A transducer 107p or D/A transducer 107n input is transformed to picture signal, and output image signal.After this, negative edge (this negative edge represents second constantly) in image output control signal 2 (XSTB2), connect switch 111, and will output to picture signal outlet terminal 109c and 109d (XOUT3 and XOUT4) by the picture signal that conversion obtains simultaneously thus.Particularly, from picture signal outlet terminal 109c (XOUT3) the output anodal picture signal corresponding, from picture signal outlet terminal 109d (XOUT4) the output negative pole picture signal corresponding with the negative pole video data with anodal video data.

Be later than the second latch cicuit B106b, the first latch cicuit A106a begins to latch and export video data.Image output control signal 1 (XSTB1) slave controller 104 as first image output control signal is input to the first latch cicuit A106a.At the rising edge of expression the 3rd image output control signal 2 (XSTB2) constantly, the first latch cicuit A106a latchs from the video data of video data holding unit 105 and line output.At this point, the first latch cicuit A106a latchs the anodal video data that will output to the first data line DL and will output to the negative pole video data of the second data line DL.

In addition, the first latch cicuit A106b is to the anodal video data that will output to first data line of anodal D/A transducer 107p output latch, and to the negative pole video data that will output to second data line of negative pole D/A transducer 107n output latch.D/ A transducer 107p and 107n use the D/A conversion to a plurality of grayscale voltages that produce by the grayscale voltage generating circuit (not shown), and according to the video data that is input to D/ A transducer 107p and 107n the grayscale voltage of expecting are outputed to the first output buffer unit 120a.

Then, the first output buffer unit 120a is by using impedance conversion to grayscale voltage, and the grayscale voltage from D/A transducer 107p or D/A transducer 107n input is transformed to picture signal, and output image signal.After this, at the negative edge of expression first image output control signal 1 (XSTB1) constantly, connect switch 111, and will output to picture signal outlet terminal 109a and 109b (XOUT1 and XOUT2) by the picture signal that conversion obtains simultaneously thus.Particularly, from picture signal outlet terminal 109a (XOUT1) the output anodal picture signal corresponding, from picture signal outlet terminal 109b (XOUT2) the output negative pole picture signal corresponding with the negative pole video data with anodal video data.

In the 4th frame after the 3rd frame, when polar signal XPOL became " L " level, image output control signal 2 (XSTB2) was prior to image output control signal 1 (XSTB1) work.Owing to this reason, about the order of the moment in the 4th frame, what rise in presentation video output control signal 2 (XSTB2) the 4th is second moment that presentation video output control signal 2 (XSTB2) descends after constantly, being that presentation video is exported the 3rd moment that control signal 1 (XSTB1) rises afterwards, is first moment that presentation video output control signal 1 (XSTB1) descends afterwards.

Polar signal XPOL slave controller 104 is input to polarity switching circuit.When polar signal XPOL became " L " level, linear pattern switch 116 disconnected, and chiasma type switch 117 is connected.

Second image output control signal (XSTB2) slave controller 104 is input to the second output buffer unit 120b.At the rising edge of second image output control signal (XSTB2) (its be the 4th constantly), output switch 111 disconnects, in and switch 118 connect.This has neutralized at the cathode voltage at the cathode voltage at odd number picture signal outlet terminal 109a and 109c place and even number picture signal outlet terminal 109b and 109d place.In other words, by the odd number data line DL and the even number data line DL of common node 119 short circuit display panels 101, and make the voltage equalization of data line thus.

In addition, image output control signal 2 (XSTB2) also is imported into the second latch cicuit B106b.At the rising edge of expression the 4th image output control signal 2 (XSTB2) constantly, the second latch cicuit B106b latchs from the video data of video data holding unit 105 and line output.At this point, the second latch cicuit B106b latchs the negative pole video data that will output to the 3rd data line DL and will output to the anodal video data of the 4th data line DL.

Subsequently, latch cicuit B106b is to the negative pole video data that will output to the 3rd data line of negative pole D/A transducer 107n output latch, and to the anodal video data that will output to the 4th data line of anodal D/A transducer 107p output latch.D/ A transducer 107p and 107n use the D/A conversion to a plurality of grayscale voltages that produce by the grayscale voltage generating circuit (not shown), and according to the video data that is input to D/ A transducer 107p and 107n the grayscale voltage of expecting are outputed to the second output buffer unit 120b.

Then, the second output buffer unit 120b is by using impedance conversion to grayscale voltage, and the grayscale voltage from D/A transducer 107p or D/A transducer 107n input is transformed to picture signal, and output image signal.After this, at the negative edge (this negative edge represents second constantly) of image output control signal 2 (XSTB2), connect switch 111, and will output to picture signal outlet terminal 109c and 109d (XOUT3 and XOUT4) thus by the picture signal that conversion obtains.Particularly, from picture signal outlet terminal 109c (XOUT3) the output negative pole picture signal corresponding, from picture signal outlet terminal 109d (XOUT4) the output anodal picture signal corresponding with anodal video data with the negative pole video data.

Be later than the second latch cicuit B106b, the first latch cicuit A106a begins to latch and export video data.Image output control signal 1 (XSTB1) slave controller 104 as first image output control signal is input to the first latch cicuit A106a.At the rising edge of expression the 3rd image output control signal 1 (XSTB1) constantly, the first latch cicuit A106a latchs from the video data of video data holding unit 105 and line output.At this point, the first latch cicuit A106a latchs the negative pole video data that will output to the first data line DL and will output to the anodal video data of the second data line DL.

In addition, the first latch cicuit A106a is to the negative pole video data that will output to first data line of negative pole D/A transducer 107n output latch, and to the anodal video data that will output to second data line of anodal D/A transducer 107p output latch.D/ A transducer 107p and 107n use the D/A conversion to a plurality of grayscale voltages that produce by the grayscale voltage generating circuit (not shown), and according to the video data that is input to D/ A transducer 107p and 107n the grayscale voltage of expecting are outputed to the first output buffer unit 120a.

Then, the first output buffer unit 120a is by using impedance conversion to grayscale voltage, and the grayscale voltage from D/A transducer 107p or D/A transducer 107n input is transformed to picture signal, and output image signal.After this, at the negative edge of expression first image output control signal 1 (XSTB1) constantly, connect switch 111, and will output to picture signal outlet terminal 109a and 109b (XOUT1 and XOUT2) by the picture signal that conversion obtains simultaneously thus.Particularly, from picture signal outlet terminal 109a (XOUT1) the output negative pole picture signal corresponding, from picture signal outlet terminal 109b (XOUT2) the output anodal picture signal corresponding with anodal video data with the negative pole video data.

By this way, any one in first moment that differs from one another and second moment outputs to picture signal respectively the data line of display panels 101.In other words, according to present embodiment, the quantity of the picture signal that each from source electrode driver is exported simultaneously is reduced to half of the picture signal quantity exported simultaneously from source electrode driver according to routine techniques, as the situation in first embodiment.This makes it possible to suppress otherwise can be at the peak point current of instantaneous appearance in each of source driver chip.Therefore, this makes it possible to suppress otherwise can come from the electromagnetic interference (EMI) noise of this peak point current.

In addition, in situation according to the source electrode driver 103 of present embodiment, output cathode picture signal and negative pole picture signal simultaneously.In each four frame period, by with before and after two outputs control signals (XSTB1 and XSTB2) alternately, per two frames staggered to the first and second data line output image signals the moment and to moment of the third and fourth data line output image signal.This makes it possible to improve picture quality.

In the situation of the 4th embodiment, by using two signals, promptly image output control signal 1 (XSTB1) and image output control signal 2 (XSTB2) are controlled from the video data of each and the output of picture signal in the source electrode driver 103.Yet, the invention is not restricted to this.As the situation among first embodiment, can use three or more image output control signals (XSTB).Can design adjacent picture signal outlet terminal and come respectively, for example, are set three different moment by mode with three different corresponding color R, G constantly and B at three moment output image signals that differ from one another.

In this case, any one in three kinds of colors of expectation is in identical moment output.In the situation of the some inversion driving system that uses color R, G and B, for the polarity of each the reverse image signal in the sub-pixel of representing color R, G and B respectively.Owing to this reason, the polarity of sub-pixel that has same color in any one polarity in R, the G that constitutes a pixel and the B sub-pixel and the neighbor is different.

In other words, from picture signal outlet terminal XOUT (6m-5) or picture signal outlet terminal XOUT (6m-2), the picture signal that will have opposed polarity respectively offers two R sub-pixels that are included in two neighbors, and wherein m is a natural number.In addition, from picture signal outlet terminal XOUT (6m-4) or picture signal outlet terminal XOUT (6m-1), the picture signal that will have opposed polarity respectively offers two G sub-pixels that are included in two neighbors.In addition, from picture signal outlet terminal XOUT (6m-3) or picture signal outlet terminal XOUT (6m), the picture signal that will have opposed polarity respectively offers two B sub-pixels that are included in two neighbors.

For this purpose, three image output control signals are provided, be image output control signal 1 (XSTB1), image output control signal 2 (XSTB2) and image output control signal 3 (XSTB3), and export the picture signal that will offer the sub-pixel that is included in the same color in the neighbor thus simultaneously.In other words, expectation comes control chart image signal outlet terminal XOUT (6m-5) and picture signal outlet terminal (6m-2) by using image output control signal 1 (XSTB1), by using image output control signal 2 (XSTB2) to come control chart image signal outlet terminal XOUT (6m-4) and picture signal outlet terminal XOUT (6m-1), reach by using image output control signal 3 (XSTB3) to come control chart image signal outlet terminal XOUT (6m-3) and picture signal outlet terminal XOUT (6m).

Although should be noted that by the example that provides liquid crystal indicator to have illustrated that driving circuit according to the present invention is not limited to liquid crystal indicator according to driving circuit of the present invention.Driving circuit according to the present invention can be used for various image display devices, comprises PDP and organic EL display.

Claims (14)

1. drive circuit chip, it comprises:

A plurality of picture signal entry terminals are used to receive picture signal;

A plurality of picture signal outlet terminals are used to respond the image output control signal that provides from the outside and come output image signal during same horizontal cycle, described picture signal is in a plurality of moment outputs that comprise first moment and second moment that was different from for first moment.

2. drive circuit chip as claimed in claim 1,

Wherein, described a plurality of picture signal outlet terminal comprises the first picture signal outlet terminal and the second picture signal outlet terminal, each first picture signal outlet terminal responds described first moment output image signal, each second picture signal outlet terminal responds described second moment output image signal, and

Wherein, the described first picture signal outlet terminal is arranged between the second picture signal outlet terminal.

3. drive circuit chip as claimed in claim 2,

Wherein, the described first picture signal outlet terminal is the odd number picture signal outlet terminal in the described drive circuit chip, and

Wherein, the described second picture signal outlet terminal is the even number picture signal outlet terminal in the described drive circuit chip.

4. drive circuit chip as claimed in claim 2,

Wherein, the described first picture signal outlet terminal is (4m-3) and (4m-2) picture signal outlet terminal in the described drive circuit chip, and wherein m is a natural number, and

Wherein, the described second picture signal outlet terminal is (4m-1) and the 4m picture signal outlet terminal in the described drive circuit chip, and wherein m is a natural number.

5. drive circuit chip as claimed in claim 2,

Wherein, the described first picture signal outlet terminal is (4m-3) and (4m) picture signal outlet terminal in the described drive circuit chip, and wherein m is a natural number, and

Wherein, the described second picture signal outlet terminal is (4m-2) and (4m-1) picture signal outlet terminal in the described drive circuit chip, and wherein m is a natural number.

6. drive circuit chip as claimed in claim 4,

Wherein, provide picture signal with first polarity to described (4m-3) and (4m-1) picture signal outlet terminal, and

Wherein, provide picture signal to described (4m-2) and 4m picture signal outlet terminal with second polarity that is different from first polarity.

7. drive circuit chip as claimed in claim 1,

Wherein, described a plurality of picture signal outlet terminals comprise: the first picture signal outlet terminal, and each response first is output image signal constantly; The second picture signal outlet terminal, each response are different from second moment output image signal in first moment; And the 3rd picture signal outlet terminal, each response is different from first and second constantly the 3rd output image signals constantly; And

Wherein, the described first picture signal outlet terminal is (3m-2) picture signal outlet terminal in the described drive circuit chip, and wherein m is a natural number,

The described second picture signal outlet terminal is (3m-1) picture signal outlet terminal in the described drive circuit chip, and wherein m is a natural number, and

Described the 3rd picture signal outlet terminal is (3m) picture signal outlet terminal in the described drive circuit chip, and wherein m is a natural number.

8. drive circuit chip as claimed in claim 7,

Wherein, the described first picture signal outlet terminal is (6m-5) and (6m-2) picture signal outlet terminal in the described drive circuit chip, and wherein m is a natural number,

The described second picture signal outlet terminal is (6m-4) and (6m-1) picture signal outlet terminal in the described drive circuit chip, and wherein m is a natural number, and

Described the 3rd picture signal outlet terminal is (6m-3) and (6m) picture signal outlet terminal in the described drive circuit chip, and wherein m is a natural number, and

Wherein provide picture signal with first polarity to described (6m-5), (6m-3) and (6m-1) picture signal outlet terminal, and

Wherein provide picture signal with second polarity that is different from first polarity to described (6m-4), (6m-2) and (6m) picture signal outlet terminal.

9. drive circuit chip as claimed in claim 1 wherein, is controlled the order in described a plurality of moment, so that the order in described a plurality of moment differs predetermined horizontal cycle with another, or differs the predetermined frame period with another.

10. drive circuit chip as claimed in claim 1, it also comprises:

Launch and holding circuit, be used to launch and keep order to be input to wherein digital displaying data, and and the described digital displaying data of line output;

The D/A translation circuit is used for the video data that is kept is used the D/A conversion; And

Buffer circuit,

Wherein, described expansion and holding circuit comprise: first latch cicuit is used for first video data that constantly latchs described video data the 3rd; And second latch cicuit, be used for second video data that latchs described video data constantly the 4th, and

Wherein, described first and second constantly, to as picture signal, output to described picture signal outlet terminal by to using the grayscale voltage that the D/A conversion is obtained from the output of described first latch cicuit with from the output of described second latch cicuit by impact damper.

11. drive circuit chip as claimed in claim 1, it also comprises:

Launch and holding circuit, be used to launch and keep order to be input to wherein simulation video data, and and the described simulation video data of line output; And

Buffer circuit,

Wherein, described expansion and holding circuit are made of a plurality of switches and a plurality of electric capacity, and comprise: first sampling hold circuit is used for first video data that constantly latchs described video data the 3rd; And second sampling hold circuit, be used for second video data that latchs described video data constantly the 4th, and

Wherein, described first and second constantly, voltage that will be kept by described first sampling hold circuit and the voltage that is kept by described second sampling hold circuit as picture signal, output to described picture signal outlet terminal by described buffer circuit.

12. drive circuit chip as claimed in claim 10, wherein, described first to the 4th is the moment that differs from one another constantly.

13. drive circuit chip as claimed in claim 10, wherein, described third and fourth is the identical moment constantly.

14. a display device, it comprises:

According to each drive circuit chip in the claim 1;

Be used for providing the controller of picture output signal to described drive circuit chip; And

Display panel by described drive circuit chip driving.

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