CN1819665A - Digital TV-set signalling comprehensive analyzer - Google Patents
Digital TV-set signalling comprehensive analyzer Download PDFInfo
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- CN1819665A CN1819665A CN 200610013308 CN200610013308A CN1819665A CN 1819665 A CN1819665 A CN 1819665A CN 200610013308 CN200610013308 CN 200610013308 CN 200610013308 A CN200610013308 A CN 200610013308A CN 1819665 A CN1819665 A CN 1819665A
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Abstract
A digital TV signal comprehensive analyzer belongs to digital TV field. The invention is that use software radio (SDR) theory demodulate digital TV signal to carry on the modulation territory analysis. The principle is that abstract the digital TV demodulating physical theory to a whole set mathematics algorithm, and then realizes the algorithm demodulation digital TV radio-frequency signal by the software (hard logical and soft logical comprehension) mode; distill the middle variable in the demodulating processing, get the data which the test needs, such as constellation information, MER/EVM information and BER information etc. The advantages of the invention are: strong function, good target consistency, simple production, moreover, the second function development is simple that only need to establish the algorithm mathematical model and the software realization.
Description
Technical field
The present invention relates to digital TV field, specifically a kind of digital TV-set signalling comprehensive analyzer.
Background technology
Continual renovation and maturation along with technology, Digital Television is more and more universal, and the power of digital television signal is the key point that influences the Digital Television effect, so the detection of the signal of Digital Television is just become a key technology, digital TV-set signalling comprehensive analyzer just arises at the historic moment.Digital TV-set signalling comprehensive analyzer (DVB-C analyzer) has modulating domain analyzing (comprising planisphere test and analysis, modulation error rate (MER)/vector amplitude error (EVM), the R-S decoding front and back error rates (BER) test), sign indicating number domain analysis and frequency-domain analysis function (channel power test, carrier-to-noise ratio test (C/N), parasitism output rejection ratio, frequency accuracy test and the analytic function of making an uproar mutually).
This quasi-instrument has two kinds of technical schemes at present:
A. adopt the mode of application-specific IC (ASIC): advantages such as the advantage of this mode is to be easy to realize, the R﹠D cycle is short.Shortcoming is that the accommodation of product is narrow, and a kind of asic chip only is fit to a kind of standard to be used, if the requirement of the multiple function of appliance requires will need a large amount of asic chips so, this can bring circuit complexity, debug difficulties, problem that cost is high; Next is that this technology upgrading replacement is difficult, if new standard signal needs the redesign system.The scope of application of summing up to get up this quasi-instrument is narrower.
B. adopt the mode of software radio, this mode has overcome above shortcoming, and advantage is that function is strong, and the standard of support is comprehensive; Circuit is simple, produces debugging easily; Be easy to upgrading, as long as the software of the new function of design does not need the change of hardware.The shortcoming of this scheme is, technical difficulty is very big, and the construction cycle is long.
Summary of the invention
The present invention adopts the theoretical demodulate digital TV signal of software radio (SDR) to carry out modulating domain analyzing.To be exactly that physical theory with the Digital Television demodulation is abstract be a whole set of mathematical algorithm to its principle, the mode by software (hard logic and soft logic in conjunction with) then, implementation algorithm demodulation Digital Television radiofrequency signal; Extract the intermediate variable in the demodulating process, obtain testing needed data, as constellation information, MER/EVM information and BER information etc.
In order to finish digital television signal integration test function, the present invention has designed broadband superheterodyne receiver hardware platform and algorithm mathematics model and software platform on this.
The hardware platform technical scheme adopts traditional superheterodyne receiver to add the digitlization processing mode.As shown in Figure 1, divide three parts: broadband superheterodyne reception part, high-speed data sampling section and DSP and embedded processing part.
The broadband superheterodyne receiver partly is to adopt superhet scheme commonly used, and double conversion is simple in structure, technology maturation.
This project realizes modulation domain, frequency-domain analysis function with this scheme.
The content of software platform mainly comprises: the design of FPGA hardware logic, the design of DVB modulating domain analyzing Mathematical Modeling, the design of frequency-domain analysis Mathematical Modeling and DSP and built-in PC software design realize.
The design of FPGA hardware logic realizes fast data buffer and high-speed data processing, and key technology comprises the design of high speed ping-pong buffers, high speed DDC (digital down converter) and the design of decimation in frequency Design of Filter.Adopt the VHDL design language to realize.
The design of DVB modulating domain analyzing Mathematical Modeling is the major function of this project, also is the core technology of project.As shown in Figure 2, model comprises that quadrature demodulation unit, interpolation and matched filtering unit, timing recovery loop, FFE equalizer and carrier recovery unit, carrier recovery loop, DFE equalizer, planisphere mapping and decision unit, deinterleaving and channel-decoding unit, energy separate randomization and MPEGII output unit, also has two output units in addition: planisphere output and BER test cell.This model adopts the characteristic of software radio, only needs configuration just can finish the digital television signal of various standards, and can also support the standard signal of the heart by upgrade software, and secondary development is simple.
DVB modulating domain analyzing model specifically as shown in Figure 2, the front end analog signal is digital signal after digitlization, data format is 14 bit strip symbol integers, data enter demodulating unit, will import intermediate-freuqncy signal and do Hilbert transform, are converted to digital orthogonal baseband signal; Baseband signal enters interpolator and matched filter; Constitute regularly restore funcitons module together with the timing recovery unit, this partial function is a sign indicating number clock of following the tracks of and lock input signal, does the interpolation of parabolic interpolation algorithm in corresponding moment point, recovers the signal value of corresponding moment point; The FFE equalizer is a CMA adaptive blind equalization algorithm, the influence of preliminary equalization channel frequency response; The effect of carrier recovery unit is frequency error and a phase difference of following the tracks of input signal, and does corresponding tracking, and the scope of tracking is ± 150KHz; The DFE equalizer is a decision-feedback type adaptive equalizing filter, and effect is the influence of further eliminating bandwidth efficient channel; Planisphere information can be exported in this unit.(ITU-T is AnnexA J.83, B﹠amp according to international standard with decision unit in the planisphere mapping; C DOCSIS EuroDOCSIS) does the mapping and the judgement of planisphere, and generates data, and (ITU-T is Annex A J.83, B﹠amp for these data based international standards; C DOCSIS EuroDOCSIS) makes corresponding deinterleaving, R-S decoding and energy and separates channel treatment processes such as randomization, the MPEGII ASCII stream file ASCII of outputting standard afterwards, and all above functions all are based on the settling mode of software radio.
Beneficial effect of the present invention: it is strong to have function, and indicator consilience is good, produces the simple advantage of debugging, and the secondary function exploitation is simple, only need set up algorithm mathematics model and software and realize getting final product.
Description of drawings
Fig. 1 is circuit system hardware and software principle block diagram
Fig. 2 is the modulating domain analyzing model
Embodiment
Embodiment 1
Contrast the description of drawings embodiments of the present invention below, Fig. 1 is circuit system hardware and software principle block diagram, and Fig. 2 is the modulating domain analyzing model.
The hardware platform technical scheme adopts traditional superheterodyne receiver to add the digitlization processing mode.Shown in figure one, divide three parts: broadband superheterodyne reception part, high-speed data sampling section and DSP and embedded processing part.
The high-speed data sampling section adopts pipeline system 50MSPS adc circuit, and the 14BIT quantization digit can be handled broadband signal, and dynamically big, sample circuit has 8M byte bulk sampling storage depth simultaneously, for various standard signal demodulation analysis provide the foundation.
DSP and embedded processing partly for adapting to big dynamic, high-speed signal processing, adopt high-speed floating point to count the technical scheme of dsp processor and high speed FPGA combination, have the processing speed of 1600/1200 MIPS/MFLOPS.Embedded processing partly adopts low-power-consumption embedded industrial microcomputer, and compact conformation is stable.
Algorithm mathematics model and software platform have adopted totally digitilized scheme, adopt the theoretical mode of software radio to realize item-function, though technical difficulty is very big, but it is strong to have function, indicator consilience is good, produce the simple advantage of debugging, and the secondary function exploitation is simple, only need sets up algorithm mathematics model and software and realize getting final product.
The content of software platform mainly comprises: the design of FPGA hardware logic, the design of DVB modulating domain analyzing Mathematical Modeling, the design of frequency-domain analysis Mathematical Modeling and DSP and built-in PC software design realize.
The design of FPGA hardware logic realizes fast data buffer and high-speed data processing, and key technology comprises the design of high speed ping-pong buffers, high speed DDC (digital down converter) and the design of decimation in frequency Design of Filter.Adopt the VHDL design language to realize.
The design of DVB modulating domain analyzing Mathematical Modeling is the major function of this project, also is the core technology of project.As shown in Figure 2, model comprises that quadrature demodulation unit, interpolation and matched filtering unit, timing recovery loop, FFE equalizer and carrier recovery unit, carrier recovery loop, DFE equalizer, planisphere mapping and decision unit, deinterleaving and channel-decoding unit, energy separate randomization and MPEGII output unit, also has two output units in addition: planisphere output and BER test cell.This model adopts the characteristic of software radio, only needs configuration just can finish the digital television signal of various standards, and can also support the standard signal of the heart by upgrade software, and secondary development is simple.
DVB modulating domain analyzing model specifically as shown in Figure 2, the front end analog signal is digital signal after digitlization, data format is 14 bit strip symbol integers, data enter demodulating unit, will import intermediate-freuqncy signal and do Hilbert transform, are converted to digital orthogonal baseband signal; Baseband signal enters interpolator and matched filter; Constitute regularly restore funcitons module together with the timing recovery unit, this partial function is a sign indicating number clock of following the tracks of and lock input signal, does the interpolation of parabolic interpolation algorithm in corresponding moment point, recovers the signal value of corresponding moment point; The FFE equalizer is a CMA adaptive blind equalization algorithm, the influence of preliminary equalization channel frequency response; The effect of carrier recovery unit is frequency error and a phase difference of following the tracks of input signal, and does corresponding tracking, and the scope of tracking is ± 150KHz; The DFE equalizer is a decision-feedback type adaptive equalizing filter, and effect is the influence of further eliminating bandwidth efficient channel; Planisphere information can be exported in this unit.(ITU-T is AnnexA J.83, B﹠amp according to international standard with decision unit in the planisphere mapping; C DOCSIS EuroDOCSIS) does the mapping and the judgement of planisphere, and generates data, and (ITU-T is Annex A J.83, B﹠amp for these data based international standards; C DOCSIS EuroDOCSIS) makes corresponding deinterleaving, R-S decoding and energy and separates channel treatment processes such as randomization, the MPEGII ASCII stream file ASCII of outputting standard afterwards, and all above functions all are based on the settling mode of software radio.
Technical indicator is as follows:
Modulated test
Modulation type
16/32/64/128/256QAM，QPSK?ITU-T?J.83?Annex?A，B&C
DOCSIS，EuroDOCSIS
Felt properties:
Up?to?128×4?In?Annex?B，
12×17?In?Annex?A/C
Planisphere shows QPSK 16/32/64128/256QAM
Band planisphere enlarging function
The test of digital carrier average power
Amplitude range: (30-120) dB μ V
Resolution: 0.01dB
Absolute precision: representative value ± 1.0dB@+20 ℃
Test specification: 1MHz-1000MHz
Bandwidth range: 200kHz-200MHz
Modulation error rate (MER)
Scope: (22-40) dB
Precision: ± 0.5dB (22-30) dB;
±1.0dB (30-35)dB
±1.8dB (35-40)dB
Vector error amount (EVM)
Scope: 0.65%-4.1%
The error rate (every clock) before and after the decoding
Scope 1e-9-2e-3
Symbol rate:
Scope: (1-7) MS/s
Claims (2)
1. digital TV-set signalling comprehensive analyzer, the superheterodyne receiver that its hardware using is traditional adds the digitlization processing mode, divide three parts: broadband superheterodyne reception part, high-speed data sampling section and DSP and embedded processing part, it is characterized in that: its software platform has adopted totally digitilized scheme to realize modulation domain, frequency-domain analysis function, and content mainly comprises: the design of FPGA hardware logic, the design of DVB modulating domain analyzing Mathematical Modeling, the design of frequency-domain analysis Mathematical Modeling and DSP and built-in PC software design;
The design of FPGA hardware logic realizes fast data buffer and high-speed data processing, mainly comprises the design of high speed ping-pong buffers, high speed DDC (digital down converter) and the design of decimation in frequency Design of Filter;
DVB modulating domain analyzing Mathematical Modeling design comprises that quadrature demodulation unit, interpolation and matched filtering unit, timing recovery loop, FFE equalizer and carrier recovery unit, carrier recovery loop, DFE equalizer, planisphere mapping and decision unit, deinterleaving and channel-decoding unit, energy separate randomization and MPEGII output unit, in addition two output units in addition: planisphere is exported and the BER test cell;
The front end analog signal is a digital signal after digitlization, and data enter demodulating unit, will import intermediate-freuqncy signal and do Hilbert transform, is converted to digital orthogonal baseband signal; Baseband signal enters interpolator and matched filter; Constitute regularly restore funcitons module together with the timing recovery unit, this partial function is a sign indicating number clock of following the tracks of and lock input signal, does the interpolation of parabolic interpolation algorithm in corresponding moment point, recovers the signal value of corresponding moment point; The FFE equalizer is a CMA adaptive blind equalization algorithm, the influence of preliminary equalization channel frequency response; The effect of carrier recovery unit is frequency error and a phase difference of following the tracks of input signal, and does corresponding tracking, and the scope of tracking is ± 150KHz; The DFE equalizer is a decision-feedback type adaptive equalizing filter, and effect is the influence of further eliminating bandwidth efficient channel, and planisphere information can be exported in this unit; (ITU-T is Annex A J.83, B﹠amp according to international standard with decision unit in the planisphere mapping; C DOCSIS EuroDOCSIS) does the mapping and the judgement of planisphere, and generates data, these data based international standards (ITU-TJ.83 Annex A, B﹠amp; C DOCSIS EuroDOCSIS) makes corresponding deinterleaving, R-S decoding and energy and separates channel treatment processes such as randomization, afterwards the MPEGII ASCII stream file ASCII of outputting standard.
2. method that in digital TV-set signalling comprehensive analyzer, realizes modulation domain, frequency-domain analysis, described digital TV-set signalling comprehensive analyzer hardware platform technical scheme adopts traditional superheterodyne receiver to add the digitlization processing mode, divide three parts: broadband superheterodyne reception part, high-speed data sampling section and DSP and embedded processing part
It is characterized in that: this method comprises the design of FPGA hardware logic, the design of DVB modulating domain analyzing Mathematical Modeling, the design of frequency-domain analysis Mathematical Modeling and DSP and built-in PC software design;
The design of-FPGA hardware logic realizes fast data buffer and high-speed data processing, mainly comprises the design of high speed ping-pong buffers, high speed DDC (digital down converter) and the design of decimation in frequency Design of Filter;
The design of-DVB modulating domain analyzing Mathematical Modeling, model comprises that quadrature demodulation unit, interpolation and matched filtering unit, timing recovery loop, FFE equalizer and carrier recovery unit, carrier recovery loop, DFE equalizer, planisphere mapping and decision unit, deinterleaving and channel-decoding unit, energy separate randomization and MPEGII output unit, also has two output units in addition: planisphere output and BER test cell;
The front end analog signal is a digital signal after digitlization, and data enter demodulating unit, will import intermediate-freuqncy signal and do Hilbert transform, is converted to digital orthogonal baseband signal; Baseband signal enters interpolator and matched filter; Constitute regularly restore funcitons module together with the timing recovery unit, be used to follow the tracks of and lock the sign indicating number clock of input signal, do the interpolation of parabolic interpolation algorithm, recover the signal value of corresponding moment point in corresponding moment point.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101516030A (en) * | 2009-04-10 | 2009-08-26 | 华硕电脑股份有限公司 | Data processing circuit and processing method with multi-format image coding and decoding functions |
| CN101227308B (en) * | 2007-12-17 | 2010-06-23 | 北京创毅视讯科技有限公司 | Analysis system and analysis method of mobile multimedia broadcast signal |
| CN102355591A (en) * | 2011-08-05 | 2012-02-15 | 天津市德力电子仪器有限公司 | China mobile multimedia broadcast signal demodulation analysis method for quasi real-time signal analyzer |
| CN101581734B (en) * | 2008-04-30 | 2014-03-05 | 特克特朗尼克公司 | Equalization simulator with training sequence detection for oscilloscope |
| US11729054B2 (en) | 2014-07-15 | 2023-08-15 | Comcast Cable Communications, Llc | Reconfigurable device for processing signals |
| CN117526957A (en) * | 2024-01-04 | 2024-02-06 | 秦玄汉(苏州)信息科技有限公司 | Analog-to-digital converter with optimal quantization bit number |
Families Citing this family (1)
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| CN101895699B (en) * | 2010-06-30 | 2012-11-28 | 天津市德力电子仪器有限公司 | Ground digital television signal demodulating, decoding and analyzing method for quasi-real-time signal analyzer |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101227308B (en) * | 2007-12-17 | 2010-06-23 | 北京创毅视讯科技有限公司 | Analysis system and analysis method of mobile multimedia broadcast signal |
| CN101581734B (en) * | 2008-04-30 | 2014-03-05 | 特克特朗尼克公司 | Equalization simulator with training sequence detection for oscilloscope |
| CN101516030A (en) * | 2009-04-10 | 2009-08-26 | 华硕电脑股份有限公司 | Data processing circuit and processing method with multi-format image coding and decoding functions |
| CN102355591A (en) * | 2011-08-05 | 2012-02-15 | 天津市德力电子仪器有限公司 | China mobile multimedia broadcast signal demodulation analysis method for quasi real-time signal analyzer |
| US11729054B2 (en) | 2014-07-15 | 2023-08-15 | Comcast Cable Communications, Llc | Reconfigurable device for processing signals |
| CN117526957A (en) * | 2024-01-04 | 2024-02-06 | 秦玄汉(苏州)信息科技有限公司 | Analog-to-digital converter with optimal quantization bit number |
| CN117526957B (en) * | 2024-01-04 | 2024-03-19 | 秦玄汉(苏州)信息科技有限公司 | Analog-to-digital converter with optimal quantization bit number |
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