CN102355591A - China mobile multimedia broadcast signal demodulation analysis method for quasi real-time signal analyzer - Google Patents
China mobile multimedia broadcast signal demodulation analysis method for quasi real-time signal analyzer Download PDFInfo
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Abstract
The invention discloses a China mobile multimedia broadcast (CMMB) signal demodulation analysis method for a quasi real-time signal analyzer. The method specifically comprises the following steps of: periodically acquiring data under the control of a data acquisition control module of a digital signal processor (DSP), performing the preprocessing of down-conversion and low-pass filtering on the data, and transmitting the processed data to the DSP by using a field programmable gate array (FPGA); performing the demodulation processing of interpolation, matched filtering, slight frequency offset compensation, time slot synchronization, fast Fourier transform (fft), valid data extraction and descrambling, channel equalization and the like on a received signal by using the DSP; and outputting channel power, a constellation diagram, frequency offset and symbol rate offset by the modulation processing, calculating values of a modulation error ratio (MER) and error vector magnitude (EVM) by analyzing the constellation diagram, reading the information of a demodulation chip and calculating a low density parity check (LDPC) block error ratio (LDPC BLER) and a Reed-Solomon (RS) BLER. By the method, the characteristics of low complexity, high flexibility and real-time decoding of quasi real-time signal analysis are ensured; and simultaneously, a data acquisition periodic control part is added for the characteristics of the CMMB signal to ensure the accuracy and reference of CMMB signal demodulation output.
Description
Technical field
The invention belongs to China Mobile's DMB (CMMB) signal demodulation analysis technical field.
Background technology
On October 24th, 2006, SARFT(The State Administration of Radio and Television) formally issues China Mobile multimedia broadcasting (being commonly called as mobile TV) industry standard, confirms to adopt the Mobile Multimedia Broadcasting industry standard of China's independent research.The CMMB signal characteristics maximum with respect to cable TV signal and DTMB (digital TV ground multimedia broadcasting) signal be exactly the modulation system of the TV programme that in a channel, transmits be unfixed.The signal of BPSK (biphase phase shift keying), QPSK (quarternary phase-shift keying (QPSK)) and 16QAM (quadrature amplitude modulation) can arbitrarily timesharing combined transmit.Present CMMB signal analysis has real-time analysis and quasi real time analyzes two kinds.Real-time analysis is the scheme that adopts chip or FPGA demodulation basically, and it is big to implement difficulty, very flexible.Quasi real time analysis is with the mode of DSP+FPGA+ASIC chip the signal limit to be gathered, and output is handled on the limit, and demodulation output is discontinuous.Quasi real time the complexity of Fen Xiing is relatively low, realizes flexibly.But because the characteristic of CMMB signal; Be applicable to the random acquisition of other standards; The method of deal with data then; Because the not stationarity of CMMB signal modulation system causes MER (modulation error rate), EVM (vector error) and the isoparametric statistical property of ENM (noise margin) can not reflect the general state of channel.
Summary of the invention
The present invention seeks to solve the not stationarity of existing method because of CMMB signal modulation system; Cause MER (modulation error rate), EVM (vector error) and the isoparametric statistical property of ENM (noise margin) can not reflect the problem of the general state of channel, a kind of quasi real time China Mobile's digital multimedia broadcasting signal demodulation analysis method of signal analyzer that is used for is provided.
The present invention adopts the timer that DSP carries in the signal analyzer quasi real time, and in conjunction with the characteristic of CMMB signal, timing acquiring assigned timeslot signal data carries out demodulation output, makes test result more accurate, has more project reference value.
Provided by the inventionly be used for quasi real time that the concrete steps of China Mobile's digital multimedia broadcasting signal demodulation analysis method of signal analyzer are:
1st, data acquisition
1.1st, FPGA is under the control of data acquisition and control module; Timing acquiring is the intermediate-freuqncy signal of signal analyzer quasi real time; And data are carried out the preliminary treatment of down-conversion and low-pass filtering, among the external memory synchronous DRAM SDRAM of DSP, supply signal to separate the data-storing after handling and call;
1.2nd, the workflow of data acquisition and control module
Demodulation beginning, the timing length that timer is set is 1 second, and the current time slots that the CMMB demodulation is set number equals target time slot number, and does not start the work of fft module, valid data extraction and descrambling module and channel equalization module;
After the demodulation locking, the timing length of timer is set at 2 seconds, and the current time slots that demodulation is come out number and target time slot number compare, and equate, then export current demodulation result, wait for regularly simultaneously and interrupting, and after interrupting taking place, carry out data acquisition; Unequal, then compensate the time of current time slots to target time slot, the make-up time=(40+ target time slot number-current time slots number) * 25ms;
DSP starts new data acquisition after regularly interrupting taking place, and carries out the CMMB demodulation, and affirmation current time slots number begins new feedback cycle;
2nd, signal demodulation
2.1st, the data that the 1st step was gathered under timer control; The entering signal demodulation; DSP carries out interpolation and matched filtering to data; Carry out tiny compensate of frequency deviation afterwards; Enter into the slot synchronization module,, do the frequency offset estimating of integral multiple through the isolated beacon part of slot synchronization; The result of frequency offset estimating feeds back to tuner, is used for accurate semaphore lock further;
2.2nd, the Cyclic Prefix of OFDM symbol and data volume are partly done relevantly, calculate the value of fractional part of frequency offset;
2.3rd, the data of fractional part of frequency offset feed back to tiny compensate of frequency deviation module through after first loop filter 1, do the compensation of tiny frequency deviation;
2.4th, the data volume of OFDM symbol part is after the fft conversion, and extracted valid data carries out descrambling to valid data;
2.5th, the data behind the descrambling; Opsition dependent extracts scattered pilot, with the phase difference estimation timing error of scattered pilot, and timing error is fed back to interpolation and matched filtering through second loop filter 2; The structure of loop filter 2 is identical with loop filter 1, but the loop coefficient is different; Carry out channel estimating with scattered pilot simultaneously, and the data body portion is carried out channel equalization with results estimated;
2.6th, from the output of channel equalization, extract the transmission indication information in the continuous pilot, the timeslot number in the transmission indication information is transferred to the data acquisition control part, the data acquisition of control next round;
3rd, demodulation output
3.1st, the current channel power of data computation from gathering;
3.2nd, according to the demodulation result after the 2.5th step channel equalization, output planisphere, output frequency skew simultaneously and symbol rate frequency deviation demodulating information;
3.3rd, planisphere analysis
Result according to the planisphere of exporting; Calculate the value of MER and EVM; Read SLCH service logical channels information and the low density parity check code LDPC of demodulation chip, the mistake piece number of Reed Solomon code RS, calculate LDPC BLER (Block Error Rate)/RS BLER with mistake piece number.
Advantage of the present invention and good effect:
The present invention is guaranteeing quasi real time signal analysis; Implementation complexity is low, flexibility is high and the characteristic of real-time decoding the time; To the characteristics of signals of CMMB, add data acquisition timing controlled part, the accuracy that guarantees CMMB signal demodulation output with can be with reference to property.
The inventive method quasi real time verifies that proof procedure and result are following on the signal analyzer (DS8831T and DS8853T) in the numeral of Deli Electronic Instrument Co., Ltd., Tianjin City's latest generation:
DSP operating frequency 200MHz, timing accuracy 1/50M second, timing length is 1 second before the semaphore lock, gathers 100 milliseconds data at every turn; Timing length is 2 seconds after the semaphore lock, gathers 50 milliseconds data at every turn.Carrier error estimation range ± 50KHz; Timing error estimation range ± 20ppm; Planisphere MER test specification (16QAM) 14dB-36dB; Timeslot number setting range 0-39, LDPC (low density parity check code) BLER (Block Error Rate)/RS (Reed Solomon code) BLER adds up duration 1 minute to 72 hours.
Description of drawings
Fig. 1 is that the CMMB signal frame structure is divided;
Fig. 2 is a CMMB signal demodulating process;
Fig. 3 is a loop filter structure;
Fig. 4 is the data collection task flow chart;
Fig. 5 is the TS information that chip solution accesses;
Fig. 6 is DSP demodulation output result.
Embodiment
Embodiment 1
The CMMB standard is the system towards mobile phone, PDA (palmtop PC), MP3, MP4, digital camera, the multiple portable terminal of notebook computer, utilizes the S-band satellite-signal to realize that the whole nation covers, and supports 25 cover TV programme and 30 cover broadcast programs.The physical layer signal of CMMB signal was 1 frame in 1 second, was divided into 40 time slots, and the length of each time slot is 25ms, comprised a beacon and 53 OFDM (OFDM) signal.Beacon is made up of with 2 identical synchronizing signals sender unit identification, and the OFDM symbol is made up of Cyclic Prefix and data volume, as shown in Figure 1.
The present invention designs soft demodulation scheme as shown in Figure 2 according to the characteristic of CMMB signal.Whole proposal comprises three parts: data acquisition, the signal demodulation is transferred output.
1. data acquisition:
FPGA under the control of data acquisition and control module, timing acquiring data, and data are carried out the preliminary treatment of down-conversion and low-pass filtering, and the data-storing after will handling supplies signal to separate among the external memory synchronous DRAM SDRAM of DSP to call.The target time slot of demodulation number is that the user sets according to TS (time slot) information table of chip demodulation output.
The workflow diagram of data acquisition and control module as shown in Figure 3.Therefore timeslot number need carry out just reading the timeslot number of institute's restituted signal after the complete signal demodulation with continuous pilot output.At the beginning of the demodulation; Before integer and fractional part of frequency offset are not proofreaied and correct; Fft (Fourier transform) valid data extraction and descrambling and channel equalization module cisco unity malfunction afterwards; Just there is not number output of correct current time slots yet; Therefore when beginning we timing length is set is 1 second; Current time slots number equals target time slot number, and does not start the work of fft module, valid data extraction and descrambling module and channel equalization module.This setting can be practiced thrift the locking time of whole signal demodulation.After the demodulation locking; The timing length of timer is set at 2 seconds (time that demodulation is current and the adjacent time-slots data are required); The current time slots that demodulation is come out number and target time slot number compare; Equal then; Export current demodulation result, wait for regularly simultaneously and interrupting, after interrupting taking place; Carry out data acquisition, the unequal time that then compensates current time slots to target time slot.The make-up time=(40+ target time slot number-current time slots number) * 25ms.DSP starts new data acquisition after regularly interrupting taking place, and carries out the CMMB demodulation, and affirmation current time slots number begins new feedback cycle.
2. the timer control data entering signal demodulation of collection down
Data through interpolation and matched filtering are carried out after the tiny compensate of frequency deviation; Enter into the slot synchronization module,, do the frequency offset estimating of integral multiple through the isolated beacon part of slot synchronization; The result of frequency offset estimating feeds back to tuner, is used for accurate semaphore lock further.It is relevant that the Cyclic Prefix of OFDM symbol and data volume are partly done, and calculates the value of fractional part of frequency offset.The data of fractional part of frequency offset feed back to tiny compensate of frequency deviation module through after the loop filter 1, do the compensation of tiny frequency deviation.The data volume part of OFDM symbol is after the fft conversion, and extracted valid data carries out descrambling to valid data.Data behind the descrambling, opsition dependent are extracted scattered pilot, with the phase difference estimation timing error of scattered pilot, and timing error are fed back to the data of interpolation and matched filtering through loop filter 2.Carry out channel estimating with scattered pilot simultaneously, and the data body portion is carried out channel equalization with results estimated.From the output of channel equalization, extract the transmission indication information in the continuous pilot.Timeslot number in the transmission information is transferred to the data acquisition control part, the data acquisition of control next round.
3. demodulation output
From the current channel power of gathering of data computation; Demodulation result according to second portion; The output planisphere; Frequency shift (FS) (carrier shift); Symbol rate frequency deviation information such as (timing slips); Result according to planisphere; Calculate the value of MER and EVM; Read SLCH (Service Logical Channel) service logical channels information and the LDPC of demodulation chip, the mistake piece number of RS, calculate LDPC (low density parity check code) BLER (Block Error Rate)/RS (Reed Solomon code) BLER with mistake piece number.
The inventive method is through quasi real time verifying that proof procedure and result are following on the signal analyzer (DS8831T and DS8853T) in the numeral of Deli Electronic Instrument Co., Ltd., Tianjin City's latest generation:
DSP operating frequency 200MHz, timing accuracy 1/50M second, timing length is 1 second before the semaphore lock, gathers 100 milliseconds data at every turn; Timing length is 2 seconds after the semaphore lock, gathers 50 milliseconds data at every turn.Carrier error estimation range ± 50KHz; Timing error estimation range ± 20ppm; Planisphere MER test specification (16QAM) 14dB-36dB; Timeslot number setting range 0-39, LDPC (low density parity check code) BLER (Block Error Rate)/RS (Reed Solomon code) BLER adds up duration 1 minute to 72 hours.
Claims (1)
1. one kind is used for quasi real time China Mobile's digital multimedia broadcasting signal demodulation analysis method of signal analyzer, it is characterized in that the concrete steps of this method are:
1st, data acquisition
1.1st, FPGA is under the control of data acquisition and control module; Timing acquiring is the intermediate-freuqncy signal of signal analyzer quasi real time; And data are carried out the preliminary treatment of down-conversion and low-pass filtering, among the external memory synchronous DRAM SDRAM of DSP, supply signal to separate the data-storing after handling and call;
1.2nd, the workflow of data acquisition and control module
Demodulation beginning, the timing length that the DSP timer is set is 1 second, and the current time slots that the CMMB demodulation is set number equals target time slot number, and does not start the work of fft module, valid data extraction and descrambling module and channel equalization module;
After the demodulation locking, the timing length of timer is set at 2 seconds, and the current time slots that demodulation is come out number and target time slot number compare, and equate, then export current demodulation result, wait for regularly simultaneously and interrupting, and after interrupting taking place, carry out data acquisition; Unequal, then compensate the time of current time slots to target time slot, the make-up time=(40+ target time slot number-current time slots number) * 25ms;
DSP starts new data acquisition after regularly interrupting taking place, and carries out the CMMB demodulation, and affirmation current time slots number begins new feedback cycle;
2nd, signal demodulation
2.1st, the data that the 1st step was gathered under timer control; The entering signal demodulation; DSP carries out interpolation and matched filtering to data; Carry out tiny compensate of frequency deviation afterwards; Enter into the slot synchronization module,, do the frequency offset estimating of integral multiple through the isolated beacon part of slot synchronization; The result of frequency offset estimating feeds back to tuner, is used for accurate semaphore lock further;
2.2nd, the Cyclic Prefix of OFDM symbol and data volume are partly done relevantly, calculate the value of fractional part of frequency offset;
2.3rd, the data of fractional part of frequency offset feed back to tiny compensate of frequency deviation module through after first loop filter, do the compensation of tiny frequency deviation;
2.4th, the data volume of OFDM symbol part is after the fft conversion, and extracted valid data carries out descrambling to valid data;
2.5th, the data behind the descrambling, opsition dependent are extracted scattered pilot, with the phase difference estimation timing error of scattered pilot, and timing error are fed back to the data of interpolation and matched filtering through second loop filter; Carry out channel estimating with scattered pilot simultaneously, and the data body portion is carried out channel equalization with results estimated;
2.6th, from the output of channel equalization, extract the transmission indication information in the continuous pilot, the timeslot number in the transmission indication information is transferred to the data acquisition control part, the data acquisition of control next round;
3rd, demodulation output
3.1st, the current channel power of data computation from gathering;
3.2nd, according to the demodulation result after the 2.5th step channel equalization, output planisphere, output frequency skew simultaneously and symbol rate frequency deviation demodulating information;
3.3rd, planisphere analysis
Result according to the planisphere of exporting; Calculate the value of MER and EVM; Read SLCH service logical channels information and the low density parity check code LDPC of demodulation chip, the mistake piece number of Reed Solomon code RS, calculate the Packet Error Ratio BLER of LDPC and RS sign indicating number with mistake piece number.
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Application publication date: 20120215 |