CN1787374A - Electrical level shifting circuit for OTP device - Google Patents
Electrical level shifting circuit for OTP device Download PDFInfo
- Publication number
- CN1787374A CN1787374A CN 200410089227 CN200410089227A CN1787374A CN 1787374 A CN1787374 A CN 1787374A CN 200410089227 CN200410089227 CN 200410089227 CN 200410089227 A CN200410089227 A CN 200410089227A CN 1787374 A CN1787374 A CN 1787374A
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- China
- Prior art keywords
- nmos
- level shift
- shift circuit
- pair
- pmos pipe
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Abstract
This invention discloses a level shift circuit used in an OTP device, in which, a PMOS tube ensures that the PN junction is not broken through by a serial mode and NMOS applies NW as the drain to ensure that the PN junction is not broken so as to enable the entire circuit to work under 12V.Another invented method is to use the substrate resistance of the PMOS tube to realize limit flow so as to endure high voltage and reduce the size of the device.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to the level shift circuit of a kind of OTP of being used for (but onetime programming one-time programming) device.
Background technology
In order to reduce cost, OTP technology can only increase once on the common process basis to be injected, and does not therefore have special high-voltage tube power supply road design.But need be during module programming, thereby need to adopt high-voltage tube design level shift circuit at the voltage that adds on the grid about 12V.Fig. 1 is classical level shift circuit, and in order to bear high pressure, metal-oxide-semiconductor MP1, MP2, MN1 and MN2 must use high-voltage tube, and this will inevitably increase production cost.If use common low pressure metal-oxide-semiconductor (as the metal-oxide-semiconductor that uses under the 5V voltage), will cause the puncture of PN junction, thereby influence the function and the long-term reliability of circuit.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of level shift circuit that is used for OTP parts, utilizes the design of common low voltage transistor can high voltage bearing level shift circuit, reduces the technology cost.
For solving the problems of the technologies described above, the level shift circuit that is used for OTP parts of the present invention, the combinational network that comprises a NMOS, this combinational network contains the nmos switch structure of two complementations, and be connected to the grid of a pair of PMOS pipe across, constitute the network that positive feedback is arranged, wherein, two NMOS pipes MN1, MN2 adopt the FD pipe, and a pair of PMOS pipe is made of MP1, MP2 and MP3, MP4 serial connection respectively.
Adopt after the said structure, can use low-voltage tube to constitute high-pressure level shift circuit.
The level shift circuit that is used for OTP parts of the present invention, can also adopt another technical scheme, it comprises the combinational network of a NMOS, this combinational network contains the nmos switch structure of two complementations, and be connected to the grid of a pair of PMOS pipe across, constitute the network that positive feedback is arranged, wherein, two NMOS pipes MN1, MN2 adopt the metal-oxide-semiconductor (drain electrode is the N trap) of FD type, and the substrate of a pair of PMOS pipe is connected with power supply VPPI by resistance R 1.
Adopt technique scheme can reduce in first kind of technical scheme of the present invention because the chip area that adopts series connection structure to bring increases problem.
Description of drawings
Fig. 1 is the level shift circuit schematic diagram of prior art;
Fig. 2 is level shift circuit technical scheme of the present invention () schematic diagram;
Fig. 3 is level shift circuit technical scheme of the present invention (a two) schematic diagram.
Embodiment
As shown in Figure 2, the level shift circuit that is used for OTP parts of the present invention comprises the combinational network of a NMOS, and this combinational network contains the nmos switch structure of two complementations, and is connected to the grid of a pair of PMOS pipe across, constitutes the network that positive feedback is arranged.Wherein, two NMOS pipes MN1, MN2 adopt the FD pipe, i.e. NMOS pipe drain electrode is made of the N trap, and a pair of PMOS pipe is made of MP1, MP2 and MP3, MP4 serial connection respectively.
After the employing said structure, because two NMOS manage the metal-oxide-semiconductor that MN1, MN2 have adopted the FD type, its drain electrode is the N trap, so the raising of the puncture voltage of PN junction, thereby has solved the withstand voltage problem of Nch (nmos pass transistor).Owing to be N-well process, the PMOS pipe can not improve withstand voltage with similar method, and therefore, the employing series connection structure is connected in series respectively by MP1, MP2 and MP3, MP4 and constitutes, so withstand voltage puncture voltage by 1 PN junction becomes the puncture voltage of 2 PN junctions.So far, realized that the use low-voltage tube constitutes high-pressure level shift circuit.
As shown in Figure 3, the level shift circuit that is used for OTP parts of the present invention, can also adopt another technical scheme, it comprises the combinational network of a NMOS, and this combinational network contains the nmos switch structure of two complementations, and is connected to the grid of a pair of PMOS pipe across, constitute the network that positive feedback is arranged, wherein, two NMOS pipes MN1, MN2 adopt the metal-oxide-semiconductor of FD type, and the substrate of a pair of PMOS pipe is connected with power supply VPPI by resistance R 1.
Adopt technique scheme can reduce in the scheme shown in Figure 2 because the chip area that adopts series connection structure to bring increases problem.Usually the PMOS side under high pressure will puncture, but (12～12.5V) is approaching, therefore adopts resistance R 1 restriction breakdown current can guarantee the reliability of circuit because the puncture voltage (11.5V) of PMOS is with working voltage.For selected word line, the OUT end will be exported VPPI; And for not selected word line, the OUT end will be exported
VPPI-Vd-Vbd＝12.5V-0.7-11.5V＝0.3V
Wherein VPPI is an external high pressure, and Vd is the positive bias-voltage of PN, and Vbd is the puncture voltage of P+NW.Because the cut-in voltage (Vt) of OTP parts is generally greater than 1.0V, so 0.3V can not make break-over of device, and circuit can operate as normal.So just avoided because the element layout area that adopts series connection structure to cause increases.
By the above, adopt technical scheme of the present invention can realize utilizing the requirement of low-voltage tube design level shift circuit fully as can be seen, reduced the technology cost, the competitiveness of this technology is improved.
Claims (2)
1, a kind of level shift circuit that is used for OTP parts, the combinational network that comprises a NMOS, this combinational network contains the nmos switch structure of two complementations, and be connected to the grid of a pair of PMOS pipe across, constitute the network that positive feedback is arranged, it is characterized in that: two NMOS pipes MN1, MN2 adopt the metal-oxide-semiconductor of FD type, and a pair of PMOS pipe is made of MP1, MP2 and MP3, MP4 serial connection respectively.
2, a kind of level shift circuit that is used for OTP parts, it comprises the combinational network of a NMOS, this combinational network contains the nmos switch structure of two complementations, and be connected to the grid of a pair of PMOS pipe across, constitute the network that positive feedback is arranged, it is characterized in that: two NMOS pipes MN1, MN2 adopt the metal-oxide-semiconductor of FD type, and the substrate of a pair of PMOS pipe is connected with power supply VPPI by resistance R 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410089227 CN1787374A (en) | 2004-12-08 | 2004-12-08 | Electrical level shifting circuit for OTP device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410089227 CN1787374A (en) | 2004-12-08 | 2004-12-08 | Electrical level shifting circuit for OTP device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1787374A true CN1787374A (en) | 2006-06-14 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410089227 Pending CN1787374A (en) | 2004-12-08 | 2004-12-08 | Electrical level shifting circuit for OTP device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1787374A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872646B (en) * | 2009-04-23 | 2013-09-11 | 上海华虹Nec电子有限公司 | NMOS (N-channel Metal Oxide Semiconductor) one time programmable device |
| CN104123963A (en) * | 2014-07-21 | 2014-10-29 | 中国人民解放军国防科学技术大学 | Level shifter realized by low-voltage transistor |
| CN104242909A (en) * | 2014-10-22 | 2014-12-24 | 上海芯导电子科技有限公司 | Level conversion circuit |
-
2004
- 2004-12-08 CN CN 200410089227 patent/CN1787374A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872646B (en) * | 2009-04-23 | 2013-09-11 | 上海华虹Nec电子有限公司 | NMOS (N-channel Metal Oxide Semiconductor) one time programmable device |
| CN104123963A (en) * | 2014-07-21 | 2014-10-29 | 中国人民解放军国防科学技术大学 | Level shifter realized by low-voltage transistor |
| CN104123963B (en) * | 2014-07-21 | 2018-03-30 | 中国人民解放军国防科学技术大学 | A kind of level translator realized with low voltage transistor |
| CN104242909A (en) * | 2014-10-22 | 2014-12-24 | 上海芯导电子科技有限公司 | Level conversion circuit |
| CN104242909B (en) * | 2014-10-22 | 2017-09-05 | 上海芯导电子科技有限公司 | A kind of level shifting circuit |
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