CN1773844A - Variable gain amplifier - Google Patents
Variable gain amplifier Download PDFInfo
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- CN1773844A CN1773844A CNA2005101033357A CN200510103335A CN1773844A CN 1773844 A CN1773844 A CN 1773844A CN A2005101033357 A CNA2005101033357 A CN A2005101033357A CN 200510103335 A CN200510103335 A CN 200510103335A CN 1773844 A CN1773844 A CN 1773844A
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- Prior art keywords
- gain amplifier
- nmos pass
- pass transistor
- variable gain
- amplifying unit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
- H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
- H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier using FETs
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Abstract
A variable gain amplifier (VGA) having stable input impedance matching and a stable noise figure in spite of a variation of an amplification gain is provided. In an embodiment of the VGA, a first stage of a cascode amplification unit has a fixed impedance regardless of a change of an amplification gain, and a variable gain determination unit comprised of a plurality of transistors is formed at an upper stage in the cascode amplification unit. Accordingly, a change of an input impedance of the cascode amplification unit due to the change of the amplification gain is minimized. In another embodiment of the VGA, an amplification gain of an amplification unit is controlled by adjusting a voltage applied to the amplification unit by controlling a current to be output by a current supply source, and stable input impedance matching and a stable noise figure are obtained.
Description
The application requires to be submitted on November 11st, 2004 priority of 10-2004-0091913 and two korean patent applications of 10-2004-0091912 of Korea S Department of Intellectual Property, and these two application full disclosures are in this, for reference.
Technical field
The equipment consistent with the present invention relates to a kind of variable gain amplifier (VGA), more particularly, relates to a kind of VGA that has stable input impedance matching and stable noise factor (NF) regardless of the variation of gain amplifier.
Background technology
Usually, VGA is used as prime (pre-power) amplifier in the transmitting element of wireless communication system, and it is constant to keep the amplitude that sends signal.VGA also is used as low noise amplifier (LNA) in the receiving element of wireless communication system, and hour under high gain mode, operate when the amplitude of input signal, perhaps when the amplitude of input signal is big, under low gain mode, operate, therefore suitable gain amplifier is provided.
Consider that signal to noise ratio (snr), frequency bandwidth, low distortion factor, the linearity, I/O coupling and noise characteristic or the like have designed such VGA.
For example, the noise factor (NF) of the VGA that uses in the first order of receiving element has great influence to the NF of whole receiving element.Therefore, to have stable, low NF be important to VGA.
Fig. 1 is the circuit diagram of traditional VGA.With reference to Fig. 1, traditional VGA comprises: the input matching unit 10 that comprises inductor L1; Cascode amplifier (cascode) amplifying unit 20 is used for input signal is amplified and the output amplifying signal; Output matching unit 30 comprises inductor L2 and capacitor C2.
The coupling of the input impedance of 10 realizations of input matching unit and cascode amplifier amplifying unit 20.The coupling of the output impedance of 30 execution of output matching unit and cascode amplifier amplifying unit 20.
Cascode amplifier amplifying unit 20 comprises common source amplifying unit 21 and common gate amplifying unit 23.Common source amplifying unit 21 comprises that a plurality of nmos pass transistor N1 to Ni and a plurality of switch SW 1 are to SWi.Common gate amplifying unit 23 is the cascode amplifiers that are connected to the common drain of nmos pass transistor N1 to Ni.
The grid that constitutes the nmos pass transistor N1 to Ni of common source amplifying unit 21 is connected respectively to the input port In and the first biasing source electrode Bias1 through switch SW 1 to SWi.The grid that constitutes the nmos pass transistor Nj of common gate amplifying unit 23 is connected to the second biasing source electrode Bias2.In Fig. 1, the first capacitor C1 is used as the nmos pass transistor Nj that makes common gate amplifying unit 23 and exchanges (AC) ground connection.
Cascode amplifier amplifying unit 20 has reduced the Miller effect that is caused by the parasitic capacitance between the grid of transistor N1 to Ni and the drain electrode, wherein, common source amplifying unit 21 and common gate amplifying unit 23 are incorporated into together in the cascode amplifier structure.Therefore, cascode amplifier amplifying unit 20 provides fabulous frequency characteristic, thereby is used continually in high-frequency amplifier.
In traditional like this VGA, gain amplifier is determined according to the optionally on/off operation of the nmos pass transistor N1 to Ni of common source amplifying unit 21.In other words, has different mutual conductance (g as nmos pass transistor N1 to Ni
m) value, and switch SW 1 to SWi is during by on/off optionally, among the nmos pass transistor N1 to Ni of different transconductance value which be the faradic value basis of the common drain of common source amplifying unit 21 have and be switched on and change.Therefore, gain amplifier changes according to which of on/off switch SW1 to SWi optionally.
For example, suppose that the first nmos pass transistor N1 has maximum mutual conductance in nmos pass transistor N1 to Ni, and i transistor Ni has minimum mutual conductance.In this case, if first switch SW 1 is connected and remaining disconnects, then traditional VGA operates having under the high gain mode of maximum gain amplifier.On the other hand, if only i transistor Ni connects, then traditional VGA operates having under the low gain mode of minimum gain amplifier.
Yet in aforesaid traditional VGA, the input impedance of common source amplifying unit 21 changes according to gain amplifier.Specifically, optionally conduction and cut-off is when changing gain amplifier as the nmos pass transistor N1 to Ni of common source amplifying unit 21, and the input impedance of common source amplifying unit 21 has changed.Therefore, in traditional VGA, input impedance changes according to gain amplifier, and NF also changes.
Fig. 2 A to 2D is the curve chart of gain that the VGA of Fig. 1 is shown, noise factor, input impedance matching and output impedance coupling.The curve chart of Fig. 2 A to 2D has shown in 4.7 to 5.3GHz frequency range the analog result to 0.18 μ m CMOS RF MOSFET.
With reference to Fig. 2 A, the VGA of Fig. 1 provides goodish characteristic under high gain mode.Yet shown in Fig. 2 B and Fig. 2 C, the VGA of Fig. 1 provides very poor noise factor and very poor input impedance matching under low gain mode.Under the frequency of operation of 5GHz, VGA has the input impedance matching of noise factor and the about-2dB of about 10dB under low gain mode, and these values are poorer than the value under the high gain mode.
In a word, in traditional VGA, input signal is connected to and comprises a plurality of transistorized common source amplifying units, and input impedance is switched on according in the transistor which and changes.Therefore, along with the variation of gain amplifier, it is unstable that input impedance becomes, and noise factor alters a great deal.
Summary of the invention
The invention provides a kind of variable gain amplifier that has stable noise factor regardless of the variation of gain amplifier.
The present invention also provides a kind of variable gain amplifier with stable input impedance, and described input impedance can easily not change along with the variation of gain amplifier.
According to an aspect of the present invention, provide a kind of VGA that changes gain amplifier, described VGA comprises: the common source amplifying unit, and it is constant that input impedance is kept in the input signal amplification simultaneously; The variable gain determining unit, its mode with cascode amplifier is connected to the common source amplifying unit, and will be amplified by the signal of common source amplifying unit output.The variable gain determining unit comprises: a plurality of transistors, described transistor is switched on/ends to change gain amplifier by the switch that is connected to described transistorized grid.
According to a further aspect in the invention, provide a kind of VGA that changes gain amplifier, described VGA comprises: differential common source amplifying unit comprises that transistor is right, and is used for receiving and amplifies differential wave to keep input impedance simultaneously constant; Differential variable gain determining unit, its mode with cascode amplifier is connected to differential common source amplifying unit, will be amplified by the signal of differential common source amplifying unit output.Differential variable gain determining unit comprises: a plurality of transistors, described transistor is switched on/ends to change gain amplifier by the switch that is connected to described transistorized grid.
According to a further aspect in the invention, provide a kind of VGA that changes gain amplifier, described VGA comprises: the gain amplifier control unit, and output is used to control the control signal of gain amplifier; Current source cell, output current, described electric current is controlled to gain amplifier proportional according to control signal; Bias unit, service voltage, described voltage is adjusted according to the electric current by current source cell output; Amplifying unit comprises transistor, and this transistorized gain amplifier changes according to the size of the voltage that bias unit is supplied with.
According to a further aspect in the invention, a kind of VGA that changes gain amplifier is provided, described VGA comprises: the cascode amplifier amplifying unit comprises first amplifying unit that is connected to input port and second amplifying unit that is connected to first amplifying unit in the mode of cascode amplifier; The gain amplifier control unit, output is used to control the control signal of the gain amplifier of cascode amplifier amplifying unit; Current source cell, output is controlled to and the proportional electric current of gain amplifier according to control signal; And bias unit, according to the voltage that will supply with first amplifying unit by the electric current adjustment of current source cell output.
Description of drawings
By the detailed description that the reference accompanying drawing carries out exemplary embodiment of the present invention, above-mentioned and other aspects of the present invention will become apparent, wherein:
Fig. 1 is the circuit diagram of traditional VGA;
Fig. 2 A to Fig. 2 D is the curve chart of characteristic that the VGA of Fig. 1 is shown;
Fig. 3 is the circuit diagram of VGA according to an exemplary embodiment of the present invention;
Fig. 4 is the circuit diagram according to switch of the present invention;
Fig. 5 is the circuit diagram of the VGA of another exemplary embodiment according to the present invention;
Fig. 6 A to Fig. 6 D is the curve chart of characteristic that the VGA of Fig. 3 and Fig. 5 is shown;
Fig. 7 is the circuit diagram of the VGA of another exemplary embodiment according to the present invention;
Fig. 8 is the circuit diagram of the VGA of another exemplary embodiment according to the present invention;
Fig. 9 is the circuit diagram of the VGA of another exemplary embodiment according to the present invention;
Figure 10 is the circuit diagram of the VGA of another exemplary embodiment according to the present invention; With
Figure 11 A to Figure 11 D is the curve chart that Fig. 7,8,9 and 10 characteristic are shown.
Embodiment
The exemplary embodiment of the present that is used as the active device that constitutes variable gain amplifier now with reference to mosfet transistor is described the present invention.Yet spirit of the present invention is not limited to the use of mosfet transistor.A those of ordinary skill for this area is clear that very much, and spirit of the present invention also can realize by the transistor that uses other, for example, and BJT, JFET, MESEFT or the like.
The VGA of the exemplary embodiment of the present of design consideration Fig. 3 and Fig. 5, thereby the first order of cascode amplifier amplifying unit can have fixing impedance regardless of the variation of gain amplifier, and comprises that a plurality of transistorized variable gain determining units are formed on the upper level of cascode amplifier amplifying unit.Therefore, prevented to cause the variation of the input impedance of VGA, and the variation of noise factor is stabilized owing to the variation of gain amplifier.
Fig. 3 is the circuit diagram of VGA according to an exemplary embodiment of the present invention.With reference to Fig. 3, VGA comprises input matching unit 100, cascode amplifier amplifying unit 200 and output matching unit 300.
Cascode amplifier amplifying unit 200 comprises common source amplifying unit 210 and variable gain determining unit 220.
Common source amplifying unit 210 comprises that single nmos pass transistor NM1 changes according to the variation of gain amplifier to prevent input impedance.The grid of nmos pass transistor NM1 is connected to node A to receive the signal that is exaggerated.The first bias voltage Bias1 is transferred to the grid of nmos pass transistor NM1 by node A, with biasing nmos pass transistor NM1.
The source ground of nmos pass transistor NM1, its drain electrode are connected to nmos pass transistor NM2, the NM3 that constitutes variable gain determining unit 220 ... source electrode with NMi.Therefore, the nmos pass transistor NM1 of common source amplifying unit 210 is nmos pass transistor NM2, NM3 of 220 that mode with cascode amplifier is connected to the variable gain determining unit ... and NMi.
Variable gain determining unit 220 comprises: nmos pass transistor NM2 to NMi, and they are connected to the drain electrode of nmos pass transistor NM1 jointly; A plurality of switch S 2, S3 ... and Si, be connected respectively to the grid of nmos pass transistor NM2 to NMi.The quantity of the nmos pass transistor of formation variable gain determining unit 220 and the responsible gain amplifier level of quantity of switch.
Switch S 2 to Si is connected to the second bias voltage Bias2, and on/off is with the conduction and cut-off operation of control nmos pass transistor NM2 to NMi.Nmos pass transistor NM2 to the NMi value of taking on a different character, for example, mutual conductance (g
m) value.Which is switched on and changes in according to transistor NM2 to NMi at the gain amplifier of the one-level of variable gain determining unit 220.The first capacitor C1 is used to make the AC signal ground.
Fig. 4 is the circuit diagram of each example in the switch S 2 to Si.With reference to Fig. 4, illustrative switch comprises nmos pass transistor NS1 and PMOS transistor PS1.The source electrode of nmos pass transistor NS1 is connected to the second bias voltage Bias2, and its drain electrode is connected to the source electrode of PMOS transistor PS1.The grounded drain of PMOS transistor PS1.Be input to the grid of nmos pass transistor NS1 and PMOS transistor PS1 by the switch controlling signal of switch control unit (not shown) output.Switch controlling signal is used for according to one in the gain amplifier value connection switch SW 2 to SWi.Node N between the source electrode of the drain electrode of nmos pass transistor NS1 and PMOS transistor PS1 is connected to nmos pass transistor NM2 ... perhaps NMi.
The switching manipulation of Fig. 4 is as follows.If switch controlling signal is a logic high, then nmos pass transistor NS1 and PMOS transistor PS1 are switched on, and the second bias voltage Bias2 that is input to nmos pass transistor NS1 source electrode is transferred to the nmos pass transistor NM2 of variable gain determining unit 220 by node N ... the perhaps grid of NMi.On the other hand, if switch controlling signal is a logic low, then nmos pass transistor NS1 and PMOS transistor PS1 are cut off, thereby the second bias voltage Bias2 is not transferred to nmos pass transistor NM2 ... the perhaps grid of NMi.
Return with reference to Fig. 3, output matching unit 300 comprises the second inductor L2 and the second capacitor C2, and impedance matching is provided for the output impedance for cascode amplifier amplifying unit 200 in a side of Node B.The end of the second inductor L2 is connected to external power source VDD, and its other end is connected to the drain electrode of nmos pass transistor NM2 to NMi.The end of the second capacitor C2 is connected to the drain electrode of nmos pass transistor NM2 to NMi, and its other end forms output port OUT.
In the operation of VGA in Fig. 3 with such structure, at first in common source amplifying unit 210, be exaggerated at input signal, secondly when amplifying by one of them of the nmos pass transistor NM2 to NMi that constitutes variable gain determining unit 220 then, the variation of gain amplifier takes place.In other words, there is not the variation of the gain amplifier that the nmos pass transistor NM1 by common source amplifying unit 210 causes, but gain amplifier is according to which is switched on and changes among the nmos pass transistor NM2 to NMi, and described nmos pass transistor NM2 to NMi is by switch S 2 to Si conduction and cut-off optionally.As a result, whole gain amplifier changes.
More particularly, be transferred to the grid of the nmos pass transistor NM1 of common source amplifying unit 210 by input matching unit 100 by the signal of input port In input.At first be outputted as the leakage current of nmos pass transistor NM1 by nmos pass transistor NM1 amplifying signal.Be in an amplification of conducting state among next nmos pass transistor NM2 to NMi of amplifying signal by variable gain determining unit 220.Because nmos pass transistor NM2 to NMi has different gain amplifier (that is, mutual conductance), so gain amplifier is according to which is switched on and changes among the nmos pass transistor NM2 to NMi.
Describe the variation of gain amplifier in detail with reference to following equation.At first, total mutual conductance G of cascode amplifier amplifying unit 200
mUtilize equation 1 to calculate:
Wherein, g
M1The mutual conductance of expression nmos pass transistor NM1, g
M2Be illustrated in the mutual conductance of the nmos pass transistor of conducting in the variable gain determining unit 220, g
Mb2Expression is owing to the mutual conductance of the nmos pass transistor of body effect conducting, r
O1The output impedance of expression nmos pass transistor NM1, r
O2The output impedance of the nmos pass transistor of expression conducting, that is, and the output impedance of the nmos pass transistor that expression is selected from the nmos pass transistor of variable gain determining unit 220.Learn total mutual conductance G of cascode amplifier amplifying unit 220 as equation 1 is approximate
mRely on the mutual conductance g of nmos pass transistor NM1
M1, by the mutual conductance g of nmos pass transistor NM1
M1Input signal is at first amplified.
Utilize equation 2 to calculate output impedance R about input port OUT one end
Out:
R
out＝[1+(g
m2+g
mb2)r
o2]r
o1+r
o2≈(g
m2+g
mb2)r
o2r
o1?…(2)
Here, the impedance when the load that is connected to output port OUT is R
LoadThe time, the gain amplifier A of cascode amplifier amplifying unit 200
vBy equation 3 expression, equation 3 is based on equation 1 and 2:
A
v＝-G
m(R
out//R
load)≈-g
m1(g
m2+g
mb2)r
o2r
o1 …(3)
With reference to equation 3, the mutual conductance g of nmos pass transistor NM1
M1Fix g
M2And g
Mb2According to which is switched on and changes among the nmos pass transistor NM2 to NMi of variable gain determining unit 220.As a result, gain amplifier A
vAccording to which is switched on and changes among the nmos pass transistor NM2 to NMi of variable gain determining unit 220.
In the VGA of Fig. 3, the first order of amplifying the cascode amplifier amplifying unit 200 of the signal that receives is made of nmos pass transistor NM1, thereby because the change of gain amplifier causes the change of input impedance can become limited.
As everyone knows, the first order of casacade multi-amplifier affects noise factor greatly.In the traditional VGA of Fig. 1, comprise that a plurality of transistorized common source amplifying units 210 are formed on the first order of cascode amplifier amplifying unit 200 to change gain amplifier.Therefore, the input impedance of cascode amplifier amplifying unit 200 is according to which is switched on and changes in the transistor of common source amplifying unit 210.The change of input impedance has negative influence to noise factor.Yet, in the VGA of Fig. 3 according to exemplary embodiment of the present invention, at first the common source amplifying unit 210 of amplification input signal is made of single nmos pass transistor NM1, and be used for determining that the variable gain determining unit 220 of gain amplifier is formed on the top one-level of the level of common source amplifying unit 210, thereby common source amplifying unit 210 and variable gain determining unit 220 are bonded to each other with the structure of cascode amplifier.Therefore, can prevent that change owing to gain amplifier from causing the change of input impedance.
Fig. 5 is the circuit diagram of the VGA of another exemplary embodiment according to the present invention.Except the VGA of Fig. 5 is constructed to the differential amplifier, the structure of the VGA of Fig. 5 is similar with operation to the structure of the VGA of Fig. 3 with operation.
With reference to Fig. 5, VGA comprises: input matching unit 400, differential cascode amplifier amplifying unit 500 and input matching unit 600.
Similar to the VGA of Fig. 3, input matching unit 400 provides and the input impedance phase impedance for matching of mating differential cascode amplifier amplifying unit 500.Input matching unit 400 comprises third and fourth inductor L3 and the L4, and they are connected respectively to differential input terminal mouth In+ and In-.Clearly, input matching unit 400 can also comprise capacitor or the like, and is not limited to shown in Figure 5 these.
Differential cascode amplifier amplifying unit 500 comprises differential common source amplifying unit 510 and differential variable gain determining unit 520.
Differential common source amplifying unit 510 comprises pair of transistor ND1 and ND2, their source ground, and they are arranged with the structure of differential amplifier.The grid of ND1 and ND2 is connected respectively to differential input terminal mouth In+ and In-, and is connected to the first bias voltage Bias1 received signal and bias voltage respectively.
The drain electrode of ND1 and ND2 is connected to the source electrode of a plurality of transistor ND3 to NDj in the mode of cascode amplifier, and described a plurality of transistor ND3 to NDj constitute differential variable gain determining unit 520.
Differential variable gain determining unit 520 comprises: transistor ND3 to NDj, and it is differential right to form; A plurality of switch S D3 to SDj are connected respectively to the grid of transistor NS3 to NDj.The differential wave Vout that amplifies outputs to the drain electrode of transistor ND3 to NDj.
Switch S D3 to SDj be connected to the second bias voltage Bias2 and optionally the conduction and cut-off differential transistor to ND3 and ND4 to NDi and NDj, to change the gain amplifier of differential variable gain determining unit 520.More particularly, transistor ND3, ND4 ... NDi and NDj are differential right, be connected to two right switches of each differential transistor according to gain amplifier by the while on/off.For example, be connected to the switch S D3 of grid of pair of differential transistor ND3 and ND4 and SD4 according to by the switch controlling signal of switch control unit (not shown) output by the while on/off.The gain amplifier of differential variable gain determining unit 520 changes being switched on according to which of the differential transistor centering of differential variable gain determining unit 520.The 3rd capacitor C3 is used as makes the AC signal ground.
Output matching unit 600 comprises the 5th inductor L5 and the 6th inductor L6, but also can comprise capacitor or the like in some cases.Output matching unit 600 provides the impedance that the output impedance with differential cascode amplifier amplifying unit 500 is complementary.
In the VGA of Fig. 5, the signal of importing by differential input terminal mouth In+ and In-is transferred to differential common source amplifying unit 510 by input matching unit 400, and is at first amplified by differential common source amplifying unit 510.Secondly amplifying signal is amplified by the pair of differential transistor in differential variable gain determining unit 520, and this is selectively logical by the on/off operation of switch S D3 to SDj to differential transistor.Secondly amplifying signal is outputted as differential wave Vout.
Similar to the VGA of Fig. 3, pair of transistor ND1 and the ND2 of the VGA of Fig. 5 in the VGA of first order formation Fig. 5 of differential cascode amplifier amplifying unit 500 is to be used for amplification input signal.Therefore, the change of the input impedance of VGA is along with the change of the gain amplifier of VGA can be reduced, and the change of noise factor can be stabilized.
The VGA of Fig. 3 and Fig. 5 can be used as single chip and realizes separately.Perhaps, only there is cascode amplifier amplifying unit 200 or 500 to can be used as single chip and realizes that remaining inductor and capacitor can be connected to external device (ED).
Fig. 6 A to Fig. 6 D shown respectively Fig. 3 and Fig. 5 are shown VGA each gain, noise factor, input impedance matching and the curve chart of output impedance coupling.The curve chart of Fig. 6 A to Fig. 6 D has shown in 4.7 to 5.3GHz frequency range the analog result to 0.18 μ m CMOS RF MOSFET.
With reference to Fig. 6 B, when the frequency of operation of 5GHz under the high gain mode and the difference between the noise factor under the low gain mode be 2.2dB, it is less than the 7.9dB in the noise factor curve chart of Fig. 2.Have stable noise factor even can see the VGA of Fig. 3 and Fig. 5 under low gain mode, their noise factor is not higher than 5dB yet.
Curve S with reference to Fig. 6 C
11, it shows input impedance matching, and the input impedance matching value in 4.7 to 5.3GHz whole frequency ranges under the low gain mode is not more than-10dB.Therefore, the VGA of Fig. 3 and Fig. 5 provides good input impedance matching.
As shown in Figure 6A, the control range of gain amplifier is about 13dB, so this scope is wide.Shown in Fig. 6 D, the output impedance matching value is not more than-8dB, so the VGA of Fig. 3 and Fig. 5 provides good output impedance coupling.
As mentioned above, because the change of gain amplifier and make noise factor stable, so the VGA of Fig. 3 and Fig. 5 can reduce the change of input impedance.
Fig. 7,8,9 and 10 has shown the exemplary embodiment of VGA, wherein, by controlling the voltage that is applied to amplifying unit by the Current Regulation of current source output, controls the gain amplifier of amplifying unit.
Fig. 7 is the circuit diagram of the VGA of another exemplary embodiment according to the present invention.With reference to Fig. 7, VGA comprises: gain amplifier control unit 1000, current source cell 1010, bias unit 1100 and amplifying unit 1200.
Gain amplifier control unit 1000 output gain amplifier control signals.
Current source cell 1010 receives the gain amplifier control signal from gain amplifier control unit 1000, and the gain amplifier Control current i of output dependence gain amplifier
cDigital analog converter (DAC) can be used as current source cell 1010.In this case, the gain amplifier control signal of being exported by gain amplifier control unit 1000 is a digital signal, and this digital gain amplification control signal is converted to gain amplifier Control current i by current source cell 1010
c
Bias unit 1100 is included in first and second division resistor (division resistor) R1 and the R2 that contact between service voltage VDD and the earthed voltage GND.First divides resistor R 1 is connected between service voltage VDD and the current source cell 1010, and second divides resistor R 2 is connected between current source cell 1010 and the earthed voltage GND.Be connected to amplifying unit 1200 at first and second nodes of dividing between resistor R 1 and the R2 1111.To describe after a while, the voltage that is applied to node 1111 is used as the control voltage of the gain amplifier that is used for definite amplifying unit 1200.Node 1111 has the voltage V1+V2 of the summation of voltage V1 and voltage V2, voltage V1 divides resistor R 1 by first and second and R2 divides service voltage VDD, and voltage V2 is by gain amplifier Control current i current source cell 1010 outputs and that flow through the second division resistor R 2
cProvide.
Specifically, by the first and second division resistor R 1 and R2 service voltage VDD is divided, thereby the voltage V1 of { R2/ (R1+R2) } * VDD size is applied to node 1111.Gain amplifier Control current ic by current source cell 1010 outputs divides resistor R 2 by being connected to second of earthed voltage GND, thus i
cThe voltage V2 of * R2 is applied to node 1111.Therefore, node 1111 has { (R2/ (R1+R2)) * VDD+ (i
c* R2) } big or small voltage V1+V2.
Amplifying unit 1200 comprises nmos pass transistor N10, and this nmos pass transistor N10 is by the grid received signal and amplify this signal.The grid of nmos pass transistor N10 is connected to node 1111 and input port In.As shown in Figure 7, also can comprise the inductor L10 that is connected between nmos pass transistor N10 and the node 1111, be connected capacitor C10 between node 1111 and the input port In or the like to realize input impedance matching.
As shown in Figure 7, nmos pass transistor N10 is the commonsource amplifier with source electrode of grid by its received signal and ground connection.By of the drain electrode output of nmos pass transistor N10 amplifying signal by nmos pass transistor N10.Be used for the inductor L11 of output impedance coupling and the drain electrode that capacitor C11 can be connected to nmos pass transistor N10.
In the operation of the VGA of Fig. 7, gain amplifier control unit 1000 outputs to current source cell 1010 with the gain amplifier control signal, so that determine will be by the gain amplifier Control current i of current source cell 1010 outputs
cSize.
Current source cell 1010 outputs are controlled to and the proportional gain amplifier Control current of gain amplifier i according to the gain amplifier control signal
cFor example, if the gain amplifier control signal is to be used to increase gain amplifier, then current source cell 1010 increases gain amplifier Control current i
cSize and export the gained electric current.If the gain amplifier control signal is to be used to reduce gain amplifier, then current source cell 1010 reduces gain amplifier Control current i
eSize and export the gained electric current.
Gain amplifier Control current i by current source cell 1010 outputs
cFlow through second and divide resistor R 2, thus i
cThe voltage V2 of xR2 is applied to node 1111.Service voltage VDD is divided according to first and second ratios of dividing the resistance of resistor R 1 and R2, thereby the voltage V1 of { R2/ (R1+R2) } * VDD also is applied to node 1111.As a result, the service voltage based on gain amplifier Control current ic and division calculates { (R2/ (R1+R2)) * VDD+ (i
c* R2) size voltage V1+V2 be applied to node 1111.
The gain amplifier A of the nmos pass transistor N10 of amplifying unit 1200
vBecause underlying cause relies on the voltage V1+V2 that is applied to node 1111.
The mutual conductance g of nmos pass transistor N10
M1Represent by equation 4:
Because electron mobility μ
n, the plane-parallel capacitor per unit area capacitor C
Ox, the width W of channel region, the length L and the threshold voltage V of channel region
ThBe by the treatment technology that is used to make nmos pass transistor N10 and definite constant, so the mutual conductance g of nmos pass transistor N10
M1Dependence is applied to the grid of nmos pass transistor N10 and the voltage V between the source electrode
GsAs everyone knows, the gain amplifier A of the nmos pass transistor N10 of amplifying unit 1200
vBe mutual conductance g
M1With output impedance R
OutProduct, that is, and (g
M1* R
Out).Therefore, as the grid voltage V of nmos pass transistor N10
GsDuring change, the mutual conductance g of nmos pass transistor N10
M1Change, and the gain amplifier A of nmos pass transistor N10
vAlso change.
Therefore, changed will be by the gain amplifier Control current i of current source cell 1010 outputs for the VGA of Fig. 7
cSize, to adjust the grid voltage of nmos pass transistor N10, changed the gain amplifier of nmos pass transistor N10 thus.In addition, in the VGA of Fig. 7,, thereby can obtain stable input impedance matching even when gain amplifier changes, also can not change in the input impedance of grid one end of nmos pass transistor N10.
Fig. 8 is the circuit diagram of the VGA of another exemplary embodiment according to the present invention.Except the structure of the employing of the VGA among Fig. 8 differential amplifier, the VGA of Fig. 8 is similar to the VGA of Fig. 7, and this differential amplifier will amplify by the differential wave that input port In+ and In-import.
Specifically, the VGA of Fig. 8 comprises: gain amplifier control unit 2000, current source cell 2010, bias unit 2100 and differential motion amplifying unit 2200.
Similar to the VGA of Fig. 7, the current source cell 2010 output gain amplifier Control current i of Fig. 8
c, the value of this gain amplifier Control current is according to the gain amplifier control signal Be Controlled that receives from gain amplifier control unit 2000, with proportional with gain amplifier.
The voltage V1 and the i of { R2/ (R1+R2) } * VDD size
cThe voltage V2 of * R2 size is applied to first and second nodes of dividing between resistor R 1 and the R2 2111, the voltage V1 of described { R2/ (R1+R2) } * VDD size obtains described i by the first and second division resistor R 1 and the R2 that utilizes bias unit 2100 with service voltage VDD division
cThe voltage V2 of * R2 size divides the gain amplifier Control current i of resistor R 2 by flowing through second
cAnd obtain.
Differential motion amplifying unit 2200 comprises pair of differential nmos pass transistor N20 and N21.The grid of nmos pass transistor N20 and N21 is connected respectively to differential input terminal mouth In+ and In-, and is connected to node 2111, their source ground.
As shown in Figure 8, be used between the inductor L20 of input impedance matching and the grid and node 2111 that L21 also can be included in nmos pass transistor N20 and N21.In addition, be used for the capacitor C20 of input impedance matching and C21 also can be included between node 2111 and the differential input terminal mouth In+ respectively and between node 2111 and the differential input terminal mouth In-.
Be output as differential wave Vout by of the drain electrode of differential motion amplifying unit 2200 amplifying signals by nmos pass transistor N20 and N21.Be used for the drain electrode that the inductor L22 of output impedance coupling and L23 and capacitor C22 and C23 also can be connected to nmos pass transistor N20 and N21.
The VGA class of operation of Fig. 8 is similar to the VGA of Fig. 7.In other words, be applied to the voltage of node 2111, that is, the nmos pass transistor N20 of differential motion amplifying unit 2200 and the grid voltage of N21 are according to the gain amplifier Control current i by current source cell 2010 outputs
cSize and change.Therefore, the change of the mutual conductance of differential motion amplifying unit 2200 has caused the change of the gain amplifier of differential motion amplifying unit 2200.
Therefore, in the VGA of Fig. 8, the gain amplifier of differential motion amplifying unit 2200 changes along with the change of the grid voltage that is applied to nmos pass transistor N20 and N21, and the input impedance of nmos pass transistor N20 and N21 is stable.
Fig. 9 is the circuit diagram of the VGA of another exemplary embodiment according to the present invention.Except cascode amplifier amplifying unit 3200 replacement differential motion amplifying unit 2200 were used, the VGA of Fig. 9 was similar to the VGA of Fig. 8.Because cascode amplifier amplifying unit 3200 can improve the insulating properties between input port and the output port, so can prevent owing to disturb the noise that produces between input port and the output port.
Specifically, the VGA of Fig. 9 comprises: gain amplifier control unit 3000, current source cell 3010, bias unit 3100 and cascode amplifier amplifying unit 3200.
Similar to the VGA of Fig. 7 and Fig. 8, current source cell 3010 output gain amplifier Control current i
c, this gain amplifier Control current is according to the gain amplifier control signal Be Controlled that receives from gain amplifier control unit 3000, with proportional with gain amplifier.
Cascode amplifier amplifying unit 3200 comprises: first amplifying unit 3210 and second amplifying unit 3220, they are connected to each other in the mode of cascode amplifier.More particularly, divide the grid that node 3111 between resistor R 2 and the R3 is connected to nmos pass transistor N30 at the second and the 3rd of bias unit 3100, nmos pass transistor N30 constitutes first amplifying unit 3210.Divide the grid that node 3112 between resistor R 1 and the R2 is connected to nmos pass transistor N31 at first and second of bias unit 3100, nmos pass transistor N31 constitutes second amplifying unit 3220.It is apparent that for those of ordinary skill in the art, first of bias unit 3100 is divided resistor R 1, the second division resistor R 2 and the 3rd is divided resistor R 3 and can be replaced by load component, and the quantity of the division resistor of formation bias unit 3100 can change.
The grid of the nmos pass transistor N30 of first amplifying unit 3210 is connected to input port In, its source ground.The drain electrode of nmos pass transistor N30 is connected to the source electrode of nmos pass transistor N31 of second amplifying unit 3220 to form the cascode amplifier structure.By of the drain electrode output of nmos pass transistor N31 amplifying signal by nmos pass transistor N31.
In Fig. 9, be connected grid and the inductor L30 between the node 3111 of nmos pass transistor N30 and be connected node 3111 and input port In between capacitor C30 be used to realize input impedance matching.The capacitor C31 that is connected between node 3112 and the earthed voltage GND is used as the AC ground connection that makes nmos pass transistor N31.The inductor L31 and the capacitor C32 that are connected to nmos pass transistor N31 drain electrode are used to realize the output impedance coupling.
In the operation of the VGA with this spline structure of Fig. 9, gain amplifier control unit 3000 is operated in the mode identical with the VGA of Fig. 7 and Fig. 8 with current source cell 3010.In other words, gain amplifier control unit 3000 outputs to current source cell 3010 with the gain amplifier control signal, will be by the gain amplifier Control current i of current source cell 3010 outputs with control
cSize.
Gain amplifier Control current i by current source cell 3010 outputs
cFlow through the 3rd and divide resistor R 3.Therefore, i
cThe voltage V2 of * R3 size is applied to node 3111.Service voltage VDD divides resistor R 1, the second division resistor R 2 and the 3rd ratio of dividing the resistance of resistor R 3 according to first and is divided, thereby the voltage V1 of { R3/ (R1+R2+R3) } * VDD size is applied to node 3111.Therefore, { (R3/ (R1+R2+R3)) * VDD+ (i
c* R3) size voltage V1+V2 be applied to node 3111, this voltage is by gain amplifier Control current i
cCalculate with the service voltage VDD that divides.
Service voltage VDD divides resistor R 1, second by first and divides resistor R 2 and 3 divisions of the 3rd division resistor R, so the voltage of { (R2+R3)/(R1+R2+R3) } * VDD size is applied to node 3112, the nmos pass transistor N31 that is connected to node 3112 is biased.
Signal by input port In input is amplified by the nmos pass transistor 3210 of cascode amplifier amplifying unit 3200 and 3220.The grid voltage of the nmos pass transistor N30 of the gain amplifier of cascode amplifier amplifying unit 3200 and first amplifying unit 3210, the voltage that promptly is applied to node 3111 is determined pro rata.To be described as the reason of the gain amplifier of what cascode amplifier amplifying unit 3200 now according to the voltage change of node 3111.
The mutual conductance of supposing the nmos pass transistor N30 of first amplifying unit 3210 is g
M1, the output impedance of nmos pass transistor N30 is r
O1, the mutual conductance of the nmos pass transistor N31 of second amplifying unit 3220 is g
M2, the output impedance of nmos pass transistor N31 is r
O2, because the mutual conductance of the nmos pass transistor N31 that body effect causes is g
Mb2, the mutual conductance G of cascode amplifier amplifying unit 3200 then
mBe expressed as equation 5:
With reference to equation 5, the mutual conductance G of cascode amplifier amplifying unit 3200
m, the mutual conductance that depends on the nmos pass transistor N30 of first amplifying unit 3210 is g
M1, input signal is transferred to this nmos pass transistor N30 at first.
Output impedance R at the cascode amplifier amplifying unit 3200 of output port OUT one side
OutBe expressed as equation 6:
R
out＝[1+(g
m2+g
mb2)r
o2]r
o1+r
o2≈(g
m2+g
mb2)r
o2r
o1(6)
The gain amplifier A of cascode amplifier amplifying unit 3200
vBe expressed as equation 7, it is based on equation 5 and 6:
A
v＝-G
mR
out≈-g
m1(g
m2+g
mb2)r
o2r
o1 …(7)
With reference to equation 7, r
O1, r
O2, g
M2And g
Mb2Value fix, so the gain amplifier A of cascode amplifier amplifying unit 3200
vRely on the mutual conductance g of nmos pass transistor N30
M1Shown in equation 4, the mutual conductance g of nmos pass transistor N30
M1According to the grid of nmos pass transistor N30 and the voltage V between the source electrode
GsAnd change.
Therefore, will be by control by the gain amplifier Control current i of current source cell 3010 outputs
cSize regulate the voltage of the nmos pass transistor N30 of first amplifying unit 3210, the VGA of Fig. 9 can change gain amplifier.
In addition, because no matter the change of gain amplifier, the input impedance of cascode amplifier amplifying unit 3200 is fixed, so even noise factor also can be stable when gain amplifier changes.
Figure 10 is the circuit diagram of the VGA of another exemplary embodiment according to the present invention.Except differential cascode amplifier amplifying unit 4200 replaces cascode amplifier amplifying units 3200 and being comprised, the VGA of Figure 10 is similar to the VGA of Fig. 9, and this differential cascode amplifier amplifying unit 4200 comprises: differential transistor is to N40 and N41 and N42 and N43.
The VGA of Figure 10 comprises: gain amplifier control unit 4000, current source cell 4010, bias unit 4100 and differential cascode amplifier amplifying unit 4200.
Similar to Fig. 7, Fig. 8 with Fig. 9, current source cell 4010 output gain amplifier Control current i
c, this gain amplifier Control current is according to receiving the gain amplifier control signal and Be Controlled from gain amplifier control unit 4000, with proportional with gain amplifier.
The voltage of { (R2+R3)/(R1+R2+R3) } * VDD size that service voltage VDD is divided into is applied to first of bias unit 4100 and divides the resistor R 1 and second node of dividing between the resistor R 2 4112.From gain amplifier Control current i
c{ (R3/ (R1+R2+R3)) * VDD+ (i with the service voltage VDD acquisition of dividing
c* R3) } voltage of size is applied to second and divides resistor R 2 and the 3rd node of dividing between the resistor R 3 4111.
Differential cascode amplifier amplifying unit 4200 comprises: first differential motion amplifying unit 4210 and second differential motion amplifying unit 4220.First differential motion amplifying unit 4210 comprises: the differential nmos pass transistor of common source is to N40 and N41, their source ground.The grid of nmos pass transistor N40 and N41 is connected respectively to differential input terminal mouth In+ and In-, and is connected to node 4111.
Second differential motion amplifying unit 4220 comprises: pair of differential nmos pass transistor N42 and N43 are connected to first differential motion amplifying unit 4210 in the mode of cascode amplifier.Specifically, the source electrode of nmos pass transistor N42 is connected to the drain electrode of nmos pass transistor N40, and the source electrode of nmos pass transistor N43 is connected to the drain electrode of nmos pass transistor N41, has therefore formed the differential amplifier with cascode amplifier structure.
The nmos pass transistor N42 of second differential motion amplifying unit 4220 and the grid of N43 are connected to node 4112.Differential wave Vout is by the drain electrode output of nmos pass transistor N42 and N43.
Inductor L40 and L41 and capacitor C40 and C41 are used to realize input impedance matching, inductor L40 and L41 are connected between the grid and node 4111 of the nmos pass transistor N40 of first differential motion amplifying unit 4210 and N41, and capacitor C40 and C41 are connected between node 4111 and differential input terminal mouth In+ and the In-.
Be connected the AC ground connection that the grid of the nmos pass transistor N42 of second differential motion amplifying unit 4220 and N43 and the capacitor C42 between the earthed voltage GND and C43 are included to make nmos pass transistor N42 and N43.Be connected to the inductor L42 of nmos pass transistor N42 and N43 drain electrode and L43 and capacitor C42 and C43 and be used to realize the output impedance coupling.
Therefore, will regulate the nmos pass transistor N40 of first differential motion amplifying unit 4210 and the grid voltage of N41 by the size of the gain amplifier Control current ic of current source cell 4010 output by control, the VGA with this spline structure of Figure 10 can change gain amplifier.In addition, because no matter the change of gain amplifier, the input impedance of differential cascode amplifier amplifying unit 4200 is fixed, so even noise factor also is stable when gain amplifier changes.
Figure 11 A to Figure 11 D has shown each the curve chart of gain, noise factor, input impedance matching and output impedance coupling of Fig. 7,8,9 and 10 VGA has been shown.The curve chart of Figure 11 A and Figure 11 D has shown in 5 to 6GHz frequency range the analog result to 0.18 μ m CMOS RF MOSFET.
With reference to Figure 11 B, when the 5GHz frequency of operation under the high gain mode and the difference between the noise factor under the low gain mode be 3.3dB, its be in the noise factor curve chart of Fig. 2 7.9dB 40%.
Curve S with reference to Figure 11 C and 11D
11And S
22, they show input impedance matching and output impedance coupling, in the frequency of operation of 5.5GHz, the value of input impedance matching and output impedance coupling is not more than respectively-15dB and-14dB.Therefore, Fig. 7,8,9 and 10 VGA provide good input and output impedance matching.
As mentioned above, Fig. 7,8,9 and 10 VGA can control gain amplifier by regulation voltage, and affiliated voltage obtains and be applied to amplifying unit 1200,2200,3200 and 4200 from the electric current by current source cell output.Therefore, the change of the noise factor of the change of dependence gain amplifier is little, and the output impedance coupling is stabilized.
In VGA according to the present invention, can prevent to rely on the change of input impedance of the change of gain amplifier, thereby can improve noise factor.
In addition, even the input and output impedance matching also can be stabilized when gain amplifier changes.
And, utilize the control of the gain amplifier of the electric current of supplying with by current source cell that the scope of gain amplifier is broadened, and gain amplifier is fine adjusted.
Though specify and described the present invention with reference to exemplary embodiment of the present invention, but will be understood by those skilled in the art that, under the situation that does not break away from the spirit and scope of the present invention that claim limits, can carry out various changes on form and the details to it.
Claims (24)
1, a kind of variable gain amplifier that changes gain amplifier, described variable gain amplifier comprises:
The common source amplifying unit, it is constant that input impedance is kept in the input signal amplification simultaneously;
The variable gain determining unit, its mode with cascode amplifier is connected to the common source amplifying unit, and will amplify by the signal of common source amplifying unit output, wherein, the variable gain determining unit comprises a plurality of transistors, described transistor is switched on/ends by the switch that is connected to described transistor gate, to change gain amplifier.
2, variable gain amplifier as claimed in claim 1, wherein, the common source amplifying unit comprises nmos pass transistor, and described nmos pass transistor is a commonsource amplifier, the signal that the is exaggerated grid by described nmos pass transistor is received, and the source ground of described nmos pass transistor.
3, variable gain amplifier as claimed in claim 1, wherein, the transistor of variable gain determining unit is a nmos pass transistor, and the source electrode of described nmos pass transistor is connected to the drain electrode of common source amplifying unit jointly, and amplifying signal is by the drain electrode output of described nmos pass transistor.
4, a kind of variable gain amplifier that changes gain amplifier, described variable gain amplifier comprises:
Differential common source amplifying unit comprises that transistor is right, and is used for receiving and amplifies differential wave and keep the input impedance constant simultaneously;
Differential variable gain determining unit, its mode with cascode amplifier is connected to differential common source amplifying unit, and will amplify by the signal of differential common source amplifying unit output, wherein, differential variable gain determining unit comprises a plurality of transistors, described a plurality of transistor is switched on/ends by the switch that is connected to described transistorized grid, to change gain amplifier.
5, variable gain amplifier as claimed in claim 4, wherein, the transistor of differential variable gain determining unit is a nmos pass transistor, the source electrode of described nmos pass transistor is connected to the drain electrode of described differential common source amplifying unit, and the differential wave of amplification is by the drain electrode output of described nmos pass transistor.
6, a kind of variable gain amplifier that changes gain amplifier, described variable gain amplifier comprises:
The gain amplifier control unit, output is used to control the control signal of gain amplifier;
Current source cell, output current, described electric current is controlled to gain amplifier proportional according to described control signal;
Bias unit, service voltage, described voltage is adjusted according to the electric current by current source cell output;
Amplifying unit comprises the transistor with the gain amplifier that changes according to the voltage of being supplied with by bias unit.
7, variable gain amplifier as claimed in claim 6, wherein, bias unit comprises:
First divides resistor, is connected between service voltage and the current source cell;
Second divides resistor, is connected between current source cell and the earthed voltage.
8, variable gain amplifier as claimed in claim 7, wherein, the electric current of being exported by current source cell flows through the second division resistor, thus first and second voltages of dividing the node between the resistors change.
9, variable gain amplifier as claimed in claim 6, wherein, the transistor of amplifying unit is a nmos pass transistor, the source ground of described nmos pass transistor, grid is connected to bias unit and input port, thereby gain amplifier changes according to the voltage of being supplied with by bias unit.
10, variable gain amplifier as claimed in claim 6, wherein, the control signal of being exported by the gain amplifier control unit is a digital signal.
11, variable gain amplifier as claimed in claim 10, wherein, current source cell comprises the digital analog converter that digital signal is converted to analog current signal.
12, variable gain amplifier as claimed in claim 6 also comprises being used for importing or the inductor of output impedance coupling and at least one of capacitor.
13, variable gain amplifier as claimed in claim 6, wherein, the transistor of amplifying unit comprises that differential transistor is right.
14, variable gain amplifier as claimed in claim 13, wherein, differential transistor is to comprising nmos pass transistor, the source ground of described nmos pass transistor, grid is connected to bias unit and differential input terminal mouth, thereby gain amplifier changes according to the voltage of being supplied with by bias unit.
15, a kind of variable gain amplifier that changes gain amplifier, described variable gain amplifier comprises:
The cascode amplifier amplifying unit comprises first amplifying unit that is connected to input port and second amplifying unit that is connected to first amplifying unit in the mode of cascode amplifier;
The gain amplifier control unit, output is used to control the control signal of the gain amplifier of cascode amplifier amplifying unit;
Current source cell, output is controlled to and the proportional electric current of gain amplifier according to described control signal;
Bias unit will offer the voltage of first amplifying unit according to the electric current adjustment by current source cell output.
16, variable gain amplifier as claimed in claim 15, wherein, first amplifying unit comprises first nmos pass transistor, the grid of described first nmos pass transistor is connected to input port and bias unit, source ground;
Second amplifying unit comprises second nmos pass transistor, and the source electrode of described second nmos pass transistor is connected to the drain electrode of the nmos pass transistor of first amplifying unit, and grid is connected to bias unit, and drain electrode is connected to service voltage.
17, variable gain amplifier as claimed in claim 15, wherein, bias unit is divided power supply first and second amplifying units of setovering by utilize at least three division resistors that connect between service voltage and earthed voltage.
18, variable gain amplifier as claimed in claim 17, wherein, electric current by current source cell output flows through the division resistor that is connected to first amplifying unit, the voltage that is fed into first amplifying unit is adjusted according to the electric current that flows through this division resistor, to control the gain amplifier of first amplifying unit.
19, variable gain amplifier as claimed in claim 15, wherein, the control signal of being exported by the gain amplifier control unit is a digital signal.
20, variable gain amplifier as claimed in claim 19, wherein, current source cell comprises the digital analog converter that digital signal is converted to analog current signal.
21, variable gain amplifier as claimed in claim 15 also comprises being used for importing or the inductor of output impedance coupling and at least one of capacitor.
22, variable gain amplifier as claimed in claim 15, wherein, each comprises that differential transistor is right first and second amplifying units.
23, variable gain amplifier as claimed in claim 22, wherein, the differential transistor of first amplifying unit is to comprising nmos pass transistor, and the grid of described nmos pass transistor is connected to bias unit and differential input terminal mouth, source ground is to have the structure of common source differential amplifier.
24, variable gain amplifier as claimed in claim 23, wherein, the differential transistor of second amplifying unit is to comprising nmos pass transistor, and the grid of described nmos pass transistor is connected to bias unit, and source electrode is connected to the drain electrode of the nmos pass transistor of first amplifying unit.
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|---|---|---|---|
| KR1020040091913 | 2004-11-11 | ||
| KR1020040091912 | 2004-11-11 | ||
| KR1020040091912A KR100708117B1 (en) | 2004-11-11 | 2004-11-11 | Variable gain amplifier |
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|---|---|---|---|
| CNA2008101823674A Division CN101425786A (en) | 2004-11-11 | 2005-09-16 | Variable gain amplifier |
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| CN1773844A true CN1773844A (en) | 2006-05-17 |
| CN100481713C CN100481713C (en) | 2009-04-22 |
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| CNB2005101033357A Expired - Fee Related CN100481713C (en) | 2004-11-11 | 2005-09-16 | Variable gain amplifier |
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| US10693231B2 (en) | 2017-09-11 | 2020-06-23 | Qualcomm Incorporated | Transmit/receive switching circuit |
| CN107809220A (en) * | 2017-11-30 | 2018-03-16 | 建荣半导体（深圳）有限公司 | Low-noise amplifier, RF IC, signal receiving module and rf chip |
| CN107809220B (en) * | 2017-11-30 | 2024-01-09 | 建荣半导体（深圳）有限公司 | Low noise amplifier, radio frequency integrated circuit, signal receiving module and radio frequency transceiver chip |
| WO2022141198A1 (en) * | 2020-12-30 | 2022-07-07 | 华为技术有限公司 | Operational amplifier, drive circuit, interface chip, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20060044106A (en) | 2006-05-16 |
| CN100481713C (en) | 2009-04-22 |
| CN101425786A (en) | 2009-05-06 |
| KR100708117B1 (en) | 2007-04-16 |
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