CN101202030B - Driving voltage generating circuit - Google Patents
Driving voltage generating circuit Download PDFInfo
- Publication number
- CN101202030B CN101202030B CN2006101672942A CN200610167294A CN101202030B CN 101202030 B CN101202030 B CN 101202030B CN 2006101672942 A CN2006101672942 A CN 2006101672942A CN 200610167294 A CN200610167294 A CN 200610167294A CN 101202030 B CN101202030 B CN 101202030B
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- CN
- China
- Prior art keywords
- current source
- generating circuit
- voltage generating
- transistor
- variable current
- Prior art date
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Abstract
The invention provides a driving voltage generating circuit which comprises a voltage source, a varying source of electric current, a resistor and a unit gain buffer amplifier. The resistor is coupled between the voltage source and the output end of the varying source of the electric current. The input end of the unit gain buffer amplifier is coupled with the output end of the varying source of the electric current. The output end of the unit gain buffer amplifier is the output end of the driving voltage generating circuit and a voltage level thereof is controlled by the varying source of theelectric current, and the varying source of the electric current can be a current mirror device. The driving voltage generating circuit of the invention shortens the number of transmission gates and control signals needing to be used in the circuit.
Description
Technical field
The invention relates to a kind of drive voltage generating circuit, be meant a kind of drive voltage generating circuit that is used for display especially.
Background technology
Fig. 1 is a kind of traditional drive voltage generating circuit 100, comprising be coupled to a voltage source (V with the series connection form
DD) and an earth terminal (V
SS) between a plurality of resistance R, a plurality of transmission gate (T
1, T
2, T
3, T
4, T
5, T
6And T
7) and a unity gain buffer amplifier 102.This conventional ADS driving voltage generation circuit 100 more comprises a control circuit (not showing in the drawings), in order to produce a plurality of control signal (C
1, C
2, C
3, C
4, C
5, C
6And C
7) control above-mentioned transmission gate (T
1, T
2, T
3, T
4, T
5, T
6And T
7).By the different above-mentioned transmission gate (T of conducting
1, T
2, T
3, T
4, T
5, T
6And T
7), the user can change the voltage quasi position of node 104, to determine the output voltage V of this drive voltage generating circuit 100
OutValue.This unity gain buffer amplifier 102 is coupled between the output terminal of this node 104 and this drive voltage generating circuit 100, to avoid this output voltage V
OutAlong with the load drift that is driven.
Conventional ADS driving voltage generation circuit 100 shown in Figure 1 is dividing potential drops of utilizing each connection end point of the described resistance R of connecting, and different voltage quasi positions is provided.As shown in Figure 1, this conventional ADS driving voltage generation circuit 100 must adopt at least eight resistance and seven transmission gate (T
1, T
2, T
3, T
4, T
5, T
6And T
7), can provide seven voltage quasi positions to select for node 104.In addition, this control module must produce seven control signal (C
1, C
2, C
3, C
4, C
5, C
6And C
7) control described transmission gate (T respectively
1, T
2, T
3, T
4, T
5, T
6And T
7).This shows that traditional drive voltage generating circuit must consume a lot of transmission gate and control signal if will produce the accurate position of voltage in several modes.For required transmission gate that uses and control signal number in the reduction circuit, the present invention will disclose a kind of drive voltage generating circuit.
Summary of the invention
The present invention proposes a kind of drive voltage generating circuit, comprising a voltage source, a variable current source, a resistor and a unity gain buffer amplifier.This variable current source is a current mirror arrangement, and comprises a plurality of transmission gates and a control circuit of a reference current source, a first transistor, a plurality of transistor seconds, corresponding described transistor seconds.The grid of this first transistor is coupled in drain electrode.The output terminal of this reference voltage source couples the drain electrode of this first transistor.The drain electrode of described transistor seconds all is coupled to the output terminal of this variable current source.The grid of described transistor seconds is coupled to the grid of above-mentioned the first transistor respectively by pairing described transmission gate.Whether the conducting of described transmission gate, controlled by this control circuit.This control circuit is controlled the size of current that this variable current source is exported by the conducting state of controlling described transmission gate.This resistor is coupled between the output terminal of this voltage source and this variable current source.The input end of this unity gain buffer amplifier couples the output terminal of this variable current source.Wherein, the output terminal of this unity gain buffer amplifier i.e. the output terminal of this drive voltage generating circuit, and its voltage quasi position is by this variable current source control.
The grid source electrode pressure drop of described transistor seconds is all identical with the grid source electrode pressure drop of this first transistor.Described transistor seconds can have different channel width-over-length ratio.
In addition, this variable current source more can comprise one the 3rd transistor, in order to eliminate the raceway groove mudulation effect of described transistor seconds.The 3rd transistor is coupled between the output terminal of described transistor seconds and this variable current source.Wherein, the 3rd transistorized source electrode couples the drain electrode of described transistor seconds, and the 3rd transistor drain is coupled to the output terminal of this variable current source.The 3rd transistorized grid couples a bias voltage.
In addition, drive voltage generating circuit of the present invention can be used for driving a LCD, to adjust the demonstration contrast of this LCD.
Drive voltage generating circuit of the present invention has reduced required transmission gate that uses and control signal number in the circuit.
Description of drawings
Fig. 1 is traditional drive voltage generating circuit;
Fig. 2 is the embodiment of drive voltage generating circuit of the present invention;
Fig. 3 is another embodiment of drive voltage generating circuit of the present invention;
Fig. 4 is another embodiment of drive voltage generating circuit of the present invention.
Embodiment
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphic elaborating.
Fig. 2 is one embodiment of the invention.One drive voltage generating circuit 200 comprises a voltage source V
DD, a variable current source 202, a resistor R and a unity gain buffer amplifier 204.This resistor R is coupled to this voltage source V
DDAnd between the output terminal of this variable current source 202.The input end of this unity gain buffer amplifier 204 couples the output terminal of this variable current source 202.The output terminal of this unity gain buffer amplifier 204 i.e. the output terminal of this drive voltage generating circuit 200, its voltage quasi position V
OutBe by these variable current source 202 controls.As shown in Figure 2, the electric current that produced of this variable current source 202 is I.The voltage of the output terminal of this variable current source 202 is (V
DD-I * R).Therefore, the output end voltage V of this drive voltage generating circuit 200
OutBe (V
DD-I * R).
Above-mentioned variable current source 202 can be a current mirror arrangement.Fig. 3 is another kind of embodiment of the present invention, and the variable current source apparatus 302 that this drive voltage generating circuit 300 is adopted comprises a reference current source I
Ref, a first transistor M
1, a plurality of transistor seconds M
21, M
22With M
23, corresponding described transistor seconds (M
21, M
22With M
23) a plurality of transmission gate T
1, T
2With T
3, an and control circuit (show in the drawings).This first transistor M
1Grid be coupled in drain electrode.This reference current source I
RefOutput terminal couple this first transistor M
1Drain electrode.Described transistor seconds (M
21, M
22With M
23) the pressure drop of grid source electrode all with this first transistor M
1The pressure drop of grid source electrode identical, and described transistor seconds (M
21, M
22With M
23) drain electrode all be coupled to the output terminal (node 304) of this variable current source 302.Described transistor seconds (M
21, M
22With M
23) grid respectively via pairing transmission gate (T
1, T
2With T
3) be coupled to above-mentioned the first transistor M
1Grid.Described transmission gate (T
1, T
2With T
3) conducting whether be the control signal C that exports by this control circuit
1, C
2With C
3Control.The size of the output current I of this variable current source 302 can be along with described transmission gate T
1, T
2With T
3Conducting state and change.These drive voltage generating circuit 300 meetings are because of the difference of the output current I of this variable current source 302, and it presses V and produce different output
Out
With Fig. 3 is example, described transistor seconds M
21, M
22With M
23Can have different channel width-over-length ratio (W/L).Suppose this first transistor M
1With described transistor seconds M
21, M
22With M
23Channel width-over-length ratio (W/L) be 1: 1: 2: 4, and described transistor (M
1, M
21, M
22With M
23) other process parameter all identical.Control signal (C
1, C
2With C
3) when being " 1 ", the transmission gate that representative is controlled is conducting, the transmission gate that " O " representative is controlled is not conducting.Table 1 is described control signal (C
1, C
2With C
3) and the output current I of this variable current source 302 and the output voltage V of this drive voltage generating circuit 300
OutRelation.
Table 1
| C 3 | C 2 | C 1 | I | V out |
| 0 | 0 | 1 | I ref | V DD-I ref×R |
| 0 | 1 | 0 | 2I ref | V DD-2I ref×R |
| 0 | 1 | 1 | 3I ref | V DD-3I ref×R |
| 1 | 0 | 0 | 4I ref | V DD-4I ref×R |
| 1 | 0 | 1 | 5I ref | V DD-5I ref×R |
| 1 | 1 | 0 | 6I ref | V DD-6I ref×R |
| 1 | 1 | 1 | 7I ref | V DD-7I ref×R |
As shown in Table 1, this drive voltage generating circuit 300 also can provide seven kinds of different output voltage V
OutCompared to the conventional ADS driving voltage generation circuit 100 of Fig. 1, drive voltage generating circuit 300 of the present invention only needs three transmission gate (T
1, T
2, and T
3) and three control signal (C
1, C
2With C
3), seven kinds of different output voltage V can be provided
Out
Fig. 4 is another embodiment of the present invention.Compare with Fig. 3, the variable current source 402 of drive voltage generating circuit 400 more comprises one the 3rd transistor M
3The 3rd transistor M
3Be to be used for eliminating described transistor seconds (M
21, M
22With M
23) channel length modulation effect (channel length modulation).The 3rd transistor M
3Source electrode couple described transistor seconds (M
21, M
22With M
23) drain electrode, and the 3rd transistor M
3Drain electrode be coupled to the output terminal (node 404) of this variable current source.The 3rd transistor M
3Grid by a bias voltage V
BiasBias voltage.
Drive voltage generating circuit of the present invention can be used for driving a LCD, to adjust the demonstration contrast of this LCD.With Fig. 3 is example, and this drive voltage generating circuit 300 can provide seven kinds of different output voltage V
OutLiquid crystal display is selected to use, and makes this LCD that seven kinds of different demonstration contrasts can be arranged.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
100: the conventional ADS driving voltage generation circuit
102: the unit gain buffer amplifier
104: node
200: drive voltage generating circuit
202: variable current source
204,306,406: the unity gain buffer amplifier
300: drive voltage generating circuit
302: variable current source
304: the output terminal of variable current source 302
400: drive voltage generating circuit
402: variable current source
404: the output terminal of variable current source 402
C
1, C
2, C
3, C
4, C
5, C
6, C
7: control signal
I: the output current of variable current source
I
Ref: reference current source
M
1: the first transistor
M
21, M
22With M
23: transistor seconds
M
3: the 3rd transistor
R: resistor
T
1, T
2, T
3, T
4, T
5, T
6, T
7: transmission gate
V
Bias: bias voltage
V
DD: voltage source
V
Out: the output voltage of drive voltage generating circuit
V
SS: earth terminal
Claims (5)
1. a drive voltage generating circuit is characterized in that, this drive voltage generating circuit comprises:
One voltage source;
One variable current source, this variable current source is a current mirror arrangement, and comprises: a reference current source; One the first transistor, its grid is coupled in drain electrode, and its drain electrode couples the output terminal of this reference current source; A plurality of transistor secondses, its drain electrode all is coupled to the output terminal of this variable current source; A plurality of transmission gates of corresponding above-mentioned transistor seconds are coupled to the grid of pairing above-mentioned transistor seconds the grid of above-mentioned the first transistor respectively; And a control circuit, be conducting or not conducting in order to control described transmission gate, to control the size of current that this variable current source is exported;
One resistor is coupled between the output terminal of this voltage source and this variable current source; And
One unity gain buffer amplifier, its input end couples the output terminal of this variable current source;
Wherein, the output terminal of this unity gain buffer amplifier i.e. the output terminal of this drive voltage generating circuit, and its voltage quasi position is by this variable current source control.
2. drive voltage generating circuit according to claim 1, it is characterized in that, this variable current source more comprises one the 3rd transistor, in order to eliminate the raceway groove mudulation effect of described transistor seconds, wherein, the 3rd transistorized source electrode couples the drain electrode of described transistor seconds, and the 3rd transistor drain is coupled to the output terminal of this variable current source, and the 3rd transistorized grid couples a bias voltage.
3. drive voltage generating circuit according to claim 1 is characterized in that described transistor seconds has different channel width-over-length ratio.
4. drive voltage generating circuit according to claim 1 is characterized in that, can be used for driving a LCD, to adjust the demonstration contrast of this LCD.
5. drive voltage generating circuit according to claim 1 is characterized in that, the grid source electrode pressure drop of these a plurality of transistor secondses is all identical with the grid source electrode pressure drop of this first transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101672942A CN101202030B (en) | 2006-12-15 | 2006-12-15 | Driving voltage generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101672942A CN101202030B (en) | 2006-12-15 | 2006-12-15 | Driving voltage generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101202030A CN101202030A (en) | 2008-06-18 |
| CN101202030B true CN101202030B (en) | 2010-12-08 |
Family
ID=39517165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101672942A Expired - Fee Related CN101202030B (en) | 2006-12-15 | 2006-12-15 | Driving voltage generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101202030B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134991B (en) * | 2012-12-31 | 2021-03-05 | 意法半导体研发(深圳)有限公司 | Drive circuit for driving power transistor |
| US10026574B2 (en) | 2013-03-18 | 2018-07-17 | Infineon Technologies Ag | Multi-load drive circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1368792A (en) * | 2001-02-10 | 2002-09-11 | 深圳赛意法微电子有限公司 | Current amplifier structure |
| CN1420625A (en) * | 2001-11-16 | 2003-05-28 | 松下电器产业株式会社 | Variable gain amplifier and filter circuit |
| CN1604209A (en) * | 2003-10-01 | 2005-04-06 | 三星电机株式会社 | Current to voltage conversion circuit for photo detector integrated circuit employing gain switching circuit |
| CN1773844A (en) * | 2004-11-11 | 2006-05-17 | 三星电子株式会社 | Variable gain amplifier |
-
2006
- 2006-12-15 CN CN2006101672942A patent/CN101202030B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1368792A (en) * | 2001-02-10 | 2002-09-11 | 深圳赛意法微电子有限公司 | Current amplifier structure |
| CN1420625A (en) * | 2001-11-16 | 2003-05-28 | 松下电器产业株式会社 | Variable gain amplifier and filter circuit |
| CN1604209A (en) * | 2003-10-01 | 2005-04-06 | 三星电机株式会社 | Current to voltage conversion circuit for photo detector integrated circuit employing gain switching circuit |
| CN1773844A (en) * | 2004-11-11 | 2006-05-17 | 三星电子株式会社 | Variable gain amplifier |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2006-310915A 2006.11.09 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101202030A (en) | 2008-06-18 |
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Granted publication date: 20101208 Termination date: 20151215 |
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| EXPY | Termination of patent right or utility model |