CN101997489A - Amplifier and implementation method thereof - Google Patents

Abstract

The invention discloses an amplifier and an implementation method thereof so as to implement a low-noise amplifier with continuous gain-adjustable function under ultra wide band width. The provided amplifier comprises an input matching circuit unit, a gain-adjusted amplifying circuit unit and an output matching circuit unit, wherein the input matching circuit unit is used for matching input impedance and matching noises and outputting an input signal of the amplifier to the gain-adjustable amplifying circuit unit; the gain-adjustable amplifying circuit unit is used for performing amplification processing on the input signal, outputting the processed signal to the output matching circuit unit, receiving the input control voltage and adjusting the gain of the amplifier according to the control voltage; and the output matching circuit unit is used for matching output impedance and outputting the signal processed by the gain-adjusted amplifying circuit unit.

Description

A kind of amplifier and its implementation

Technical field

The present invention relates to wireless communication technology field, relate in particular to a kind of amplifier and its implementation.

Background technology

In recent years, radio communication is one of current technology with fastest developing speed.The general trend of wireless communication technology is high speed, big bandwidth.And following short distance radio communication system to realize " anyone; " connectivity any time; any place, just require now comprehensive and future broadband wireless communication systems, comprise wide area network (WANs), wireless lan (wlan), Wireless Personal Network (WPAN), wireless body area network (WBAN), mobile ad hoc network (ad-hoc) and home network etc.Various equipment be can connect, computer and various amusement equipment comprised.In various wireless communication technologys, comprise IEEE 802.11, IEEE 802.15, bluetooth (Bluetooth), home radio (Home RF) etc., emerging ultra broadband (UWB) wireless communication technology becomes the one preferred technique that realizes WPAN.

UWB is a kind of carrierfree communication technology, utilize the non-sinusoidal waveform burst pulse transmission data of nanosecond, so its spectral range that takies is very wide, it is generally acknowledged that-10 gain (dB) relative bandwidths surpass 25% to the picosecond level, perhaps-the 10dB absolute bandwidth surpasses 500MHz, just is called ultra broadband.

The UWB technology starts from the pulse communication technology of rising the sixties in 20th century, utilizes the extremely wide ultrashort pulse of frequency spectrum to communicate, and is mainly used in military radar, location and the communication system.FCC (FCC) proves repeatedly to this new technology, think radio ultra wide band system can be between 3.1GHz～10.6GHz with limited power operation, and in official approval on February 14 in 2002 the UWB technology is applied to the proposal of commercial communication.Ultra broadband is different from other some existing communication technologys, its the most basic difference is need not carrier wave, can directly launch the impulse sequence, thereby have very wide frequency spectrum and a very low average power, help coexisting with other system, improve the availability of frequency spectrum, greatly reduce the complexity of transmitting and receiving apparatus.The advantage of UWB can reduce following eight aspect: (1) need not carrier wave; (2) low in energy consumption; (3) transmission rate height; (4) good concealment, safe; (5) multi-path resolved ability is strong; (6) power system capacity is big; (7) high-precision range resolution; (8) penetration capacity is strong.Therefore, super-broadband tech will have a wide range of applications in high speed wireless personal network (HDR-WPAN), wireless ethernet interface link (WEIL), smart antenna regional network (IWAN), outdoor point to point network (OPPN), transducer, location and recognition network (SPIN) field.

In the ultra wideband receiver system, low noise amplifier (low noise amplifier is called for short LNA) is one of most important module of receiving front-end.It is in the first order behind antenna and the radio-frequency filter, must now the load characteristic of 50 ohm (Ω) to the radio frequency filter table, to guarantee maximum power delivery, its noise characteristic will directly influence the noiseproof feature of whole system, and then the sensitivity and the dynamic duty scope of decision receiver.Compare with base amplifier, low noise amplifier can reduce the noise jamming of system, the sensitivity that improves system on the one hand; Signal that on the other hand can amplification system guarantees the normal operation of system works.The performance of low noise amplifier has not only restricted the performance of whole receiving system, and, for the raising of whole receiving system technical merit, also played conclusive effect.Therefore, develop suitable high-performance, more low noise amplifier, become one of core content in the radio ultra wide band system design.

The research of low noise amplifier is own through comparative maturity, UWB LNA is accompanied by particularly improving of CMOS technology and obtain development at full speed of semiconductor technology, present difficult point and focus are how to adapt to development of wireless communication devices, especially how to adapt to the requirement of super-broadband tech and 3G technology, improve noiseproof feature, the linearity and the bandwidth of low noise amplifier, further reduce voltage and power consumption, realize that monolithic is integrated; Because UWB system broad market prospect, therefore designing high performance ultra broadband LNA is of great value research.

In ultra wideband receiver, ultra-wideband low-noise amplifier must be to next stage circuit (frequency mixer) output appropriate signals.Signal gets too small, frequency mixer can't detect; Signal is excessive, can cause overload to frequency mixer again, and the linearity is worsened.And the signal that LNA receives from antenna is at times strong and at other times weak, and this just requires the controllable gain of LNA.Secondly, have the Gain Adjustable function, can make the difference compromise of various parameters, can be suitable for the multiple needs in the practical application, have greater flexibility.Once more, gain and power consumption have certain relation, and the low noise amplifier with Gain Adjustable function can reduce power consumption well.The Gain Adjustable low noise amplifier of arrowband exists at present, but does not also realize the low noise amplifier with continuous Gain Adjustable function under the ultra broadband bandwidth at present.

Existing Gain Adjustable technology has following four kinds:

1. (Switched Gain) selected in bypass:

The mode that bypass is selected is a kind of discrete gain controlling, generally is by a high gain mode and a low gain mode, is suitable for arrowband and broadband.This method can realize the Gain Adjustable of wide region by the break-make of control end, but shortcoming is to realize continuous gain controlling.

2. feed back (Feedback Techniques):

Adopt the gain of the low noise amplifier of feedback arrangement to follow feedback impedance relevant, so can realize Gain Adjustable by regulating feedback impedance.

The advantage of this method is to realize continuous change in gain; Shortcoming is only to be applied in the arrowband at present, if be applied in the ultra broadband, gain flatness can worsen in the band when change in gain, and excursion is smaller, and noise factor is not good especially, and power consumption can increase during change in gain.

3. current separation (Current Splitting):

The gilbert who adopts on the current separation technical spirit is (Gilbert) structure (a kind of circuit structure), when control voltage VC changes from small to large, at the field effect transistor of being controlled (CMOS, ComplementaryMetal Oxide Semiconductor) (complementary metal oxide semiconductors (CMOS), voltage-controlled a kind of amplifying device).Do not have before the unlatching, be equivalent to open circuit, gaining is maximum, VC continues to increase after opening, and the drain current of this CMOS pipe of flowing through can slowly increase, but the output current sum of this electric current and amplifier is constant, so output current can diminish, gain can reduce gradually, so claim the current separation technology again.

The advantage of this method is to realize continuous change in gain, and power consumption is constant; Shortcoming is only to be applied in the arrowband at present, if be applied in the ultra broadband, compare when change in gain in the band gain flatness with feedback technique and can worsen more seriously, and excursion is smaller.

4. distributed amplifier:

Distributed amplifier (Distributed Amplifiers) has superior wide band frequency characteristics, also has good input and output impedance matching property in addition.But distributed amplifier has adopted a plurality of amplifiers, and its circuit structure complexity makes chip area very big, and power consumption is higher, does not meet present circuit low-power consumption low-voltage trend.

5. change biasing:

The method that changes biasing comes down to control the input pipe mutual conductance, or the mutual conductance of control amplifier tube, though the realization easily of this method can influence input coupling and gain flatness, and be difficult to accurate control.

In sum, prior art can't realize the low noise amplifier with continuous Gain Adjustable function under the ultra broadband bandwidth.

Summary of the invention

The embodiment of the invention provides a kind of amplifier and its implementation, in order to realize the low noise amplifier with continuous Gain Adjustable function under the ultra broadband bandwidth.

A kind of amplifier that the embodiment of the invention provides comprises:

The input matching circuit unit is used to realize input impedance matching and noise coupling; And the input signal of described amplifier exported to the Gain Adjustable amplifier circuit unit;

The Gain Adjustable amplifier circuit unit be used for described input signal is carried out processing and amplifying, and the signal that will obtain after will handling is exported to the output matching circuit unit; And the control voltage that receives input, and, adjust described Amplifier Gain by described control voltage;

The output matching circuit unit is used to realize the output impedance coupling; And, the signal output that will obtain after will handling through described Gain Adjustable amplifier circuit unit.

The implementation method of a kind of amplifier that the embodiment of the invention provides comprises:

Realize input impedance matching and noise coupling by the input matching circuit unit;

By the Gain Adjustable amplifier circuit unit input signal is carried out processing and amplifying, and the control voltage that utilizes input, described Amplifier Gain adjusted;

Realize the output impedance coupling by the output matching circuit unit, and the signal output that will obtain after will handling through described Gain Adjustable amplifier circuit unit.

In the embodiment of the invention, the input matching circuit unit is used to realize input impedance matching and noise coupling; And the input signal of described amplifier exported to the Gain Adjustable amplifier circuit unit; The Gain Adjustable amplifier circuit unit be used for described input signal is carried out processing and amplifying, and the signal that will obtain after will handling is exported to the output matching circuit unit; And input control voltage, and, adjust described Amplifier Gain by described control voltage; The output matching circuit unit is used to realize the output impedance coupling; And, the signal output that will obtain after will handling through described Gain Adjustable amplifier circuit unit.Thereby realized having the continuously adjustable low noise amplifier that is applied to ultra broadband of gain.

Description of drawings

The electrical block diagram of the amplifier that Fig. 1 provides for the embodiment of the invention;

The CMOS that Fig. 2 A provides for the embodiment of the invention manages the noise source schematic diagram of M1;

The CMOS that Fig. 2 B provides for the embodiment of the invention manages the noise equivalent circuit schematic diagram of M1;

N channel metal-oxide-semiconductor that Fig. 3 provides for the embodiment of the invention (NMOS, N-Mental-Oxide-Semiconductor) basic current mirror intention;

The simulation result schematic diagram of the circuit that Fig. 4 provides for the embodiment of the invention;

The simulation result schematic diagram of the circuit that Fig. 5 provides for the embodiment of the invention;

The simulation result schematic diagram of the circuit that Fig. 6 provides for the embodiment of the invention;

The simulation result schematic diagram of the circuit that Fig. 7 provides for the embodiment of the invention;

The simulation result schematic diagram of the circuit that Fig. 8 provides for the embodiment of the invention;

The simulation result schematic diagram of the circuit that Fig. 9 provides for the embodiment of the invention;

The simulation result schematic diagram of the circuit that Figure 10 provides for the embodiment of the invention;

Figure 11 is the embodiment of the invention and the performance comparison schematic diagram that has various low noise amplifiers now;

The implementation method schematic flow sheet of a kind of amplifier that Figure 12 provides for the embodiment of the invention.

Embodiment

The embodiment of the invention provides a kind of low noise amplifier and its implementation, in order to realize the low noise amplifier with continuous Gain Adjustable function under the ultra broadband bandwidth.

The described ultra broadband bandwidth of the embodiment of the invention is meant the bandwidth of 3GHz～5GHz scope.

The embodiment of the invention relates to field effect transistor (CMOS, Complementary Metal OxideSemiconductor) field of radio frequency integrated circuits, be the continuously adjustable CMOS ultra-wideband low-noise amplifier of gain that has of realizing a kind of 3GHz of being operated in～5GHz specifically, this amplifier circuit adopts the cascode amplifier structure at the two poles of the earth, adopt the second order Chebyshev filter as input, source follower has obtained good input and output coupling and noiseproof feature as output in band.Bias current by control second level amplifying circuit has obtained the continuous Gain Adjustable of 36dB, and does not influence the input and output coupling.

In order to realize the continuous Gain Adjustable of ultra-wideband low-noise amplifier, and input and output coupling, and the function that do not worsen of gain flatness, the circuit that the embodiment of the invention provides has been avoided the deficiency of existing Gain Adjustable technology, promptly in the first generation radio ultra wide band system of LNA working band, in the change in gain process, do not influence the input and output coupling at 3GHz～5GHz, gain flatness does not worsen yet, and various aspects of performance is also far better than other ultra-wideband low-noise amplifiers.

The circuit of the low noise amplifier that the embodiment of the invention provides totally comprises four parts as shown in Figure 1:

Input matching unit: adopt the second order Chebyshev filter, can reach good reflection coefficient and noise factor.

Amplifier circuit unit: adopt the two-stage cascodes.

First order amplifying circuit mainly is in order to realize good input coupling, to suppress Miller (Miller) effect, realizing higher reverse isolation degree and better noiseproof feature.

Second level amplifying circuit, be gain control circuit, control the gain of entire circuit by the partial bias current of control circuit (second level amplifying circuit is operated in the drain current under the magnifying state), and in change in gain, keep good gain flatness and reverse isolation degree, do not influence the input and output coupling simultaneously.

The output matching unit: output buffer, adopt the load of source class follower (a kind of amplifying circuit) coupling 50 Ω.

The biasing circuit unit: employing be current mirror.

Referring to Fig. 1, provide the concrete unit of circuit shown in this figure and the explanation of calculating simulation result below.

One, concrete unit

1, input matching circuit unit is used to realize input impedance matching and noise coupling; And the input signal of amplifier exported to first order amplifier circuit unit in the Gain Adjustable amplifier circuit unit.

The input matching circuit unit links to each other with first order amplifier circuit unit by field effect transistor M1.

In ultra broadband LNA design, utilize inductance capacitance (LC) ladder network can in very wide bandwidth, obtain good power and noise coupling as input.

The embodiment of the invention adopts the second order Chebyshev filter as the input matching circuit unit, than three rank Chebyshev filters, can reach more excellent noiseproof feature, and reduce chip area.

The input impedance of circuit shown in Figure 1 is:

$Z_{\mathrm{in}}=L_{g}s//\frac{1}{C_{\mathrm{gd}}s}+L_{s}s+\frac{1}{(C_p+C_{\mathrm{gs}})s}+{\mathrm{\ω}}_T{L}_s$

Wherein, L _gThe grid inductance of expression CMOS pipe M1; S is the complex variable C in the Laplace transform _GdThe gate leakage capacitance of expression CMOS pipe M1; L _sThe source inductance of expression CMOS pipe M1; C _GsThe grid source electric capacity of expression CMOS pipe M1; ω _TThe cut-off frequency of expression CMOS pipe M1.

And, ω _T=g _m/ (C _Gs+ C _p)=g _m/ C _t, wherein, g _mThe mutual conductance of expression CMOS pipe M1; C _t=C _Gs+ C _p

Z _InReal part ω _TL _s=R _s=50 Ω, but because the gate leakage capacitance C of CMOS pipe M1 _GdExistence, therefore in the design ultra-wideband low-noise amplifier, make real part compare ω _TL _sLittle, so the source inductance L of CMOS pipe M1 _sBe a bit larger tham R _s/ ω _T, Z _InResonance by L _gAnd C _Gd+ C _t/ (1-ω ²L _sC _t) decision, wherein ω represents frequency, so L _gBe arranged to compare L ₁-L _sBig, C _tCompare C ₁-C _GdPoint.So just be easy to utilize Chebyshev filter in 3GHz～5GHz frequency band, to realize the input impedance of approximate 50 Ω.

2, Gain Adjustable amplifier circuit unit be used for input signal is carried out processing and amplifying, and the signal that will obtain after will handling is exported to the output matching circuit unit; And input control voltage, and, adjust described Amplifier Gain by control voltage.

Preferably, described Gain Adjustable amplifier circuit unit comprises:

First order amplifier circuit unit be used for input signal is carried out processing and amplifying, and the signal that will obtain after will handling is exported to second level amplifier circuit unit.

Second level amplifier circuit unit be used for the signal of first order amplifier circuit unit output is carried out processing and amplifying, and the signal that will obtain after will handling is exported to the output matching circuit unit; And input control voltage, and, adjust the gain of whole amplifier by control voltage.

First order amplifying circuit comprises field effect transistor M1 and M2, inductance L _d, resistance R _d, capacitor C ₂

Inductance L _dWith resistance R _dLink to each other resistance R _dLink to each other with the leakage level of field effect transistor M2, the supply power voltage of amplifier shown in Figure 1 is from inductance L _dInput, capacitor C ₂An end and leakage level and the resistance R of field effect transistor M2 _dLink to each other capacitor C ₂The other end link to each other with second level amplifier circuit unit.

After first order amplifying circuit carries out processing and amplifying to input signal, the signal that obtains after handling is passed through capacitor C ₂Export to second level amplifier circuit unit.

Second level amplifying circuit comprises field effect transistor M3 and M4, inductance L _L, resistance R _L

Field effect transistor M3 links to each other with field effect transistor M4, and the signal of first order amplifying circuit output is from the grid input of field effect transistor M3, and control voltage is from the grid input of field effect transistor M4, leakage level and the resistance R of field effect transistor M4 _LLink to each other; Inductance L _LWith resistance R _LLink to each other, the supply power voltage of amplifier shown in Figure 1 is from inductance L _LInput.

From circuit structure diagram shown in Figure 1 as can be seen, first order amplifier circuit unit and second level amplifier circuit unit all adopt two-stage cascade source inductance negative feedback structure, be in order to suppress the Miller effect and to obtain lower noise factor, and realize Gain Adjustable but do not influence the input and output coupling.

The input matching circuit unit is Chebyshev (Chebyshev) filter, and its impedance is R _s/ W (s), i.e. Z _In, wherein W (s) is the transfer function (known) of input matching circuit unit.If input signal is V _In, the signal code that then enters CMOS pipe M1 is:

i _in＝V _in·W(S)/R _s

When high frequency, the CMOS pipe shows as a current amplifier, and the current amplification factor of first order amplifier circuit unit and second level amplifier circuit unit is respectively: β ₁(s)=g _M1/ sC _tAnd β ₂(s)=g _M3/ sC _Gs3, g wherein _MlThe mutual conductance of expression CMOS pipe M1; g _M3The mutual conductance of expression CMOS pipe M3; S represents the complex variable in the Laplace transform; C _t=C _Gs+ C _pC _GsBe the grid source electric capacity of CMOS pipe M1; C _Gs3Be the grid source electric capacity of CMOS pipe M3; So the output current of CMOS pipe M1 is:

$i_{\mathrm{out}}=i_{\mathrm{in}}\·{\mathrm{\β}}_1\left(s\right)\·{\mathrm{\β}}_2\left(s\right)=\frac{V_{\mathrm{in}}\·W\left(s\right)g_{m1}{g}_{m3}}{s^2{C}_t{C}_{\mathrm{gs}3}{R}_s}$

And the output impedance of circuit shown in Figure 1 is:

R _out＝(L _L+R _L)//C _out

So the voltage signal of output is:

$V_{\mathrm{out}}=i_{\mathrm{out}}\·R_{\mathrm{out}}=\frac{V_{\mathrm{in}}\·W\left(s\right)g_{m1}{g}_{m3}}{s^2{C}_t{C}_{\mathrm{gs}3}{R}_s}{R}_{\mathrm{out}}$

The gain of entire circuit shown in Figure 1 is:

$\frac{V_{\mathrm{out}}}{V_{\mathrm{in}}}=\frac{W\left(s\right)g_{m1}{g}_{m3}}{s^2{C}_t{C}_{\mathrm{gs}3}{R}_s}\·R_{\mathrm{out}}$

$=\frac{W\left(s\right)g_{m1}{g}_{m3}}{s^2{C}_t{C}_{\mathrm{gs}3}{R}_s}\·[(L_L+R_L)//C_{\mathrm{out}}]$

$=\frac{W\left(s\right)g_{m1}{g}_{m3}}{s^2{C}_t{C}_{\mathrm{gs}3}{R}_s}\·\frac{R_L(1+s{L}_L/R_L)}{1+{\mathrm{sR}}_L{C}_{\mathrm{out}}+s^2{L}_L{C}_{\mathrm{out}}}$

Above various in, R _LAnd L _LBe respectively load resistance and load inductance, output capacitance is C _Out=C _Db4+ C _Gd5, wherein, C _Db4Be the capacitance to substrate (capacitance to substrate is meant a kind of parasitic capacitance in CMOS technology) of CMOS pipe M4, C _Db5It is the gate leakage capacitance of CMOS pipe M5.

Following formula shows that the gain of entire circuit (being whole low noise amplifier) is with the mutual conductance g of CMOS pipe M3 _M3Proportional.

Yet, for CMOS pipe M3, have:

${\mathrm{<figure-callout\; id="3"\; label="g\; m"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">g</figure-callout>}}_m=\sqrt{{2K}^{\&prime;}W/L\left|I_D\right|(1+{\mathrm{\&lambda;V}}_{\mathrm{ds}3})}$

$I_D=K^{\&prime;}\frac{W}{2L}{(V_{\mathrm{gs}3}-V_T)}^2(1+{\mathrm{\&lambda;V}}_{\mathrm{ds}3})$

K ' expression transconductance parameters in the formula, W are represented the grid width of CMOS pipe M3 and M4, and L represents the channel length of CMOS pipe M3 and M4, I _DThe leakage level bias current of expression second level amplifying circuit, λ is the channel length modulation parameter, V _Ds3And V _Gs3Drain-source voltage and the gate source voltage of representing CMOS pipe M3 respectively.In fact, can manage the load that M4 regards CMOS pipe M3 as to CMOS, corresponding load impedance is made as Z _Ds4, as grid voltage (promptly the controlling voltage) V of CMOS pipe M3 _CDuring increase, Z _Ds4Reduce, so I _DCan increase, from top two formulas as can be seen, V _Ds3Also increase, thus g _M3Also along with increase.In sum, changed V _CValue just equal to have changed the gain of entire circuit, thereby realize the function of Gain Adjustable.

The general expression formula of the noise factor that classical noise theory provides is:

F＝F _min+G _n/R _s|Z _s-Z _opt| ²

Wherein, F _MinBe device noise, G _n/ R _s| Z _s-Z _Opt| ²Be because the loss of the input circuit that the low-quality factor of integrated inductor causes.If can reach the inductance of good input coupling and enough high quality factor (Q) values, G _n/ R _s| Z _s-Z _Opt| ²Can minimize.Therefore, in embodiment of the invention circuit shown in Figure 1, noiseproof feature is determined by two aspects: the noise that the loss of input matching circuit unit and CMOS pipe M1 cause.

The optimization of the noise that CMOS pipe M1 is caused, be exactly under certain power consumption condition to the selection of the grid width of CMOS pipe M1.Make a concrete analysis of as follows:

The noise model of CMOS pipe M1 comprises two noise sources as shown in Figure 2, and one is the thermal noise of channel current, and one is grid noise, uses i respectively _NdAnd i _NgExpression.

Fig. 2 A is determined by following two formulas to the equivalence of Fig. 2 B:

$i_n=i_{\mathrm{ng}}+\frac{\mathrm{j\&omega;}{C}_t}{g_m}{i}_{\mathrm{nd}}$

$e_n=\mathrm{j\&omega;}{L}_s{i}_{\mathrm{ng}}+(1-{\mathrm{\&omega;}}^2{C}_t{L}_s)\frac{i_{\mathrm{nd}}}{g_m}=\frac{i_{\mathrm{nd}}}{g_m}+{\mathrm{j\&omega;L}}_s{i}_n$

Wherein, i _nThe expression equivalent noise current; e _nThe expression noise equivalent voltage; g _mThe mutual conductance of expression CMOS pipe M1; i _NdThe drain electrode noise current of expression CMOS pipe M1, i _NgThe grid noise electric current of expression CMOS pipe M1.

i _NgPower spectral density be:

$S_{i_{\mathrm{ng}}}\left(\mathrm{\&omega;}\right)=4\mathrm{kT\&delta;}\frac{{\mathrm{\&omega;}}^2{{\mathrm{<figure-callout\; id="2"\; label="C\; gs"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}}^2}{{5g}_{d0}}$

Wherein, k represents Boltzmann constant; T represents temperature; C _GsThe grid source electric capacity of expression CMOS pipe M1; g _D0Expression V _DS=0 o'clock channel conduction.

i _NdPower spectral density be:

$S_{i_{\mathrm{nd}}}\left(\mathrm{\&omega;}\right)=4\mathrm{kT\&gamma;}{g}_{d0}$

Wherein, δ is about 1.33～4, and γ is about 0.67～1.33, is additional noise parameter, g _D0Be V _DS=0 o'clock channel conduction, V _DSThe drain-source voltage of expression CMOS pipe M1.

Through complicated calculating, the impedance Z that the equivalent noise model is relevant _CFor:

$Z_C=\frac{S_{e_n{i}_n}\left(\mathrm{\&omega;}\right)}{S_{i_n}\left(\mathrm{\&omega;}\right)}=\frac{1}{{\mathrm{j\&omega;C}}_t\&CenterDot;\frac{1+2\left|c\right|\mathrm{p\&alpha;\&chi;}+{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">p</figure-callout>}}^2{\mathrm{\&alpha;}}^2{\mathrm{\&chi;}}^2}{1+\left|c\right|\mathrm{p\&alpha;\&chi;}}}+\mathrm{j\&omega;}{L}_s$

Wherein,

Expression e _ni _nThe related power spectrum density;

Expression i _nPower spectral density; P=C _Gs/ C _t,

α=g _m/ g _D0, Be the coefficient correlation of raceway groove noise and grid noise,

Expression i _Ngi _NdThe related power spectrum density, for the CMOS pipe, c is approximately j0.4, and wherein, j is the coefficient correlation of grid induced noise and raceway groove noise.

Two incoherent noise source i _nAnd e _n, can lead description with following equivalent noise resistance and electricity:

$R_u=\frac{S_{e_n}\left(\mathrm{\&omega;}\right)}{4\mathrm{kT}}=\frac{\mathrm{\&gamma;}}{{\mathrm{\&alpha;}}^2{g}_{d0}}\&CenterDot;\frac{{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">p</figure-callout>}}^2{\mathrm{\&alpha;}}^2{\mathrm{\&chi;}}^2(1+{\left|c\right|}^2)}{1+2\left|c\right|\mathrm{p\&alpha;\&chi;}+{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">p</figure-callout>}}^2{\mathrm{\&alpha;}}^2{\mathrm{\&chi;}}^2}$

$G_u=\frac{S_{i_n}\left(\mathrm{\&omega;}\right)}{4\mathrm{kT}}=\frac{\mathrm{\&gamma;}}{{\mathrm{\&alpha;}}^2{G}_{d0}}\&CenterDot;{\mathrm{\&omega;}}^2{C}_t^2(1+2|c|\mathrm{p\&alpha;\&chi;}+{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">p</figure-callout>}}^2{\mathrm{\&alpha;}}^2{\mathrm{\&chi;}}^2)$

Wherein, R _uThe expression equivalent noise resistance,

Expression e _nPower spectral density, G _uThe expression equivalent noise conductance.

Noise factor can be expressed as:

$F=1+\frac{R_u+|Z_c+Z_s|G_u}{R_s}$

Wherein, Z _s=R _s+ jX _s, expression source impedance, X _sThe imaginary part of expression Zs.By the noise optimization theory of classics as can be known, if Z _Opt=Z _s=R _Opt+ jX _Opt, it is minimum that noise factor will reach.The optimization impedance is determined by following formula:

$R_{\mathrm{opt}}=\sqrt{\frac{R_u}{G_u}+{\mathrm{<figure-callout\; id="2"\; label="R\; c"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">R</figure-callout>}}_c^{}}=\sqrt{\frac{R_u}{G_u}}=\frac{\mathrm{p\&alpha;\&chi;}(1-{\left|c\right|}^2)}{{\mathrm{\&omega;C}}_t(1+2|c|\mathrm{p\&alpha;\&chi;}+{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">p</figure-callout>}}^2{\mathrm{\&alpha;}}^2{\mathrm{\&chi;}}^2)}$

Wherein, X _Opt=-X _c, X _cExpression Z _CImaginary part, R _c=0.

This shows, reach minimum noise factor, need a suitable fan-in network in the whole bandwidth of amplifier, to realize X _Opt, the expression formula of the noise factor of low noise amplifier is:

$F\left(\mathrm{\&omega;}\right)\&ap;1+\frac{R_u}{R_s}+G_n{R}_s\&ap;1+\frac{P\left(\mathrm{\&omega;}\right)}{g_m{R}_s}\&CenterDot;\frac{\mathrm{\&gamma;}}{\mathrm{\&alpha;}}$

Wherein, P (ω) is a dc power, with the drain bias electric current I _DBe directly proportional, expression formula is:

$P\left(\mathrm{\&omega;}\right)=\frac{{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">p</figure-callout>}}^2{\mathrm{\&alpha;}}^2{\mathrm{\&chi;}}^2(1-{\left|c\right|}^2)}{1+2\left|c\right|\mathrm{p\&alpha;\&chi;}+{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">p</figure-callout>}}^2{\mathrm{\&alpha;}}^2{\mathrm{\&chi;}}^2}+{\mathrm{\&omega;}}^2{C}_t^2{R}_s^2(1+2|c|\mathrm{p\&alpha;\&chi;}+{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">p</figure-callout>}}^2{\mathrm{\&alpha;}}^2{\mathrm{\&chi;}}^2)$

Wherein, γ is a raceway groove thermal noise coefficient, and α is a constant, g _mBe the mutual conductance of CMOS pipe M1, g _m=ω _T(C _Gsl+ C _p), C _Gsl=2WLC _Ox/ 3, C wherein _OxThe grid capacitance of representation unit area.Therefore, from the noise factor expression formula as can be known, noise factor depends on the drain bias electric current I of CMOS pipe M1 _D, overdrive voltage Vod, CMOS the pipe M1 grid width W and frequencies omega.

Utilizing software for calculation can depict under certain power consumption (is certain I _DThe average noise factor NF of each grid width down).The grid width of CMOS pipe M1 can obtain the optimization of noise under certain power consumption is selected, in the embodiment of the invention, and I _D=3.39 milliamperes (mA), the grid width W=240 micron (μ m) of selection CMOS pipe M1 is to obtain best noiseproof feature.Certainly, the drain bias electric current I of CMOS pipe M1 _D, overdrive voltage Vod and CMOS pipe M1 grid width W can also get other values, the just value of the best that exemplifies herein.

3, output matching circuit unit is used to realize the output impedance coupling; And, the signal output that will obtain after will handling through the Gain Adjustable amplifier circuit unit.

Form the source class follower by CMOS pipe M5 and M6, as the output buffering, be used for reaching the output coupling of 50 Ω, output impedance is:

$Z_{\mathrm{out}}\left(\mathrm{\&omega;}\right)=\frac{1+\mathrm{j\&omega;}{Z}^{\&prime;}\left(\mathrm{\&omega;}\right)C_{\mathrm{gs}5}}{{\mathrm{<figure-callout\; id="5"\; label="g\; m"\; filenames="HDA0000028554480000051.png,HDA0000028554480000071.png"\; state="\{\{state\}\}">g</figure-callout>}}_m+{\mathrm{j\&omega;<figure-callout\; id="5"\; label="C\; gs"\; filenames="HDA0000028554480000051.png,HDA0000028554480000071.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}}//{\mathrm{<figure-callout\; id="5"\; label="r\; o"\; filenames="HDA0000028554480000051.png,HDA0000028554480000071.png"\; state="\{\{state\}\}">r</figure-callout>}}_o///{\mathrm{<figure-callout\; id="6"\; label="r\; o"\; filenames="HDA0000028554480000051.png,HDA0000028554480000071.png"\; state="\{\{state\}\}">r</figure-callout>}}_o\&ap;\frac{1+\mathrm{j\&omega;}{Z}^{\&prime;}\left(\mathrm{\&omega;}\right)C_{\mathrm{gs}5}}{{\mathrm{<figure-callout\; id="5"\; label="g\; m"\; filenames="HDA0000028554480000051.png,HDA0000028554480000071.png"\; state="\{\{state\}\}">g</figure-callout>}}_m+{\mathrm{j\&omega;<figure-callout\; id="5"\; label="C\; gs"\; filenames="HDA0000028554480000051.png,HDA0000028554480000071.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}}$

Wherein, g _M5The mutual conductance of expression CMOS pipe M5; C _Gs5The grid source electric capacity of expression CMOS pipe M5; r _O5The internal resistance of expression CMOS pipe M5, r _O6The internal resistance of expression CMOS pipe M6; Z ' is by L (ω) _LAnd C _Gd4+ C _Gd5LC loop (inductance capacitance loop) impedance that constitutes, C _Gd4The gate leakage capacitance of expression CMOS pipe M4; C _Gd5The gate leakage capacitance of expression CMOS pipe M5.

Following formula shows C _Gd5As far as possible little, to obtain better output impedance coupling.For example, so in the embodiment of the invention, the grid width C of CMOS pipe M5 _Gd5Only be made as 30 μ m, CMOS pipe M6 is as a current source, and for the source class follower provides bias current, grid width is made as 60 μ m, and electric current only is 1.06mA.Certainly, the grid width of CMOS pipe M5, M6 also can be set to other values according to actual needs.

4. the biasing circuit unit is used for providing bias voltage to first order amplifier circuit unit, second level amplifier circuit unit and output matching circuit unit.

In the embodiment of the invention, the biasing circuit unit adopts CMOS tube current mirror structure.

(NMOS, N-Mental-Oxide-Semiconductor) structure of basic current mirror as shown in Figure 3 for N channel metal-oxide-semiconductor or N channel field-effect pipe.Make circuit shown in Figure 3 as current mirror, necessary condition is that CMOS pipe M1 and M2 are operated in the saturation region, i.e. V _DS1=V _GS1＞V _GS1-V _T1, V _DS2＞V _DS1-V _T2, wherein, V _DS1The drain-source voltage of expression CMOS pipe M1, V _GS1The gate source voltage of expression CMOS pipe M1; V _T1The threshold voltage of CMOS pipe M1 in the presentation graphs 3, V _DS2The drain-source voltage of expression CMOS pipe M2, V _T2The threshold voltage of CMOS pipe M2 in the presentation graphs 3.

Because:

$I_R=\frac{1}{2}{\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">K</figure-callout>}}_1^{\&prime;}\frac{W_1}{L_1}{(V_{\mathrm{GS}1}-V_{T1})}^2(1+\mathrm{\&lambda;}{2V}_{\mathrm{DS}1})$

$I_o=\frac{1}{2}{\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="HDA0000028554480000051.png"\; state="\{\{state\}\}">K</figure-callout>}}_2^{\&prime;}\frac{W_2}{L_2}{(V_{\mathrm{GS}1}-V_{T2})}^2(1+{\mathrm{\&lambda;}2V}_{\mathrm{DS}2})$

Wherein, I _RThe drain current of CMOS pipe M1 in the presentation graphs 3, K ₁The conduction parameter of CMOS pipe M1 in the ' presentation graphs 3, W ₁The grid width of expression CMOS pipe M1, L ₁The channel length of expression CMOS pipe M1; I _OThe drain current of CMOS pipe M2 in the presentation graphs 3, K ₂The conduction parameter of CMOS pipe M2 in the ' presentation graphs 3, W ₂The grid width of expression CMOS pipe M1, L ₂The channel length of expression CMOS pipe M2.

If CMOS pipe M1 and CMOS pipe M2 mate fully, i.e. K ₁'=K ₂', V _T1=V _T2, λ ₁=λ ₂=λ, then:

$\frac{I_o}{I_R}=\frac{W_2{L}_1(1+{\mathrm{\&lambda;V}}_{\mathrm{DS}2})}{W_1{L}_2(1+\mathrm{\&lambda;}{V}_{\mathrm{DS}1})}$

This shows that cmos current mirror can change I by changing the raceway groove length-width ratio of CMOS pipe M1 and M2 _OAnd I _RRatio, can provide bias voltage for the CMOS pipe, but simultaneously, I _OAnd I _RRatio also be subjected to the influence of raceway groove modulation, in emulation, to take into account.

Wherein, above-mentioned biasing circuit unit can not omit not, promptly can be directly in first order amplifier circuit unit, second level amplifier circuit unit and output matching circuit unit the corresponding C metal-oxide-semiconductor bias voltage is provided, and need not described biasing circuit unit.

The following describes the artificial debugging and the result of the circuit shown in Figure 1 that the embodiment of the invention provides.

1. circuit parameter:

The embodiment of the invention adopts CMOS 0.18 μ m technology, and operating voltage is 1.2V.The amplifier maximum power dissipation is 6.8 milliwatts (mW), and the output buffer power consumption is 1.27mW.

The input matching circuit unit finally draws the value of each element of input matching circuit unit: C according to filter theory and top discussion by ADS emulation and debugging ₁=240pF, L ₁=3.2nH, L _g=1.6nH, L _s=1.06nH, C _p=170fF.The grid width of CMOS pipe M1 is 240 μ m.

The grid width of CMOS pipe M1 can obtain the optimization of noise under certain power consumption is selected, and is chosen in this design I _D=3.39mA is so select CMOS to manage the grid width W=240 μ m of M1 to obtain best noiseproof feature.

Be total to grid CMOS pipe M2 and play a part to isolate input and output, size is more little, and parasitic capacitance is just more little, so half of the grid width that the grid width of CMOS pipe M2 is CMOS manages M1, the grid width of CMOS pipe M3 and M4 is 120 μ m too.

First order amplifier circuit unit and second level amplifier circuit unit all adopt inductive load to compensate the influence of capacitive load, and resonance is exported capacitive reactances.Resistance R _dBe used for improving low-frequency gain and gain flatness.At second level amplifier circuit unit, R _LCan eliminate a spike, load inductance L at the 6GHz place _LBe used for the resonance output capacitance to obtain maximum gain.In first order amplifier circuit unit and second level amplifier circuit unit, L _d=5.9nH, L _L=5.7nH, R _d=90 Ω, R _L=79 Ω.

In the output matching circuit unit, C _Gs5Only be made as 30 μ m to obtain better output coupling so CMOS manages the grid width of M5 as far as possible for a short time, the CMOS pipe M6 provide bias current as a current source for the source class follower, and grid width is made as 60 μ m, and electric current only is 1.06mA.

In the biasing circuit unit, in order to reduce power consumption as far as possible, the grid width of CMOS pipe M7 and M8 all is made as 15 μ m.Resistance R ₂, R ₄, R ₅, R ₆Want enough big (R ₅And R ₆Also belong to the biasing circuit unit), to such an extent as to their equivalent noise current is little of ignoring, can be made as 5k Ω.By debugging R ₁And R ₃, can obtain the highest-gain that required bias current of circuit shown in Figure 1 and first order amplifier circuit unit are reached, can get R by emulation ₁=500 Ω, R ₃=2k Ω.C _C, C ₂, C ₃, C ₄, C ₅Be direct current capacitance, C ₂=2pF, C _C=C ₃=C ₄=C ₅=10pF.

2. simulation result:

Fig. 4, Fig. 5, Fig. 6 are as input direct voltage V shown in Figure 1 _CSimulation result schematic diagram during=1.2V.Among Fig. 4, curve a represents input reflection coefficient S11 post-layout simulation results exhibit; Curve b represents the preceding simulation result of S11; Curve c represents the S22 post-layout simulation results exhibit; Curve d represents the preceding simulation result of output reflection coefficient S22; Curve e represents the S12 post-layout simulation results exhibit; Curve f represents the preceding simulation result of reverse isolation degree S12; Abscissa f is a frequency, and ordinate unit is a decibel.Among Fig. 5, the curve a simulation result before the S21 of representing to gain; Curve b represents the S21 post-layout simulation results exhibit; Curve c represents NF (noise factor) post-layout simulation results exhibit; Curve d represents the preceding simulation result of NF (noise factor); Abscissa f is a frequency, and ordinate unit is a decibel.Among Fig. 6, hand over section on input three rank at 3.8GHz place; Abscissa is an input power, and ordinate is a power output, and unit is dBm.

From Fig. 4, Fig. 5 as can be seen, solid line is preceding simulation result, shows input reflection coefficient S11 less than-10.1dB, and output reflection coefficient S22 is less than-15dB, reverse isolation degree S12＜-62dB.Fig. 5 has shown that this LNA has good gain flatness in 3GHz～5GHz, and highest-gain is 23.8dB, and the minimal noise coefficient is 1.5dB in the band, and average noise factor is 2.4dB; Dotted line is a post-layout simulation results exhibit, all differs in the 3dB with preceding simulation result, reaches more outstanding performance.By shown in Figure 6, hand over section (IIP3) to be-7dBm on input three rank, 3.8GHz place.

Fig. 7, Fig. 8, Fig. 9 are V _CThe simulation result schematic diagram of gain during variation, noise factor and power consumption.Parameter scanning V _CFrom 0.5V to 1.2V, step-length is 0.02V, and Fig. 7 is the change in gain result schematic diagram, and wherein, abscissa f is a frequency, and ordinate is S21 (gain), and unit is a decibel.Realized as can be seen gain from-13dB to the about 36dB adjustable extent of 23dB.V _CReduce promptly to gain when becoming big, NF can worsen, and the power consumption of circuit can reduce, and as Fig. 8, shown in Figure 9, the main body circuit power consumption changes to 6.8mW from 4.54mW.Abscissa f among Fig. 8 is a frequency, and ordinate is a noise factor, and unit is a decibel.Abscissa among Fig. 9 is voltage V _C, unit is a volt, and ordinate is a power, and unit is a milliwatt.

Figure 10 for the gain and noise factor with V _CSimulation result schematic diagram after the variation, wherein, post-layoutSimulation S21 is post-simulation S21, and post-layout Simulation NF is the post-simulation noise factor, and abscissa is voltage V _C, unit is a volt, ordinate is a decibel.As can be seen, it is also little that the front simulation result differs, and obtains better effect.

Area of chip that the embodiment of the invention provides can be 0.71mm ²* (0.96mm*0.74mm).

The performance comparison of the low noise amplifier that the embodiment of the invention provides and existing various low noise amplifiers as shown in figure 11, wherein, * is illustrated in input three rank, 3.8GHz place and hands over sections (IIP3) to be-7dBm; ' represent that power consumption does not comprise the power consumption of output buffer and current mirror, promptly only comprises the power consumption of first order amplifier circuit unit and second level amplifier circuit unit.

By experiment with simulation result as can be seen, the circuit as shown in Figure 1 that the embodiment of the invention provides, under the voltage supply of 1.2V, in 3GHz～5GHz bandwidth, realized-13dB is to the continuous Gain Adjustable function of the about 36dB of 23dB, and the influence to input and output coupling and gain flatness is very little, and average noise factor is 2.4dB.

Referring to Figure 12, the implementation method of a kind of low noise amplifier that the embodiment of the invention provides comprises step:

S101, realize input impedance matching and noise coupling by the input matching circuit unit.

S102, input signal is carried out processing and amplifying by the Gain Adjustable amplifier circuit unit, and the control voltage that utilizes input, Amplifier Gain adjusted.

S103, realize the output impedance coupling, and the signal that will obtain after will handling through the Gain Adjustable amplifier circuit unit be exported by the output matching circuit unit.

Preferably, the input matching circuit unit is the second order Chebyshev filter.

Preferably, the Gain Adjustable amplifier circuit unit adopts cascade source inductance negative feedback structure.

Preferably, the Gain Adjustable amplifier circuit unit adopts two-stage cascade source inductance negative feedback structure.

In sum, in existing technology, designed the continuous and adjustable LNA of discrete gain of arrowband, and the adjustable LNA of the discrete gain of ultra broadband.And the embodiment of the invention is compared with prior art, not only overcome the shortcoming of current Gain Adjustable LNA, proposed to have the continuously adjustable low noise amplifier that is applied to ultra broadband of gain, and have high-gain, high-gain adjustable extent and low noise advantage of low power consumption under big bandwidth on the performance, compare with the various ultra-wideband low-noise amplifiers that proposed in the world, also have advantage on the performance.

The technical scheme that the embodiment of the invention provides can be applied on the various ultra wideband receivers, and ultra-wideband communication system can be applied on mobile phone, data card, the palmtop PC various terminals such as (PDA), also can be applied on the various electrical equipment, to set up following home intelligent wireless network or the like.

Those skilled in the art should understand that embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt complete hardware embodiment, complete software implementation example or in conjunction with the form of the embodiment of software and hardware aspect.And the present invention can adopt the form that goes up the computer program of implementing in one or more computer-usable storage medium (including but not limited to magnetic disc store and optical memory etc.) that wherein include computer usable program code.

The present invention is that reference is described according to the flow chart and/or the block diagram of method, equipment (system) and the computer program of the embodiment of the invention.Should understand can be by the flow process in each flow process in computer program instructions realization flow figure and/or the block diagram and/or square frame and flow chart and/or the block diagram and/or the combination of square frame.Can provide these computer program instructions to the processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing device to produce a machine, make the instruction of carrying out by the processor of computer or other programmable data processing device produce to be used for the equipment of the function that is implemented in flow process of flow chart or a plurality of flow process and/or square frame of block diagram or a plurality of square frame appointments.

These computer program instructions also can be stored in energy vectoring computer or the computer-readable memory of other programmable data processing device with ad hoc fashion work, make the instruction that is stored in this computer-readable memory produce the manufacture that comprises commander equipment, this commander equipment is implemented in the function of appointment in flow process of flow chart or a plurality of flow process and/or square frame of block diagram or a plurality of square frame.

These computer program instructions also can be loaded on computer or other programmable data processing device, make on computer or other programmable devices and to carry out the sequence of operations step producing computer implemented processing, thereby the instruction of carrying out on computer or other programmable devices is provided for being implemented in the step of the function of appointment in flow process of flow chart or a plurality of flow process and/or square frame of block diagram or a plurality of square frame.

Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.

Claims (10)

1. an amplifier is characterized in that, this amplifier comprises:

The input matching circuit unit is used to realize input impedance matching and noise coupling; And the input signal of described amplifier exported to the Gain Adjustable amplifier circuit unit;

The Gain Adjustable amplifier circuit unit be used for described input signal is carried out processing and amplifying, and the signal that will obtain after will handling is exported to the output matching circuit unit; And the control voltage that receives input, and, adjust described Amplifier Gain by described control voltage;

The output matching circuit unit is used to realize the output impedance coupling; And, the signal output that will obtain after will handling through described Gain Adjustable amplifier circuit unit.

2. amplifier according to claim 1 is characterized in that, described Gain Adjustable amplifier circuit unit comprises:

First order amplifier circuit unit be used for described input signal is carried out processing and amplifying, and the signal that will obtain after will handling is exported to second level amplifier circuit unit;

Second level amplifier circuit unit be used for the signal of described first order amplifier circuit unit output is carried out processing and amplifying, and the signal that will obtain after will handling is exported to the output matching circuit unit; And input control voltage, and, adjust described Amplifier Gain by described control voltage.

3. amplifier according to claim 2 is characterized in that, described input matching circuit unit is the second order Chebyshev filter.

4. amplifier according to claim 2 is characterized in that, described first order amplifier circuit unit and described second level amplifier circuit unit adopt cascade source inductance negative feedback structure.

5. amplifier according to claim 4 is characterized in that, described input matching circuit unit links to each other with described first order amplifier circuit unit by field effect transistor M1.

6. amplifier according to claim 5 is characterized in that, described first order amplifying circuit comprises field effect transistor M1 and M2, inductance L _d, resistance R _d, capacitor C ₂

Inductance L _dWith resistance R _dLink to each other resistance R _dLink to each other with the leakage level of field effect transistor M2, the supply power voltage of described amplifier is from inductance L _dInput, capacitor C ₂An end and leakage level and the resistance R of field effect transistor M2 _dLink to each other capacitor C ₂The other end link to each other with described second level amplifier circuit unit;

After first order amplifying circuit carries out processing and amplifying to described input signal, the signal that obtains after handling is passed through capacitor C ₂Export to second level amplifier circuit unit.

7. amplifier according to claim 6 is characterized in that, described second level amplifying circuit comprises field effect transistor M3 and M4, inductance L _L, resistance R _L

Field effect transistor M3 links to each other with field effect transistor M4, and the signal of described first order amplifying circuit output is from the grid input of field effect transistor M3, and control voltage is from the grid input of field effect transistor M4, leakage level and the resistance R of field effect transistor M4 _LLink to each other; Inductance L _LWith resistance R _LLink to each other, the supply power voltage of described amplifier is from inductance L _LInput.

8. according to the described amplifier of the arbitrary claim of claim 1-7, it is characterized in that this amplifier also comprises:

The biasing circuit unit is used for providing bias voltage to described first order amplifier circuit unit, described second level amplifier circuit unit and described output matching circuit unit.

9. amplifier according to claim 8 is characterized in that, described biasing circuit unit adopts the field effect transistor current-mirror structure.

10. the implementation method of an amplifier is characterized in that, this method comprises:

Realize input impedance matching and noise coupling by the input matching circuit unit;

By the Gain Adjustable amplifier circuit unit input signal is carried out processing and amplifying, and the control voltage that utilizes input, described Amplifier Gain adjusted;

Realize the output impedance coupling by the output matching circuit unit, and the signal output that will obtain after will handling through described Gain Adjustable amplifier circuit unit.

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