CN1757121A

CN1757121A - Field-effect transistor with spin-dependent transmission characteristic and nonvolatile memory using same

Info

Publication number: CN1757121A
Application number: CN 200480005706
Authority: CN
Inventors: 菅原聪; 田中雅明
Original assignee: Japan Science and Technology Agency
Current assignee: Japan Science and Technology Agency
Priority date: 2003-03-07
Filing date: 2004-01-23
Publication date: 2006-04-05

Abstract

When a gate voltage V<SUB>GS </SUB>is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagnetic contact ( 3 b) are not injected because of the energy barrier due to semiconductive spin band of the ferromagnetic source ( 3 a). That is, only up-spin electrons are injected into the channel layer from the ferromagnetic source ( 3 a). If the ferromagnetic source ( 3 a) and the ferromagnetic drain ( 5 a) are parallel magnetized, up-spin electrons are conducted through the metallic spin band of the ferromagnetic drain to become the drain current. Contrarily, if the ferromagnetic source ( 3 a) and the (ferromagnetic drain ( 5 a) are antiparallel magnetized, up-spin electrons cannot be conducted through the ferromagnetic drain ( 5 a) because of the energy barrier Ec due to the semiconductive spin band in the ferromagnetic drain ( 5 a). Thus, a high-performance high-degree of integration nonvolatile memory composed of MISFETs operating on the above operating principle can be fabricated.

Description

Have the field-effect transistor of spin correlation transfer characteristic and used its nonvolatile memory

Technical field

The present invention relates to a kind of new transistor, in more detail, relate to and a kind ofly have the field-effect transistor of spin correlation transfer characteristic and used its nonvolatile memory.

Background technology

The development of advanced information society in recent years makes one notice, and particularly recently, installs as media just sharp in expansion among the people with " portable ".Though " mancarried device " this big demand of recognizing can become the needs of semi-conductor industry from now on, but it is corresponding, except the high speed of semiconductor integrated circuit, low power consumption, high capacity and so on high performance as existing, also produced necessity according to the non-volatile this new requirement of information.At this requirement, as non-volatile high density recording, positive focal attention is a kind of to have merged the new memory device that superior ferromagnetism body memory technology and semiconductor integrated electronic learn a skill.This device is called as MAGNETIC RANDOM ACCESS MEMORY (magnetoresistive random access memory; Hereinafter referred to as " MRAM "), ferromagnetism tunnel junction (the magnetic tunnel junction that will have the structure of the tunnel barrier of using the thin insulating properties of ferromagnetism electrode clamping; Hereinafter referred to as " MTJ ") as this memory element (for example, with reference to K.Inomata, " magnetic RAM technology now and following ", IEICETrans.Electron.Vol.E84-C, pp740-746,2001.).

Tunnel resistor is different with the interelectrode relative direction of magnetization of ferromagnetism in MTJ.Be referred to as tunnel magnetoresistive (tunneling magnetoresistance; Hereinafter referred to as " TMR ") effect.If use TMR, then the magnetized state that detects the ferromagnetism body with electrical way becomes possibility.Thereby including the non-volatile memory technology of the information of ferromagnetism body in the semiconductor integrated electronics ideally because of the existence of MTJ becomes possibility.

Below, an example of prior art is described with reference to Figure 10.As shown in figure 10, in the memory cell 100 of MRAM, the main method that constitutes 1 memory cell by 1 MTJ101 and 1 metal-oxide semiconductor fieldeffect transistor (hereinafter referred to as " MOSFET ") 103 that adopts.MTJ101 is by the 1st ferromagnetism electrode the 105, the 2nd ferromagnetism electrode 107 with being arranged at the tunnel junction that tunnel barrier (insulator) 108 that insulator between the two forms constitutes.

With source (S) ground connection (GND) of MOSFET, usefulness bolt PL etc. will leak (D) and be connected with the ferromagnetism electrode 107 of MTJ101.Another ferromagnetism electrode 105 of MTJ101 is connected with bit line BL, rewrite with word line 111 directly over the MTJ101 or under connect up with MTJ101 and other and to intersect and under the state that has carried out electric insulation with dielectric film 115, dispose across with bit line BL.Read with word line WL and be connected with the gate electrode G of MOSFET103.

In the ferromagnetism body owing to can keep magnetized direction non-volatilely, so in MTJ by the interelectrode relative magnetized state of ferromagnetism is carried out parallel magnetization or antiparallel magnetization, can store the information of 2 values non-volatilely.In addition, in MTJ, under 2 interelectrode relative magnetized states of ferromagnetism, tunnel resistor is different because of the TMR effect.Thereby if adopt the tunnel resistor corresponding with the magnetized state of parallel magnetization, antiparallel magnetization, then available electrical way detects the magnetized state in the MTJ.

The rewriting of information is by changing the confining force of 2 the ferromagnetism electrodes 105,107 among the MTJ101, or the direction of magnetization of fixing a ferromagnetism electrode, carry out and make little ferromagnetism electrode of confining force or the unfixed ferromagnetism electrode of the direction of magnetization carry out magnetization inversion.Below, the ferromagnetism electrode that will carry out magnetization inversion is called free layer, and the ferromagnetism electrode that does not carry out magnetization inversion is called pinned layer.Specifically, electric current flows through the bit line BL that intersects respectively and rewrites with word line 111 on selected cell, makes the magnetized state of the MTJ101 in the memory cell of having been selected by the resultant magnetic field in the magnetic field of each current-induced 100 become parallel magnetization or antiparallel magnetization.At this moment, do not carry out magnetization inversion as the non-selected cell that has the bit line BL identical or rewrite with word line 111 with selected unit, preestablish the current value that flows through wiring separately, make employing only come the unlikely MTJ101 of non-selected cell that makes in magnetic field of My World wiring to carry out magnetization inversion.Reading of information is to make and make the drive current of reading usefulness flow to MTJ101 through bit line BL after the MOSFET103 conducting to carry out by the word line WL that reads usefulness that is connected with selected cell being applied voltage.In MTJ101, because tunnel resistor is different with the magnetized state of parallel magnetization that is caused by the TMR effect or antiparallel magnetization, if so detect voltage drop among the MTJ101 that the drive current of reading usefulness causes (below, be called " output voltage "), then the decidable magnetized state (with reference to K.Inomata, " magnetic RAM technology now and following ", IEICE Trans.Electron.Vol.E84-C, pp740-746,2001.).

Summary of the invention

In MTJ, with across tunnel barrier and the magnetized state of opposed ferromagnetism electrode be parallel magnetization or antiparallel magnetization accordingly, get the resistance value of 2 values.In order to go out arbitrary information of the information of whether storing this 2 value with high-sensitivity detection with drive current, be necessary to regulate the impedance (junction resistance) of MTJ itself, make the size of output voltage optimum.

And then, for the memory contents of sense information exactly, must increase the ratio of the output signal between parallel magnetization and these 2 magnetized states of antiparallel magnetization.For this reason, must increase the rate of change of the TMR separately when MTJ has parallel when magnetization and has antiparallel magnetization that is referred to as the TMR ratio.TMR is than the spin polarizability P that depends on the ferromagnetism electrode, but bigger for the TMR ratio is obtained, ferromagnetism body that must the P value is big is used for the ferromagnetism electrode.

In addition, the TMR among the MTJ depends on the bias voltage that is applied on the MTJ than strongly, sharply reduces with bias voltage.When making big drive current flow through MTJ in order to carry out reading of information with high sensitivity or high speed, the voltage drop among the MTJ increases, and TMR is than reducing.Therefore,, also the bias voltage that can bear the TMR ratio must be arranged, make TMR than unlikely minimizing even in MTJ, produce big voltage drop.

MRAM since simple in structure and MTJ can miniaturization to the size of nanoscale, be to be suitable for the integrated memory of high density.Realize high integration more than thousands of megabits as desire, the channel length of then estimating MOSFET reaches below the 0.1um magnitude, even but desire at so fine transistor fine MTJ is integrated, also, make with super-high density both integrated difficulties that becomes because of contact, multilayer wiring occupy cellar area.Thereby hope has the memory cell of simpler structure.

The objective of the invention is to, provide a kind of schottky junction that the ferromagnetism body is formed to be used for the metal-insulator-semiconductor field effect transistor (MISFET) of source and leakage.In addition, the present invention also aims to, provide a kind of big capacity, nonvolatile semiconductor memory member by constituting 1 memory cell with single this transistor.

Description of drawings

Fig. 1 is the profile that the summary of the MISFET of expression the 1st execution mode of the present invention constitutes.

Fig. 2 (A) is used for the energy band diagram that ferromagnetism source/semiconductor layer/ferromagnetism of accumulation n channel-type MISFET of the structure of Fig. 1 that ferromagnetism source and ferromagnetism leak is leaked with the ferromagnetism metal.Fig. 2 (B) is the energy band diagram that the ferromagnetism source/semiconductor layer/ferromagnetism among the transoid n channel-type MISFET is leaked.

Fig. 3 is the figure of structure of the MISFET of expression the 2nd execution mode of the present invention, and Fig. 3 (A) is used for the energy band diagram that ferromagnetism source/semiconductor layer/ferromagnetism of accumulation n channel-type MISFET of the structure of Fig. 1 that ferromagnetism source and ferromagnetism leak is leaked with semimetal.Fig. 3 (B) is the energy band diagram that the ferromagnetism source/semiconductor layer/ferromagnetism among the transoid n raceway groove MISFET is leaked.

Fig. 4 is the figure of operation principle of the MISFET of the band structure of expression with Fig. 2 (A), and Fig. 4 (A) is the energy band diagram in the poised state, and Fig. 4 (B) leaks under the parallel magnetized situation with ferromagnetism in the ferromagnetism source to have applied V _DSThe time energy band diagram, Fig. 4 (C) is from the state of Fig. 4 (B) and then has applied V _GSThe time energy band diagram, Fig. 4 (D) is the energy band diagram under the situation of antiparallel magnetization leaking in ferromagnetism source and ferromagnetism under the biasing identical with Fig. 4 (C).

Fig. 5 is the figure of operation principle of the MISFET of the band structure of expression with Fig. 2 (B), and Fig. 5 (A) is the energy band diagram in the poised state, and Fig. 5 (B) leaks under the parallel magnetized situation with ferromagnetism in the ferromagnetism source to have applied V _DSThe time energy band diagram, Fig. 5 (C) is from the state of Fig. 5 (B) and then has applied V _GSThe time energy band diagram, Fig. 5 (D) is the energy band diagram under the situation of antiparallel magnetization leaking in ferromagnetism source and ferromagnetism under the biasing identical with Fig. 5 (C).

Fig. 6 is the figure of operation principle of the MISFET of the band structure of expression with Fig. 3 (A), and Fig. 6 (A) is the energy band diagram in the poised state, and Fig. 6 (B) leaks under the parallel magnetized situation with ferromagnetism in the ferromagnetism source to have applied V _DSThe time energy band diagram, Fig. 6 (C) is from the state of Fig. 6 (B) and then has applied V _GSThe time energy band diagram, Fig. 6 (D) is the energy band diagram under the situation of antiparallel magnetization leaking in ferromagnetism source and ferromagnetism under the biasing identical with Fig. 6 (C).

Fig. 7 is the figure of operation principle of the MISFET of the band structure of expression with Fig. 3 (B), and Fig. 7 (A) is the energy band diagram in the poised state, and Fig. 7 (B) leaks under the parallel magnetized situation with ferromagnetism in the ferromagnetism source to have applied V _DSThe time energy band diagram, Fig. 7 (C) is from the state of Fig. 7 (B) and then has applied V _GSThe time energy band diagram, Fig. 7 (D) is the energy band diagram under the situation of antiparallel magnetization leaking in ferromagnetism source and ferromagnetism under the biasing identical with Fig. 7 (C).

The concept map of the leakage current-voltage characteristic when Fig. 8 is the source ground connection of MISFET of present embodiment.

Fig. 9 (a) is the figure of a configuration example of the memory circuit of the expression MISFET that adopted present embodiment.Fig. 9 (b) is that the bit line end at the memory circuit shown in Fig. 9 (a) has lead-out terminal V _O, and from this lead-out terminal V _OBranch, the memory circuit that is connected with supply voltage VDD through load RL.Fig. 9 (c) is the static characteristic of the memory cell shown in the presentation graphs 9 (b) and the figure of working point.

Figure 10 is the profile of the structure of the expression memory cell of using general MRAM.

Figure 11 is an example of the memory cell structure of expression the embodiments of the present invention, is the figure of the configuration example in the total ferromagnetism source of expression.

Figure 12 is the energy band diagram of structure example of the MISFET of expression the 3rd execution mode of the present invention.

Figure 13 is the energy band diagram of the structure example of the expression the of the present invention the 4th and the MISFET of the 5th execution mode, Figure 13 (A) is that expression is used for source/leakage with n type ferromagnetism semiconductor, between source/leakage, used the structure example of the MISFET of intrinsic semiconductor, Figure 13 (B) is that expression is used for source/leakage with n type ferromagnetism semiconductor, has used the figure of structure example of the MISFET of p N-type semiconductor N between source/leakage.

Embodiment

Metal-insulator-semiconductor field effect transistor of the present invention (below, be called " MISFET ") storage as the leakage that constitutes by the ferromagnetism body (below, be called " ferromagnetism source ", " ferromagnetism leakage ") with respect to the information of the relative direction of magnetization in the source that constitutes by the ferromagnetism body, read the information that depends on the transfer characteristic of this relative direction of magnetization and be stored of utilizing.Thereby, if adopt MISFET of the present invention, then because available single transistor constitutes 1 bit non-volatile memory cell, so can realize high speed, jumbo nonvolatile memory.

At first, describe with reference to the MISFET of accompanying drawing the 1st execution mode of the present invention.

Fig. 1 is the figure of cross-section structure of the MISFET of expression the 1st execution mode of the present invention.As shown in Figure 1, the gate electrode 7 that the MISFET of present embodiment has and general MISFET (for example SiMISFET etc.) is same, gate insulating film 11, the MIS structure that constitutes by nonmagnetic semiconductor layer 1, and nonmagnetic semiconductor layer 1 between form the source (ferromagnetism source) 3 that constitutes by the ferromagnetism body of schottky junction and leak (ferromagnetism leakage) 5.Ferromagnetism source and ferromagnetism are leaked can adopt Fe, Ni, Co, permalloy, CoFe alloy (Co _1-xFe _x), CoFeB alloy (Co _1-x-yFe _xB _y) etc. ferromagnetism metal and Co ₂Cobalt manganese silicon ferromagnetism alloy (Heusler alloy), CrO such as MnSi ₂, Fe ₃O ₄Semimetals such as the CrAs of (magnetic iron ore), zincblende type, CrSb, MnAs.In addition, also can adopt the ferromagnetism semiconductor of band structure and have and become the ferromagnetism of semimetallic band structure semiconductor with ferromagnetism metalline.Ferromagnetism source 3 and ferromagnetism leak 5 by epitaxial growth on nonmagnetic semiconductor layer 1 or the formation of deposit ferromagnetism body.Perhaps, also methods such as available heat diffusion or ion injection import magnetic atom formation at nonmagnetic semiconductor layer 1.In addition, the arrow shown in ferromagnetism source in the drawings and ferromagnetism are leaked is upward represented the direction of magnetization.Have again,, can adopt SiO as gate insulating film ₂, Al ₂O ₃Or as the HfO of high dielectric constant material ₂Deng.

In the MISFET of present embodiment, can be with the charge carrier of the conduction type identical as conduction carrier with nonmagnetic semiconductor layer (or Semiconductor substrate) 1, perhaps, also can induct the charge carrier of the conduction type opposite as conduction carrier with nonmagnetic semiconductor layer 1.Herein, for convenience's sake, the former is called the accumulation channels type, the latter is called the inversion channel type.When constituting the MISFET of n raceway groove, for the accumulation channels type, use the n N-type semiconductor N, for the inversion channel type, use the p N-type semiconductor N.Equally, when constituting the MISFET of p raceway groove,, use the p N-type semiconductor N,, use the n N-type semiconductor N for the inversion channel type for the accumulation channels type.After, the accumulation channels type of n raceway groove is called accumulation n channel-type, the inversion channel type of n raceway groove is called transoid n channel-type.For the p raceway groove, also with the situation of n raceway groove similarly, be called accumulation p channel-type, transoid p channel-type.

In addition, with having or not irrespectively of the raceway groove of reality, the semiconductor region under gate insulating film/interface is called channel region.Below, situation and the accumulation n channel-type separately that uses semimetallic situation and the band structure of transoid n channel transistor that the ferromagnetism metal is used for the leakage of ferromagnetism source and ferromagnetism described.Have again, though below omitted detailed explanation, with same way, can constitute the MISFET of accumulation p channel-type and transoid p channel-type.In the present invention, though can constitute the MISFET of enhancement mode and depletion type,, only narrate enhancement mode following.In addition, originally the term of " spin " and so on is the term that uses explicitly with spin angular momentaum, but following, and the electronics of also taking to have the spin of going up only is called the mode that spins etc. and uses this term on the meaning of charge carrier.

Fig. 2 (A) and Fig. 2 (B) are the energy band diagrams when the ferromagnetism metal is used as the ferromagnetism body, and Fig. 3 (A) and Fig. 3 (B) are the energy band diagrams when semimetal is used as the ferromagnetism body.

Near the figure of the band structure the channel region of the accumulation n channel-type MISFET of Fig. 2 (A) when to be expression with the ferromagnetism metal be used for ferromagnetism source and ferromagnetism and leak.It is to combine and form by nonmagnetic n type semiconductor layer 1 and ferromagnetism metal (3,5) being carried out Schottky that ferromagnetism source 3 and ferromagnetism leak 5.Dotted line shown on solid line shown in ferromagnetism source 3 among Fig. 2 (A) and the leakage 5 and the n type semiconductor layer 1 represents that Fermi can EF.EG represents semi-conductive band gap.

E _CAnd E _VRepresent at the bottom of the conduction band of semiconductor layer 1 respectively and the valence band top.E _F, E _C, E _V, E _CIn following figure, also be used with same meaning.φ _nBarrier height for the schottky junction of ferromagnetism metal and n N-type semiconductor N.That is, expression Fermi can E _FWith E at the bottom of the conduction band of the n type semiconductor layer 1 at junction interface place _CEnergy difference.In addition, leak 5 the Fermi arrow shown in going up in ferromagnetism source 3 and ferromagnetism and represent the directions of most spins, as be last to, spin expression in, as for down to, spin under representing.In addition, the demonstration of minority spin is omitted.Below, when using the ferromagnetism metal, on energy band diagram, show the direction of most spins with same way.

Near the figure of the band structure the channel region of the transoid n channel-type MISFET of Fig. 2 (B) when to be expression with the ferromagnetism metal be used for ferromagnetism source and ferromagnetism and leak.The ferromagnetism source 3 and the ferromagnetism leakage 5 that are made of the ferromagnetism metal form schottky junction with p type semiconductor layer 1.φ _pBeing the barrier height of the schottky junction of ferromagnetism metal and p type semiconductor layer 1, is that Fermi can E _FValence band top E with the p type semiconductor layer at junction interface place _VEnergy difference.φ _nFor Fermi can E _FWith E at the bottom of the conduction band of the p type semiconductor layer at junction interface place _CEnergy difference.

Then, describe with reference to the MISFET of accompanying drawing the 2nd execution mode of the present invention.

Fig. 3 (A) is the MISFET of present embodiment, and being expression is used near the figure of the band structure the channel region of accumulation n channel-type MISFET of the situation that ferromagnetism source and ferromagnetism leak with semimetal.Semimetal to a side spin get metalline band structure (below, be called " spin band of metalline "), and the opposing party's spin had the band structure that becomes semiconductor (insulator) character (below, be called " spin band of semiconductor property ").That is, in semimetal, a side spin is had until being with that halfway is all occupied, the opposing party's spin is then separated by means of can be with (valence band) and empty can be with (conduction band) that band gap will be filled up fully.Thereby Fermi can E _FThe spin band of the metalline of a transversal side's spin, in the middle of the then transversal band gap of the opposing party's spin, the become side's that only bears the spin band that belongs to metalline spin of the conduction of charge carrier.

In Fig. 3 (A), leaking the solid line shown in the central authorities of 5a in ferromagnetism source 3a and ferromagnetism is that Fermi in the semimetal can E _FThat is E, _FBecome the Fermi surface of the spin band of metalline.In addition, at E _FUp and down shown in solid line E _C ^HM, E _V ^HMRepresent at the bottom of the conduction band in the spin band of semiconductor property respectively and the valence band top.E _G ^HMThe band gap of the spin band of the semiconductor property of expression semimetal (3a5a).Adopting semimetal (3a5a) to form under the situation of accumulation n channel-type MISFET, must make the spin band of the metalline in the semimetal (3a5a) and n type semiconductor layer 1 formation barrier height is φ _nSchottky junction.In addition, for this knot, have at the bottom of the conduction band in the spin band of the semiconductor property in its semimetal (3a5a) high energy at the bottom of the conduction band than n type semiconductor layer 1, at the interface, ideal situation is to form the discontinuous Δ E of energy _C

The discontinuous Δ E of energy _CIt is the energy difference of the energy that pushes up of the valence band in the n type semiconductor layer 1 at energy and place, junction interface on valence band top of spin band of the semiconductor property in the semimetal (3a5a).Below, similarly leak under the situation of 5a semimetal being used for ferromagnetism source 3a and ferromagnetism, the energy discontinuous quantity at the place, junction interface of the semiconductor layer 1 of conduction band in the spin band of semiconductor property and valence band is decided to be Δ E respectively _CWith Δ E _V

In addition, in the drawings, the Fermi's energy with the non magnetic 3b5b of contact of ferromagnetism leakage 5a combination with the ferromagnetism source 3a that is made of semimetal is shown also.Thereby the ferromagnetism source 3 of Fig. 1 is made of with the non magnetic 3b of contact ferromagnetism source 3a having adopted under semimetallic situation.Leak too about ferromagnetism.In addition, below record and narrate not specifying ferromagnetism metal or semimetal to ferromagnetism source 3 or ferromagnetism and leak under 5 the situation, suppose to comprise ferromagnetism source 3a and ferromagnetism is leaked 5a.φ _n' be Fermi's energy E of this non magnetic contact 3b5b _FWith the conduction band E in the spin band of semiconductor property in the semimetal (3a5a) _C ^HMEnergy difference.

In Fig. 3 (B), show near the band structure the channel region of the transoid n raceway groove MISFET under the situation that semimetal is used for the leakage of ferromagnetism source and ferromagnetism.

Must carry out incompatible formation ferromagnetism source 3a of schottky junction and ferromagnetism by the spin band that makes p type semiconductor layer 1 and semimetallic metalline and leak 5a.φ _pBarrier height for the schottky junction of the spin band of the metalline in the semimetal (3a5a) and p type semiconductor layer 1.φ _nFermi in the expression semimetal (3a5a) can E _FWith E at the bottom of the conduction band of the p type semiconductor layer 1 at junction interface place _CEnergy difference.In addition, than the energy height at the bottom of the conduction band of p type semiconductor layer 1, at the interface, ideal situation is to generate Δ E at the bottom of the conduction band in the spin band of the semiconductor property of semimetal (3aSa) _CEnergy discontinuous.

φ _n' and φ _p' be respectively Fermi can with E at the bottom of the conduction band of the spin band of semiconductor property in the semimetal (3a5a) _C ^HMWith valence band top E _V ^HMPoor.

Below, describe with reference to the operation principle of accompanying drawing each MISFET of above-mentioned present embodiment.In the MISFET of present embodiment, the ferromagnetism source has as the spin that spin is injected in the raceway groove injects sub function, in addition, ferromagnetism is leaked and is had the function of analyzing son as the direction that detects the spin that is injected into the conduction carrier in the raceway groove as the spin of the signal of telecommunication.In the MISFET of present embodiment, as mentioned above, also the ferromagnetism metal can be used for ferromagnetism source and ferromagnetism and leak, perhaps also semimetal can be used for ferromagnetism source and ferromagnetism and leak.In addition, also can the source and a side of leakage be the ferromagnetism metal, the opposing party is a semimetal.

Below, the relative direction of magnetization that ferromagnetism is leaked the ferromagnetism source is that equidirectional situation is decided to be parallel magnetization, the direction of magnetization that they are relative is that mutual reciprocal situation is decided to be antiparallel magnetization.In addition, suppose that the channel length of MISFET is short fully apart from comparing with the relaxation of spin, in addition, can ignore the Rashba effect of gate voltage.

With reference to Fig. 4 (A) operation principle that the ferromagnetism metal is used for the accumulation n channel-type MISFET of ferromagnetism source and ferromagnetism leakage is described to Fig. 4 (D).Fig. 4 (A) is the energy band diagram in the poised state, is and the corresponding figure of Fig. 2 (A).

From the poised state of Fig. 4 (A), if between ferromagnetism source 3 and gate electrode 7, apply bias voltage V _GSAnd make V _GS=0, between ferromagnetism source 3 and ferromagnetism leakage 5, apply bias voltage V _DS, then leak 5 schottky junction place with V in the schottky junction in ferromagnetism source 3 and ferromagnetism _DSDividing potential drop obtains the electromotive force shown in Fig. 4 (B).Ferromagnetism is leaked 5 schottky junction by forward bias, the barrier height of the leakage side schottky junction of seeing at the bottom of the conduction band of raceway groove central portion reduces (or disappearance), and the schottky junction in ferromagnetism source 3 is reverse biased, see at the bottom of the conduction band of raceway groove central portion at the source schottky junction, barrier height increases.At this moment, apply V _DS, make the Fermi in ferromagnetism source 3 can E _FThe energy band edge of transversal source Schottky barrier, V _DSIt is the bias voltage that tunnel(l)ing current produces the size of the sort of degree hardly.That is, from the Fermi in source schottky junction interface to ferromagnetism source 3 can with this Schottky barrier can the band edge infall thick fully apart from d, thick to the sort of degree of tunnel effect that does not produce charge carrier from ferromagnetism source 3 to raceway groove.Because the schottky junction of source is reverse biased, to cross from ferromagnetism source 3 by warm-up movement highly be φ so produced _nThe electric current of reverse saturation current degree of the schottky junction that charge carrier caused of potential barrier, and by selected φ suitably _n, can suppress fully to reduce this electric current composition.Thereby, at V _GS=0 o'clock, MISFET became cut-off state.

Then, if gate electrode 7 (Fig. 1) is applied bias voltage V _GS(＞0) then utilizes the power line that points to ferromagnetism sources 3 from gate electrode 7 to strengthen near the source Schottky barrier electric field, and shown in Fig. 4 (C), the barrier width of Schottky barrier reduces (d ' among the figure).Thereby the conduction electron in ferromagnetism source 3 is because of tunnel effect sees through this potential barrier, is injected into the channel region under the gate insulating film 11.At this moment, 3 inject most spins and minority spin from the ferromagnetism source, and because the carrier density of most spins is bigger than the carrier density of minority spin, so inject electronics generation spin polarization.Inject near the spin polarizability of Fermi's energy that the electronic spin polarizability depends on ferromagnetism source 3, this spin polarizability is big more, and it is also big more to inject the electronic spin polarizability.

Below, electronics after the spin polarization is called spinning polarized electron.The majority spin of spinning polarized electron is parallel with the minority spin with the majority spin in ferromagnetism source 3 respectively with the minority spin.Be injected into spinning polarized electron in the raceway groove on one side at V _GSEffect under attracted to gate insulating film/interface, on one side at V _DSEffect under be transported to ferromagnetism and leak 5 schottky barrier interface.Leak 5 in ferromagnetism source 3 with ferromagnetism and have under the parallel magnetized situation, the spin of the majority of spinning polarized electron is parallel with the minority spin with the majority spin of ferromagnetism leakage 5 respectively with the minority spin.Thereby, be injected into ferromagnetism and leak spinning polarized electron in 5 and be subjected to the influence of spin-dependent scattering hardly and be formed on ferromagnetism and leak conduction in 5, flow into ferromagnetism and leak 5 electric current (below, claim this electric current to be " leakage current ").Particularly, leak 5 in ferromagnetism source 3 with ferromagnetism and have under the parallel magnetized situation, will generate the V of certain leakage current of determining _GSBe decided to be threshold value V _T

On the other hand, 3 leak 5 with ferromagnetism and have under the situation of antiparallel magnetization in the ferromagnetism source, and among the spinning polarized electron in being injected into raceway groove, most spins and ferromagnetism are leaked 5 majority spin antiparallel (Fig. 4 (D)).Thereby the spinning polarized electron of raceway groove leaks in ferromagnetism and produces the resistance that spin-dependent scattering causes in 5.Thereby, even MISFET is under the same biasing, under the situation of antiparallel magnetization, to compare with cause parallel magnetized situation because of this spin-dependent scattering, leakage current also reduces.That is, compare with leak the transefer conductance (mutual conductance) that the relative magnetized state between 5 has under the parallel magnetized situation in ferromagnetism source 3 and ferromagnetism, the transefer conductance that has under the situation of antiparallel magnetization reduces.In addition, if channel length is below the mean free path to energy relaxation of charge carrier, then owing to charge carrier impact type ground conducts in raceway groove, so can expect and the similar magneto resistance effect of tunnel magneto-resistance effect.At this moment, the variation of the transefer conductance in parallel magnetization and the antiparallel magnetization is bigger.

Fig. 5 (A) is the figure that represents the ferromagnetism metal is used for source 3 and the operation principle of the transoid n channel-type MISFET of leakage 5 to Fig. 5 (D).From poised state (Fig. 5 (A)), if at V _GSApply V under=0 the state _DS(＞0), then shown in Fig. 5 (B), ferromagnetism source 3 is by forward bias, and ferromagnetism is leaked 5 and is reverse biased.Because channel region is the p type, thus if leak 5 injected holes, then produce electric current from ferromagnetism, and leak 5 the schottky junction injected hole that is reverse biased by ferromagnetism hardly.Produced by warm-up movement and crossed φ _pThe little electric current of reverse saturation current degree of the schottky junction that causes of hole, and as long as suitably select φ _p, can reduce this electric current fully.Thereby, at V _GS=0 o'clock, MISFET became cut-off state.

If gate electrode 7 (Fig. 1) is applied a certain threshold value V that determines by device architecture _TAbove V _GS(＞V _T), the electronics of then inducting at gate insulating film/interface place, the formation inversion layer (thereby, for inversion channel type and accumulation channels type, threshold value V _TThe definition difference, and for convenience's sake, under any circumstance, all the threshold value note is made V _T).At this moment, ferromagnetism source 3 in channel region and ferromagnetism are leaked 5 place, junction interface separately, and to the electronics of inversion layer, having formed barrier height is φ _nPotential barrier, and at V _DSEffect under the ferromagnetism knot that leaks 5 knot and ferromagnetism source 3 to be biased to Fig. 5 (C) such.

As mentioned above, if select fully big φ _p, φ then _n(=E _G-φ _p) less, spinning polarized electron is injected into the raceway groove because of heat emission from ferromagnetism source 3.In addition, at φ _nLittle of going out in the absence of charge carrier from 3 heat emissions of ferromagnetism source, with the accumulation channels type similarly also can tunnelling ferromagnetism source 3 sides Schottky barrier, spinning polarized electron is injected into the raceway groove from ferromagnetism source 3.

Be injected into spinning polarized electron in the raceway groove at V _DSEffect under be transported to the schottky barrier interface that ferromagnetism is leaked 5 sides.Leak 5 in ferromagnetism source 3 with ferromagnetism and have under the parallel magnetized situation, the spin of the majority of spinning polarized electron is parallel with the minority spin with the majority spin of ferromagnetism leakage 5 respectively with the minority spin.Thereby, under parallel magnetized situation, with the situation of accumulation channels type similarly, be injected into the spinning polarized electron that ferromagnetism leaks in 5 and be subjected to the influence of spin-dependent scattering hardly and leak conduction in 5 in ferromagnetism, form leakage current.

On the other hand, shown in Fig. 5 (D), 3 leak 5 with ferromagnetism and have under the situation of antiparallel magnetization in the ferromagnetism source, and the majority spin that is injected into the spinning polarized electron in the raceway groove and ferromagnetism are leaked 5 majority spin antiparallel.Thereby spinning polarized electron leaks in ferromagnetism and produces the resistance that causes because of spin-dependent scattering in 5.Thereby even the inversion channel type, the transefer conductance of MISFET also changes with the relative magnetized state that ferromagnetism source 3 and ferromagnetism are leaked between 5.That is, even under same biasing, 3 leak 5 with ferromagnetism and have under the situation of antiparallel magnetization in the ferromagnetism source, compare with parallel magnetized situation, and leakage current also reduces.In addition, with the situation of accumulation channels type similarly, if channel length is below the mean free path to energy relaxation of charge carrier, then owing to expecting and the similar magneto resistance effect of tunnel magneto-resistance effect, so the variation of the transefer conductance in parallel magnetization and the antiparallel magnetization is bigger.

Then, illustrate the situation of semimetal as the ferromagnetism body.To Fig. 6 (D), the operation principle that semimetal is used for the accumulation n channel-type MISFET of the situation that ferromagnetism source and ferromagnetism leak is described with reference to Fig. 6 (A).Fig. 6 (A) is the energy band diagram in the poised state, is and the corresponding figure of Fig. 3 (A).

Fig. 6 (B) is at V _GSApplied V under=0 the state _DSThe figure of the electromotive force shape under the situation of (＞0).Below, shown in Fig. 6 (B), the spin of spin band that will belong to the metalline of ferromagnetism source 3a is decided to be spin, and the spin that will belong to the spin band of semiconductor property is decided to be spin down.The going up of spin band that belongs to metalline spinned, and locating with the junction interface of semiconductor layer 1, is φ owing to form barrier height _nSchottky junction, V then _DSBy source schottky junction and leakage side schottky junction dividing potential drop.Thereby ferromagnetism is leaked the schottky junction of 5a by forward bias, and the schottky junction of ferromagnetism source 3a is reverse biased.At this moment, apply V _DS, make the Fermi of ferromagnetism source 3a can E _FTransversal source Schottky barrier can band edge, and the barrier width d of schottky junction thickens supreme spin not from the sort of degree of spin band tunnelling of the metalline of ferromagnetism source 3a.That is, at V _GSUnder=0 the state, going up from the injection of the tunnel of rotation direction channel region of the spin band of the metalline of ferromagnetism source 3a is suppressed.In addition, as because of cross the barrier height φ of schottky junction by warm-up movement _nAnd the reverse saturation current of the schottky junction that produces, last spin can be injected channel region, and by suitably selecting φ _nValue, can reduce this current value fully.

On the other hand, by means of having the down band gap of the spin band of the semiconductor property of the ferromagnetism source 3a of spin, the formation barrier height is φ between the spin band of the semiconductor property of ferromagnetism source 3a and the non magnetic 3b of contact _n' the energy barrier.Owing in the spin band of the semiconductor property of ferromagnetism source 3a, do not have conduction carrier, so in order to descend spin to be injected in the semiconductor layer 1, following spin must perhaps be crossed potential barrier by warm-up movement from the non magnetic spin band that contacts the semiconductor property of 3b tunnelling ferromagnetism source 3a.If thicken the thickness of ferromagnetism source 3a fully, and select the barrier height φ of the energy barrier seen from nonmagnetic metal electrode 3b by sufficient height _n', then down spin be injected into probability in the channel region can accomplish extremely low, the injection that does not produce charge carrier.Thereby, at V _GSUnder=0 the state, produce hardly because of last spin and the following electric current that spins and cause, MISFET becomes cut-off state.

Then, shown in Fig. 6 (C), if gate electrode 7 (Fig. 1) is applied bias voltage V _GS(＞0), then owing to have from the power line of gate electrode 7 (Fig. 1) towards ferromagnetism source 3a, near the source Schottky barrier electric field is enhanced, and has reduced the barrier width (with reference to the d ' among Fig. 6 (C)) to the Schottky barrier of the spin band of the metalline in the ferromagnetism source.Thereby last spin is from this Schottky barrier of spin band tunnelling of the metalline of ferromagnetism source 3a, is injected into the channel region of the semiconductor layer 1 under the gate insulating film.At this moment, for spin down, because the barrier height that has the spin band of the semiconductor property of ferromagnetism source 3a to cause is φ _n' the energy barrier, following spin is injected from non magnetic contact 3b hardly.Thereby the ferromagnetism source 3a that is formed by semimetal only injects upward spin selectively.

Be injected into going up in the raceway groove from being spun on V _DSEffect under be transported to the schottky barrier interface that ferromagnetism is leaked the 5a side.Leak 5a at ferromagnetism source 3a with ferromagnetism and have under the parallel magnetized situation, the spin of the spin band of the metalline of upward spin of being injected and ferromagnetism leakage 5a is parallel.Thereby the last spin that is injected among the ferromagnetism leakage 5a is subjected to the influence of spin-dependent scattering hardly and conducts the formation leakage current in ferromagnetism leakage 5a.Particularly, leak 5a at ferromagnetism source 3a with ferromagnetism and have the V that will produce determined a certain leakage current under the parallel magnetized situation _GSBe defined as V _T

On the other hand, shown in Fig. 6 (D), leak 5a in ferromagnetism source 3a and ferromagnetism and have under the situation of antiparallel magnetization, be injected into the spin antiparallel of spin band that spin and ferromagnetism are leaked the metalline of 5a that goes up in the raceway groove, parallel with the spin of the spin band of semiconductor property.Thereby the spin of going up that is injected in the raceway groove is leaked 5a with ferromagnetism to be felt as the barrier height is Δ E _CThe energy barrier.The last spin of this raceway groove can not tunnelling, can not cross this potential barrier by warm-up movement again, if select ferromagnetism to leak thickness and the Δ E of 5a _C, then almost can not leak 5a and conduct in ferromagnetism from the last spin of non magnetic source electrode 3b injection.Thereby, produce leakage current hardly.Thereby ferromagnetism is leaked semimetal among the 5a only makes the spin parallel with the spin of the spin band of metalline pass through, and antiparallel spin is passed through.

Can be injected into the raceway groove from the ferromagnetism source 3a spinning polarized electron that spin polarizability is high that constitutes by semimetal, in addition, the spin selection rate of leaking 5a owing to the ferromagnetism that is formed by semimetal is very big, so the relative magnetized state that leaks between the 5a in ferromagnetism source 3a and ferromagnetism is under the situation of antiparallel magnetization, compare with parallel magnetized situation, it is very little that leakage current becomes.Thereby, using under semimetallic situation, compare with the situation of using common ferromagnetism metal, can make the relative magnetized state that leaks 5a in ferromagnetism source 3a and ferromagnetism is parallel magnetized situation and the ratio of the leakage current separately of the situation of antiparallel magnetization becomes very big.

Then, to Fig. 7 (D), the operation principle that semimetal is used for the transoid n channel-type MISFET of ferromagnetism source and ferromagnetism leakage is described with reference to Fig. 7 (A).Below, the spin of the spin band of the metalline that belongs to ferromagnetism source 3a that will be formed by semimetal is decided to be spin, and the spin that will belong to the spin band of semiconductor property is decided to be spin down.

Fig. 7 (A) is the energy band diagram in the poised state, and is corresponding with Fig. 3 (B).At V _GSApplied V under=0 the state _DSSituation under, because semiconductor layer 1 is the p N-type semiconductor N, so if, then in MISFET, produce electric current from leaking the side injected hole, but the schottky junction that the spin band by semimetallic metalline among the ferromagnetism leakage 5a causes is reverse biased, and the injection in hole is suppressed.But, produced the electric current of the reverse saturation current degree of schottky junction, and passed through suitably selected φ _p, can reduce this electric current fully.

In addition, because the energy barrier φ that has the spin band of ferromagnetism leakage 5a to cause by semiconductor property _p', from leaking the non magnetic contact of side 5b, also can suppress the injection in hole.Thereby under the situation shown in Fig. 7 (B), MISFET becomes cut-off state.

If gate electrode is applied threshold value V _TAbove V _GS, then at gate insulating film/interface electronics of inducting, form inversion layer (thereby, for inversion channel type and accumulation channels type, V _TThe definition difference).At this moment, shown in Fig. 7 (C), at the place, junction interface separately that inversion layer and ferromagnetism source 3a and ferromagnetism are leaked 5a, having formed the barrier height that the spin band of semimetallic metalline causes is φ _nPotential barrier.

Pass through V _DSApply, the knot that ferromagnetism is leaked 5a and ferromagnetism source 3a be biased to shown in Fig. 7 (C) like that.If select fully big φ _p, φ then _n(=E _G-φ _p) reduce, will spin because of heat emission from the spin band of the metalline of ferromagnetism source 3a is injected into the raceway groove.In addition, inject and more to make φ carrying out hot electron never again than spinning from ferromagnetism source 3a _nUnder the situation about reducing, similarly also can inject with the accumulation channels type and will go up spin and be injected into raceway groove from the spin band of the metalline of ferromagnetism source 3a by the tunnel.On the other hand, because the semiconductor spin band of ferromagnetism source 3a is arranged, following spin is injected into hardly.

Be injected into going up in the raceway groove from being spun on V _DSEffect under be transported to the Lou junction interface of side.Leak 5a in ferromagnetism source 3a and ferromagnetism and have under the parallel magnetized situation, the spin that is injected into the spin band of going up the metalline among spin and the ferromagnetism leakage 5a in the raceway groove is parallel.Thereby the spin band conduction of the metalline of 5a is leaked in last spin through ferromagnetism, form leakage current.

Shown in Fig. 7 (D), have under the situation of antiparallel magnetization at ferromagnetism source 3a and ferromagnetism leakage 5a, be injected into the spin antiparallel of spin band that spin and ferromagnetism are leaked the metalline of 5a that goes up in the raceway groove, the spin of spin band of semiconductor property of leaking 5a with ferromagnetism is parallel.Thereby the spin of going up that is injected in the raceway groove is leaked 5a with ferromagnetism to be felt as the barrier height is Δ E _CThe energy barrier.The last spin of raceway groove can not tunnelling, and can not cross the barrier height by warm-up movement again is Δ E _CThe energy barrier, if selected ferromagnetism is leaked thickness and the Δ E of 5a _C, then produce the leakage current composition hardly.

Thereby, because ferromagnetism is leaked semimetal among the 5a spin parallel with the spin of the spin band of metalline passed through, so transefer conductance can be subjected to control with the relative magnetized state between the ferromagnetism leakage 5a at ferromagnetism source 3a.That is, have under the situation of antiparallel magnetization at ferromagnetism source 3a and ferromagnetism leakage 5a, compare with parallel magnetized situation, leakage current reduces.

Leak among the MISFET of (5 or 5a) having the ferromagnetism source that forms by above-mentioned ferromagnetism metal or semimetal (3 or 3a) and ferromagnetism, also semiconductor layer 1 can be replaced as unadulterated semiconductor or intrinsic semiconductor.At this moment, different at the ferromagnetism metal that is produced with barrier structure and Schottky barrier that semi-conductive knot place generates, and rely on this barrier structure, can expect the work of same MISFET.In this MISFET,,,, can expect big mobility for conduction carrier so there is not the influence of the impurity scattering in the channel region owing to constitute channel region with intrinsic semiconductor.Particularly, in the MISFET of the short channel of nanoscale, also can expect impact conduction to the effective charge carrier of high speed.In addition, in this MISFET, even with high density with atomic refinement the integrated situation of the MISFET of low threshold value under, also have the advantage that the dispersiveness of threshold value does not take place in itself.In addition, the raceway groove that is made of intrinsic semiconductor also is suitable for soi structure.Thereby,, can make MISFET of the present invention and use the performance of its nonvolatile memory (back will be addressed) to be further enhanced by intrinsic semiconductor is used for channel region.

Then, describe with reference to the MISFET of accompanying drawing the 3rd execution mode of the present invention.In the MISFET of present embodiment, ferromagnetism source and ferromagnetism are leaked and are formed with the thin metal level of desirable barrier height and the schottky junction of semiconductor layer, form ferromagnetism metal or semimetal on this metal level.Figure 12 is the energy band diagram of structure example that the MISFET of present embodiment is shown.As shown in figure 12, the MISFET of present embodiment has respectively ferromagnetism metal 23 and 25 is used for source and leakage, imports to be used to control the thin metal level 23a of barrier height, the structure of 25a on the interface separately of semiconductor layer 21 and ferromagnetism metal 23 and 25.At first form and obtain metal 23a, the 25a of desirable barrier height φ n and the schottky junction of semiconductor layer 21, on this metal level 23a, 25a, form ferromagnetism metal level 23,25 more respectively.As the concrete material of this metal level 23a, 25a, under with the situation of Si, consider to adopt ErSix, PtSi as semiconductor layer 21 _xDeng silicide.

Have again, even adopt above-mentioned each ferromagnetism metal level 23,25 is replaced as the semimetallic structure that illustrated in the 2nd execution mode, promptly have the MISFET that semimetallic ferromagnetism source and ferromagnetism are leaked, also can similarly control schottky barrier height with the structure of Figure 12.About this structure, also included category of the present invention in.Perhaps, also can be at the interface at ferromagnetism metal or semimetal and semiconductor layer, and ferromagnetism metal or semimetal between insert other semiconductor that can obtain desirable schottky barrier height.Perhaps, in order to control schottky barrier height, also can be in the insertion metal/semiconductor heterostructure at the interface of ferromagnetism metal or semimetal and semiconductor layer.

By taking above method, can freely select the material of ferromagnetism source and ferromagnetism leakage, and needn't consider the schottky barrier height between semiconductor layer and ferromagnetism metal or the semimetal.

Then, describe with reference to the MISFET of accompanying drawing the 4th execution mode of the present invention.In above-mentioned the 1st to the 3rd execution mode, although understand the MISFET that adopts ferromagnetism metal or semimetallic schottky junction to leak with formation ferromagnetism source and ferromagnetism, but the MISFET of present embodiment has the structure that the ferromagnetism semiconductor is used for ferromagnetism source and ferromagnetism leakage.So, even do not adopt schottky junction, also can expect to obtain the characteristic same with the MISFET of the 1st to the 3rd execution mode.

For example, shown in Figure 13 (A), adopting intrinsic semiconductor 31 as channel region, have among the MISFET of stacked gate insulator 41 and the structure of grid (electrode) 37 on intrinsic semiconductor 31, as long as ferromagnetism source 33 and ferromagnetism are leaked the 35 ferromagnetism semiconductors that are decided to be the n type, then can constitute the n raceway groove MISFET that can expect with the same characteristic of above-mentioned MISFET (for example Fig. 2 (A)).Have again, under the situation that forms p raceway groove MISFET, as long as ferromagnetism source and ferromagnetism leakage are decided to be p type ferromagnetism semiconductor.

Then, describe with reference to the MISFET of accompanying drawing the 5th execution mode of the present invention.In the MISFET of present embodiment, adopt ferromagnetism semiconductor and semi-conductive pn knot to leak (in this situation, MISFET is as the work of inversion channel type) to constitute ferromagnetism source and ferromagnetism.For example, shown in Figure 13 (B), as long as n type ferromagnetism semiconductor is used for source 53 or leaks 55, the semiconductor layer 51 that will comprise channel region is decided to be the p N-type semiconductor N and gets final product.In this case, at p type semiconductor layer 51 upper strata stacked gate insulation films 61 and grid (electrode) 57.Similarly, p type ferromagnetism semiconductor is used for source or leakage, channel region is decided to be the n N-type semiconductor N gets final product

As illustrating in the of the present invention the 4th or the 5th execution mode, even under the situation that constitutes the leakage of ferromagnetism source and ferromagnetism by the ferromagnetism semiconductor, because the spin-dependent scattering in leaking, leakage current is to be different under the situation of parallel magnetization and antiparallel magnetization in the source with leaking.In addition, as long as channel length below the mean free path to energy relaxation of charge carrier, according to the impact conduction of charge carrier, can obtain and the similar spin correlation conduction of tunnel magneto-resistance effect, in this case, can increase the variation of the transefer conductance in parallel magnetization and the antiparallel magnetization.

As the ferromagnetism semiconductor of the MISFET that is used for the 4th and the 5th execution mode, consider to Si, Ge, Si _xGe _1-x, mix the ferromagnetism semiconductor of transition metals such as Mn or Cr or rare earth element in the semiconductor such as SiC.

The output characteristic example of the MISFET of the respective embodiments described above then, is described.Fig. 8 illustrates with V _GsLeakage current I for parameter _DWith V _DSThe figure of dependence.In the MISFET of present embodiment, even ferromagnetism metal or semimetallic any ferromagnetism source 3 and ferromagnetism of being used for are being leaked under 5 the situation, even and under any situation in inversion channel type and accumulation channels type, at a certain threshold value V that gate electrode 7 is applied by the device architecture decision _TDuring following voltage, MISFET also is in cut-off state.This relative magnetized state with ferromagnetism source 3 and ferromagnetism leakage 5 is irrelevant.

As long as gate electrode 7 is applied voltage V more than the threshold value ₁(＞V _T), just can make transistor be in conducting state.At this moment, ferromagnetism source 3 and ferromagnetism are leaked the leakage current I that generates between 5 _DThe size relative magnetized state that leaks 5 pairs of ferromagnetism sources 3 because of ferromagnetism different.That is, even under same bias voltage, under parallel magnetized situation, leakage current I _D(the I among the figure greatly _D↑ ↑), under the situation of antiparallel magnetization, leakage current I _DLittle (ID among the figure ↑ ↓).Describe this feature if say it in another way, be exactly and leak transefer conductance (mutual conductance) equivalence of controlling MISFET under the magnetized state between 5 with ferromagnetism in ferromagnetism source 3.Therefore, in the MISFET of present embodiment, leakage current I _DCan be put on the voltage control on the gate electrode 7, meanwhile, also have concurrently and depend on the transefer conductance that ferromagnetism is leaked the relative magnetized state in 5 pairs of ferromagnetism sources 3.

In the ferromagnetism body, apply the magnetic field more than the coercive force only otherwise from the outside, just can keep magnetized direction.Therefore, in the MISFET of present embodiment, carry out parallel magnetization or antiparallel magnetization, can store the information of 2 values by the relative magnetized state that ferromagnetism source and ferromagnetism are leaked.

In addition, as mentioned above, above-mentioned MISFET is according to the size of leakage current or the size of transefer conductance, can detect ferromagnetism source and the ferromagnetism relative magnetized state between leaking with electrical method.Thereby for above-mentioned MISFET, available 1 MISFET constitutes 1 bit non-volatile memory cell.

Fig. 9 (a) is the figure of a structure example of the memory circuit of the expression MISFET that used present embodiment.In the memory circuit shown in Fig. 9 (a), a plurality of MISFET are configured to rectangular, with source terminal S ground connection, drain terminal D and gate terminal G are connected with reading with word line WL with reading with bit line BL respectively.In addition, rewriting being used word line become under the state at electric insulation on the above-mentioned MISFET with bit line configuration with rewriting intersects with other wiring.Also can be also used as above-mentioned read with bit line BL with word line and rewriting with bit line as this rewriting and use word line WL with reading.Fig. 9 (a) is the figure of the cellular construction under the expression dual-purpose situation.Under the situation of Fig. 9 (a), available single MISFET constitutes memory cell, also forms very simple structure simultaneously with regard to wiring.

The memory cell of the MRAM of existing structure has the structure of 1 MTJ, 1 MISFET and 4 wirings (with reference to Figure 10), and because of MTJ with rewrite existence with word line, common source but is difficult to take with the measure that reduces cellar area etc. in adjacent unit.To this, in the memory cell of present embodiment, shown in Fig. 9 (a), because with having only the simplest structure of 1 MISFET and 3 wirings can constitute memory cell, so can easily constitute the layout that is suitable for miniaturization.

For example, the shared structure in ferromagnetism source that forms the MISFET of 2 present embodiments with 1 ferromagnetism source also is possible.Figure 11 is the figure of cross-section structure example that expression has the memory cell of common source structure.Memory cell structure shown in Figure 11 has 1MISFET and the 2MISFET that adjoins each other, connect the 1st bit line BL1 that the word line WL of the gate electrode G1 of 1MISFET and the gate electrode G2 of 2MISFET, the 1st ferromagnetism that is connected 1MISFET leak D1 jointly, connect the 2nd ferromagnetism leak the 2nd bit line BL2 of D2, to the 1st and the common ferromagnetism source S of 2MISFET and with the wiring of its ground connection.When adopting said structure,, formed the cellular construction that is more suitable in densification because the source is shared.

Below, the work of memory cell is described with Fig. 9 (a).With bit line and rewriting/read situation, only be called bit line BL and word line WL as shared above-mentioned rewriting respectively/read with word line.The rewriting of information can be leaked 5 confining force by ferromagnetism source 3 among the MISFET that changes present embodiment or ferromagnetism, or fixes a side the direction of magnetization and make the relative direction of magnetization that ferromagnetism is leaked 5 pairs of ferromagnetism sources 3 form parallel magnetization or antiparallel magnetization is carried out.For example, make the magnetized state of parallel magnetization or antiparallel magnetization corresponding with the information of 2 values of " 0 " or " 1 ".Specifically, flow through electric current among bit line BL that on selected memory cell, intersects and the word line WL, make by the little ferromagnetism body of the confining force of the memory cell selected by the resultant magnetic field in the magnetic field of the current-induced that flows through wiring separately or the magnetization inversion of the unfixed ferromagnetism body of the direction of magnetization and come stored information.At this moment, because magnetization inversion does not take place the non-selected cell that is connected with bit line BL or word line WL identical with selected unit,, make and use only from the unlikely generation magnetization inversion in the magnetic field of a wiring so preestablish the current value that flows through wiring separately.

Reading of information is by the word line WL that is connected with selected cell being applied after the MISFET conducting that voltage makes present embodiment, and pairs of bit line BL applies drain voltage to detect leakage current I _DSize carry out.In the MISFET of present embodiment, the relative magnetized state that leaks with ferromagnetism in the ferromagnetism source is that transefer conductance is bigger under the parallel magnetized situation, generates big leakage current I _D, and under the situation of antiparallel magnetization, transefer conductance is less, leakage current I _DAlso little.Thereby, according to I _DBig I detect the relative magnetized state that ferromagnetism source and ferromagnetism are leaked.In addition, also can detect even apply required bias voltage by precharge.

In common MTJ, electric current in the parallel magnetization is generated by the tunnel between the state density of tunnel between the state density of the spin of the majority in two powers' magnetic pole and minority spin, under the situation of antiparallel magnetization, tunnel from the state density of minority spin to the state density of majority spin and the tunnel from the state density of majority spin to the state density of minority spin generate.Thereby, owing to comprise the electric current composition of minority spin in the electric current that under the situation of parallel magnetization and antiparallel magnetization, is flow through, so the ratio of the electric current under the situation separately of parallel magnetization and antiparallel magnetization is not allowed to be easy to do greatly.

On the other hand, the MISFET that semimetal is used for the leakage of ferromagnetism source and ferromagnetism in present embodiment, rely on the knot of semimetal and semiconductor layer, one side's the spin that can only will belong to the spin band of metalline in the ferromagnetism source is injected in the raceway groove, and then can in leaking, ferromagnetism only the spin parallel with the spin of the spin band that belongs to metalline be taken out from raceway groove, form leakage current (below, should semimetallic effect be called " spin filtering effect ").

Thereby, present embodiment semimetal is used for the MISFET that ferromagnetism source and ferromagnetism are leaked, the current ratio in the situation of the ratio of the electric current in the situation separately of parallel magnetization and antiparallel magnetization (leakage current than) and MTJ is compared and can be increased.Thereby, as long as adopt the MISFET of present embodiment, in above-mentioned memory circuit, can easily detect magnetized state.

In addition, even under the situation that constitutes ferromagnetism source and ferromagnetism leakage with the ferromagnetism metal, the high-field effect that utilization takes place in the source Schottky barrier under the gate bias effect has the possibility more than the spin polarizability that the spin polarizability (spin injection efficiency) of the charge carrier that injects from the ferromagnetism source can be increased to the ferromagnetism metal.As long as use this effect, just have the ratio of the leakage current in the situation separately of parallel magnetization and antiparallel magnetization to compare the possibility that can increase with the current ratio among the MTJ.

In addition, because TMR sharply reduces than with bias voltage in MTJ, so under the required bias voltage of circuit, TMR is also arranged than the problem that significantly reduces.In contrast, in the MISFET of present embodiment, owing to utilized spin-dependent scattering or semimetallic spin filtering effect of ferromagnetism metal, so on principle, there is not the such bias-dependent of MTJ.Thereby, under the required bias voltage of circuit, can realize big leakage current ratio.

Fig. 9 (b) is that the bit line end of the memory circuit shown in Fig. 9 (a) is lead-out terminal V _O, from this lead-out terminal V _OBranch is through load R _LWith supply voltage V _DDThe memory circuit that connects.The working point of the static characteristic of the memory cell shown in Fig. 9 (b) has been shown in Fig. 9 (c).Herein, though adopt pure resistance, adopt transistorized active load also can as load.Shown in Fig. 9 (c), the gate electrode that needs only MISFET when information is read applies gate voltage V _CS, through load resistance R _LPairs of bit line BL applies supply voltage V _DD, load resistance R _LThe working point just according to moving the output signal V under the situation of parallel magnetization and antiparallel magnetization along the load line among Fig. 9 (c) with magnetized state between the ferromagnetism leakage in the ferromagnetism source _OBe respectively the V among the figure _O↑ ↑ and V _O↑ ↓.The absolute value of each output signal and ratio (V _OThe V of ↑ ↑/ _O↑ ↓) can be utilized R _L, V _DDParameter Deng external circuit is optimized.For example, by adjusting the slope (reducing at this moment) of load line, even compare I at leakage current _DThe I of ↑ ↑/ _DAlso can obtain big output signal ratio under the situation of ↑ ↓ little.Thereby, in the memory circuit of present embodiment, the advantage of the output signal that can access desirable size is arranged.

More than, as illustrating, according to possessing of embodiments of the present invention the MISFET that leaks of ferromagnetism source and ferromagnetism, in the transistorized function that possesses as available gate voltage control leakage current, also have concurrently and can control the so distinctive characteristic of its transefer conductance (mutual conductance) by the relative direction of magnetization that ferromagnetism source and ferromagnetism are leaked.Even the relative direction of magnetization between ferromagnetism source and ferromagnetism are leaked has so-called non-volatile character that energize not also can keep former state.Thereby, utilize this relative direction of magnetization also can store the information of 2 values non-volatilely.And then, as long as adopt above-mentioned transfer characteristic, can detect this relative direction of magnetization with electrical way.That is, above-mentioned MISFET only can constitute 1 bit non-volatile memory cell with 1 transistor.Thereby,, improve such advantage so have the speed and the integrated level that can make non-volatile memory owing to, can make the structure of non-volatile memory cells simply as long as adopt the MISFET of present embodiment.

More than, though be illustrated along embodiments of the present invention, the present invention is not limited thereto.In addition, can carry out various changes, improvement, combination, these personnel to the industry are self-explantory.Self-evident, for example, in the memory element that any MISFET that illustrated in this specification also can be applicable to illustrate in this specification, the memory circuit.

Utilizability on the industry

According to possessing ferromagnetism source and the strong magnetic that has adopted ferromagnetism metal or semimetallic schottky junction The property leakage MISFET of the present invention, utilize ferromagnetism to leak the relative direction of magnetization to the ferromagnetism source, Can store the information of 2 values, available electrical way detects this relative direction of magnetization simultaneously. Thereby, Owing to as long as adopt above-mentioned MISFET, only can consist of the storage of 1 bit non-volatile with 1 transistor The unit is so can realize the non-volatile memory of high speed and high density of integration.

Claims

1. transistor is characterized in that having:

The source that constitutes by the ferromagnetism body (below, be called " ferromagnetism source "), its inject spin polarization conduction carrier (below, be called " spin polarization conduction carrier ");

The leakage that constitutes by the ferromagnetism body (below, be called " ferromagnetism leakage "), the spin polarization conduction carrier that it has accepted to inject from this ferromagnetism source;

Semiconductor layer, it is provided with between above-mentioned ferromagnetism source and the leakage of above-mentioned ferromagnetism, forms the schottky junction with Schottky barrier at the place, junction interface separately of above-mentioned ferromagnetism source and the leakage of above-mentioned ferromagnetism; And

Gate electrode to above-mentioned semiconductor layer formation.

2. transistor as claimed in claim 1 is characterized in that,

By the direction of magnetization counter-rotating that above-mentioned ferromagnetism source or above-mentioned ferromagnetism are leaked, above-mentioned ferromagnetism can be leaked the relative direction of magnetization to above-mentioned ferromagnetism source be controlled to be equidirectional (below, be called " parallel magnetization ") or rightabout (below, be called " antiparallel magnetization ").

3. transistor as claimed in claim 1 or 2 is characterized in that,

Above-mentioned ferromagnetism source and above-mentioned ferromagnetism are leaked and are formed by the ferromagnetism metal.

4. as any described transistor in the claim 1 to 3, it is characterized in that,

The conduction type of the above-mentioned spin polarization conduction carrier situation identical with above-mentioned semiconductor layer (below, be called " accumulation channels type ") under, when above-mentioned spin polarization conduction carrier is electronics, above-mentioned Schottky barrier produces in the conduction band side, when above-mentioned spin polarization conduction carrier was the hole, above-mentioned Schottky barrier produced in the valence band side.

5. as any described transistor in the claim 1 to 3, it is characterized in that,

The conduction type of the above-mentioned spin polarization conduction carrier situation different with above-mentioned semiconductor layer (below, be called " inversion channel type ") in above-mentioned semiconductor layer, do not form under the situation of inversion layer, when above-mentioned spin polarization conduction carrier is electronics, above-mentioned Schottky barrier produces in the valence band side, when above-mentioned spin polarization conduction carrier was the hole, above-mentioned Schottky barrier produced in the conduction band side.

6. transistor as claimed in claim 4 is characterized in that,

Do not apply under the state of voltage between above-mentioned gate electrode in above-mentioned accumulation channels type and the above-mentioned ferromagnetism source, above-mentioned spin polarization conduction carrier is subjected to above-mentioned Schottky barrier inhibition to injection of the tunnel of above-mentioned semiconductor layer and heat emission injection.

7. as claim 4 or 6 described transistors, it is characterized in that,

For above-mentioned accumulation channels type, by above-mentioned gate electrode is applied voltage, the above-mentioned spin polarization conduction carrier in above-mentioned ferromagnetism source injects to above-mentioned semiconductor layer by the above-mentioned Schottky barrier at the interface of tunnelling above-mentioned ferromagnetism source and above-mentioned semiconductor layer.

8. transistor as claimed in claim 4 is characterized in that,

Not above-mentioned gate electrode is not applied under the state of voltage in above-mentioned accumulation channels type, though injecting to the heat emission of above-mentioned semiconductor layer, above-mentioned spin polarization conduction carrier is subjected to above-mentioned Schottky barrier inhibition, but the above-mentioned spin polarization conduction carrier in above-mentioned ferromagnetism source injects to above-mentioned semiconductor layer by the above-mentioned Schottky barrier of tunnelling.

9. as claim 4 or 8 described transistors, it is characterized in that,

For above-mentioned accumulation channels type, by above-mentioned gate electrode is applied voltage, the above-mentioned spin polarization conduction carrier in above-mentioned ferromagnetism source is according to the above-mentioned Schottky barrier at the interface of tunnelling above-mentioned ferromagnetism source and above-mentioned semiconductor layer, the electric current that may command above-mentioned ferromagnetism source and above-mentioned ferromagnetism are produced between leaking.

10. transistor as claimed in claim 5 is characterized in that,

Not applying under the state of voltage between above-mentioned gate electrode and above-mentioned ferromagnetism source in above-mentioned inversion channel type, above-mentioned spin polarization conduction carrier is subjected to above-mentioned Schottky barrier inhibition to injection of the tunnel of above-mentioned semiconductor layer and heat emission injection.

11. as claim 5 or 10 described transistors, it is characterized in that,

For above-mentioned inversion channel type, the voltage that utilization applies above-mentioned gate electrode and in above-mentioned semiconductor layer, having formed under the situation of inversion layer, the above-mentioned spin polarization conduction carrier in above-mentioned ferromagnetism source is injected in the above-mentioned semiconductor layer by at least one side in heat emission or tunnel.

12. transistor as claimed in claim 5 is characterized in that,

Not even above-mentioned gate electrode is not applied under the state of voltage in above-mentioned inversion channel type, in above-mentioned semiconductor layer, also form inversion layer, the above-mentioned spin polarization conduction carrier in above-mentioned ferromagnetism source is injected in the above-mentioned semiconductor layer by at least one side in heat emission or tunnel.

13. as claim 5 or 12 described transistors, it is characterized in that,

For above-mentioned inversion channel type, the voltage that utilization applies above-mentioned gate electrode, at least one side by heat emission or tunnel is injected into the above-mentioned semiconductor layer the above-mentioned spin polarization conduction carrier basis in above-mentioned ferromagnetism source from above-mentioned ferromagnetism source, the electric current that may command above-mentioned ferromagnetism source and above-mentioned ferromagnetism are produced between leaking.

14. any described transistor as in the claim 4 to 13 is characterized in that,

For above-mentioned accumulation channels type or above-mentioned inversion channel type, be injected into the spin polarizability in Fermi's energy that above-mentioned spin polarization conduction carrier in the above-mentioned semiconductor layer depends on above-mentioned ferromagnetism source and carry out spin polarization.

15. any described transistor as in the claim 4 to 14 is characterized in that,

For above-mentioned accumulation channels type or above-mentioned inversion channel type,

The relative magnetized state that leaks with above-mentioned ferromagnetism in above-mentioned ferromagnetism source is under the parallel magnetized situation, the resistance that causes because of spin-dependent scattering that the above-mentioned ferromagnetism of the above-mentioned spin polarization conduction carrier that has injected from above-mentioned ferromagnetism source is leaked reduces, the relative direction of magnetization of leaking with above-mentioned ferromagnetism in above-mentioned ferromagnetism source is under the situation of antiparallel magnetization, and the resistance that causes because of spin-dependent scattering during the above-mentioned ferromagnetism of above-mentioned spin polarization conduction carrier is leaked increases.

16. any described transistor as in the claim 1 to 15 is characterized in that,

Under same bias voltage, the relative direction of magnetization control transefer conductance that can utilize above-mentioned ferromagnetism source and above-mentioned ferromagnetism to leak.

17. any described transistor as in the claim 4 to 16 is characterized in that,

For above-mentioned accumulation channels type or above-mentioned inversion channel type, have under the parallel magnetized situation with above-mentioned ferromagnetism leakage in above-mentioned ferromagnetism source, have the threshold value that is defined as following gate voltage: utilize certain voltage that above-mentioned gate electrode is applied between above-mentioned ferromagnetism source and the leakage of above-mentioned ferromagnetism, to produce certain electric current of determining.

18. a transistor is characterized in that having:

The ferromagnetism source, be the ferromagnetism body, its by the band structure of a side spin being got metalline (below, be called " spin band of metalline "), to the opposing party's spin get band structure semiconductor property or insulator character (below, be called " spin band of semiconductor property ") semimetal constitute, inject spin polarization conduction carrier;

Ferromagnetism is leaked, the spin polarization that it has accepted to inject from this ferromagnetism source above-mentioned conduction carrier;

Semiconductor layer, it is provided with, combines each above-mentioned ferromagnetism source and the leakage of above-mentioned ferromagnetism between above-mentioned ferromagnetism source and the leakage of above-mentioned ferromagnetism; And

Gate electrode to above-mentioned semiconductor layer formation.

19. transistor as claimed in claim 18 is characterized in that,

Above-mentioned ferromagnetism source and above-mentioned ferromagnetism are leaked and are formed schottky junction, the spin band of the metalline of above-mentioned schottky junction in above-mentioned semimetal and above-mentioned semiconductor layer have Schottky barrier at the interface.

20. as claim 18 or 19 described transistors, it is characterized in that,

The conduction type of the above-mentioned conduction carrier situation identical with above-mentioned semiconductor layer (below, be called " accumulation channels type ") under, when above-mentioned conduction carrier is electronics, the above-mentioned Schottky barrier that is caused by the spin band of above-mentioned metalline produces in the conduction band side, when above-mentioned conduction carrier was the hole, the above-mentioned Schottky barrier that is caused by the spin band of above-mentioned metalline produced in the valence band side.

21. as claim 18 or 19 described transistors, it is characterized in that,

The conduction type of the above-mentioned conduction carrier situation different with above-mentioned semiconductor layer (below, be called " inversion channel type ") in above-mentioned semiconductor layer, do not form under the situation of inversion layer, when above-mentioned conduction carrier is electronics, above-mentioned Schottky barrier produces in the valence band side, when above-mentioned conduction carrier was the hole, above-mentioned Schottky barrier produced in the conduction band side.

22. as claim 18 or 19 described transistors, it is characterized in that,

At the knot place of above-mentioned ferromagnetism source and leakage of above-mentioned ferromagnetism and above-mentioned semiconductor layer, the band gap of the spin band of above-mentioned semimetallic semiconductor property is bigger than the band gap of above-mentioned semiconductor layer.

23. as claim 18 or 19 described transistors, it is characterized in that,

Knot place at above-mentioned ferromagnetism source and leakage of above-mentioned ferromagnetism and above-mentioned semiconductor layer, the spin band of the semiconductor property in the above-mentioned semimetal forms the energy barrier to above-mentioned semiconductor layer, when above-mentioned conduction carrier is electronics, at least at conduction band side produce power barrier, when above-mentioned conduction carrier is the hole, at least at valence band side produce power barrier.

24. any described transistor as in the claim 18 to 23 is characterized in that,

And then, above-mentioned ferromagnetism source and above-mentioned ferromagnetism are leaked, form the contact that constitutes by nonmagnetic metal or non-magnetic conductor (below, be called " non magnetic contact ") respectively.

25. transistor as claimed in claim 24 is characterized in that,

Above-mentioned non magnetic contact forms intermetallic knot or ohm knot to the spin band of above-mentioned metalline, to the spin band of above-mentioned semiconductor property, the spin band of semiconductor property becomes between the metal of energy barrier and semiconductor or the junction structure between metal and insulator.

26. transistor as claimed in claim 20 is characterized in that,

Not applying under the state of voltage between above-mentioned gate electrode and above-mentioned ferromagnetism source in above-mentioned accumulation channels type, the above-mentioned conduction carrier of the spin band of above-mentioned metalline injects and heat emission is injected and is subjected to the Schottky barrier inhibition that the spin band by above-mentioned metalline causes to the tunnel of above-mentioned semiconductor layer.

27. as claim 20 or 26 described transistors, it is characterized in that,

For above-mentioned accumulation channels type,

By above-mentioned gate electrode is applied voltage, the conduction carrier of the spin band of the above-mentioned metalline in the above-mentioned ferromagnetism source is injected in the semiconductor layer by the above-mentioned Schottky barrier at the interface of tunnelling above-mentioned ferromagnetism source and above-mentioned semiconductor layer.

28. transistor as claimed in claim 20 is characterized in that,

Not above-mentioned gate electrode is not applied under the state of voltage in above-mentioned accumulation channels type, though injecting to the heat emission of above-mentioned semiconductor layer, the above-mentioned conduction carrier of the spin band of above-mentioned metalline is subjected to above-mentioned Schottky barrier inhibition, but the conduction carrier of the spin band of the above-mentioned metalline in the above-mentioned ferromagnetism source injects to above-mentioned semiconductor layer by the above-mentioned Schottky barrier of tunnelling.

29. as claim 20 or 28 described transistors, it is characterized in that,

For above-mentioned accumulation channels type, the voltage that utilization applies gate electrode, the conduction carrier of the spin band of the metalline in the above-mentioned ferromagnetism source is according to the above-mentioned Schottky barrier at the interface of tunnelling above-mentioned ferromagnetism source and above-mentioned semiconductor layer, the electric current that may command above-mentioned ferromagnetism source and above-mentioned ferromagnetism are produced between leaking.

30. transistor as claimed in claim 20 is characterized in that,

For above-mentioned accumulation channels type, inject and the spin band that is subjected to by above-mentioned semiconductor property causes the above-mentioned non magnetic above-mentioned energy barrier that contacts is suppressed injected in heat emission to the tunnel of above-mentioned semiconductor layer from the conduction carrier above-mentioned non magnetic contact that above-mentioned ferromagnetism source is formed, that have the spin parallel with the spin band of above-mentioned semiconductor property in the above-mentioned ferromagnetism source.

31. transistor as claimed in claim 21 is characterized in that,

Not applying under the state of voltage between above-mentioned gate electrode and above-mentioned ferromagnetism source in above-mentioned inversion channel type, the above-mentioned conduction carrier of the spin band of above-mentioned metalline is subjected to above-mentioned Schottky barrier inhibition to injection of the tunnel of above-mentioned semiconductor layer and heat emission injection.

32. as claim 21 or 31 described transistors, it is characterized in that,

For above-mentioned inversion channel type,

Utilization applies voltage to above-mentioned gate electrode and has formed in above-mentioned semiconductor layer under the situation of inversion layer, the conduction carrier of the spin band of the above-mentioned metalline in the above-mentioned ferromagnetism source is injected in the above-mentioned semiconductor layer from least one side of above-mentioned ferromagnetism source by heat emission or tunnel.

33. transistor as claimed in claim 21 is characterized in that,

Not even above-mentioned gate electrode is not applied under the state of voltage in above-mentioned inversion channel type, in above-mentioned semiconductor layer, also form inversion layer, the above-mentioned conduction carrier of the spin band of the above-mentioned metalline in the above-mentioned ferromagnetism source is injected in the above-mentioned semiconductor layer by at least one side in heat emission or tunnel.

34. as claim 21 or 33 described transistors, it is characterized in that,

For above-mentioned inversion channel type,

The voltage that utilization applies above-mentioned gate electrode, the conduction carrier of the spin band of the above-mentioned metalline in the above-mentioned ferromagnetism source is injected into the above-mentioned semiconductor layer from above-mentioned ferromagnetism source by at least one side in heat emission or tunnel, the electric current that may command above-mentioned ferromagnetism source and above-mentioned ferromagnetism are produced between leaking.

35. transistor as claimed in claim 21 is characterized in that,

For above-mentioned inversion channel type, inject and the spin band that is subjected to by above-mentioned semiconductor property causes the above-mentioned non magnetic above-mentioned energy barrier that contacts is suppressed injected in heat emission to the tunnel of above-mentioned semiconductor layer from the conduction carrier above-mentioned non magnetic contact that above-mentioned ferromagnetism source is formed, that have the spin parallel with the spin band of above-mentioned semiconductor property in the above-mentioned ferromagnetism source.

36. as claim 20 or 21 described transistors, it is characterized in that,

The barrier height that can cause with the energy gap of the spin band of the above-mentioned semiconductor property in the above-mentioned ferromagnetism source or from the spin band by the semiconductor property in above-mentioned ferromagnetism source that above-mentioned non magnetic contact is seen or the thickness in above-mentioned ferromagnetism source control with the conduction carrier of the spin with side who injects from the spin band of the above-mentioned metalline in above-mentioned ferromagnetism source to above-mentioned semiconductor layer with have from the existence of the conduction carrier of the above-mentioned non magnetic spin that contacts the opposing party who injects to above-mentioned semiconductor layer through the spin band of the above-mentioned semiconductor property in above-mentioned ferromagnetism source that above-mentioned ferromagnetism source the is formed spin polarizability than the conduction carrier of decision.

37. any described transistor as in the claim 20 to 36 is characterized in that,

The relative magnetized state that leaks with above-mentioned ferromagnetism in above-mentioned ferromagnetism source is under the parallel magnetized situation, the spin band of the above-mentioned metalline that the conduction carrier that injects to above-mentioned semiconductor layer from the spin band of the above-mentioned metalline in above-mentioned ferromagnetism source can leak in above-mentioned ferromagnetism conducts

The relative magnetized state that leaks with above-mentioned ferromagnetism in above-mentioned ferromagnetism source is under the situation of antiparallel magnetization, and the conduction of the above-mentioned conduction carrier that injects to above-mentioned semiconductor layer from the spin band of the above-mentioned metalline in above-mentioned ferromagnetism source is subjected to the energy barrier that the spin band of the above-mentioned semiconductor property that leaked by above-mentioned ferromagnetism causes and suppresses.

38. any described transistor as in the claim 20 to 37 is characterized in that,

Have under the parallel magnetized situation with above-mentioned ferromagnetism leakage in above-mentioned ferromagnetism source, have the threshold value that is defined as following gate voltage: utilize certain voltage that gate electrode is applied between above-mentioned ferromagnetism source and the leakage of above-mentioned ferromagnetism, to produce certain electric current of determining.

39. any described transistor as in the claim 18 to 38 is characterized in that,

40. any described transistor as in the claim 1 to 39 is characterized in that,

Above-mentioned ferromagnetism source and above-mentioned ferromagnetism are leaked by growth or deposit on above-mentioned semiconductor layer and are formed.

41. any described transistor as in the claim 1 to 39 is characterized in that,

Above-mentioned ferromagnetism source and above-mentioned ferromagnetism are leaked by import magnetic element in above-mentioned semiconductor layer and are formed.

42. a memory element is characterized in that,

Adopt any one described 1 transistor in the claim 1 to 41, utilize the relative direction of magnetization stored information of above-mentioned ferromagnetism leakage to above-mentioned ferromagnetism source, according to depending on the transistorized transefer conductance of above-mentioned ferromagnetism source, detect the information that is stored in the above-mentioned transistor with the relative direction of magnetization of above-mentioned ferromagnetism leakage.

43. a memory element is characterized in that having:

Any one described 1 transistor in the claim 1 to 41;

The 1st wiring, it is connected with above-mentioned gate electrode;

The 2nd wiring, it leaks with above-mentioned ferromagnetism and is connected; And

The 3rd wiring, it is with above-mentioned ferromagnetism source ground connection.

44. a memory element is characterized in that having:

Any one described 1 transistor in the claim 1 to 41;

The 1st wiring, it is connected with above-mentioned gate electrode;

The 2nd wiring, it leaks with above-mentioned ferromagnetism and is connected;

The 3rd wiring, it is with above-mentioned ferromagnetism source ground connection;

Lead-out terminal, its end in above-mentioned the 2nd wiring forms; And

The 4th wiring, it is connected with power supply through load from above-mentioned the 2nd wiring branch.

45. as claim 43 or 44 described memory elements, it is characterized in that,

Also have the 1st other wiring and the 2nd other wiring that under the state of mutually insulated on the electricity, intersects on the above-mentioned transistor or near it.

46. as claim 43 or 44 described memory elements, it is characterized in that,

Available above-mentioned the 1st wiring and above-mentioned the 2nd wiring, perhaps, above-mentioned the 1st the wiring or above-mentioned the 2nd the wiring in either party replace the above-mentioned the 1st other wiring and the above-mentioned the 2nd other the wiring, perhaps, the above-mentioned the 1st other wiring or the above-mentioned the 2nd other the wiring in either party.

47. as claim 45 or 46 described memory elements, it is characterized in that,

By the above-mentioned the 1st other the wiring and the above-mentioned the 2nd other wiring, their above-mentioned the 1st wiring and above-mentioned the 2nd wiring have perhaps been replaced, perhaps replaced the above-mentioned the 1st other wiring or the above-mentioned the 2nd other the wiring in either party above-mentioned the 1st the wiring or above-mentioned the 2nd the wiring, and be not replaced as they a side the above-mentioned the 1st other wiring or the above-mentioned the 2nd other the wiring in flow through electric current, utilize the magnetic field of inducting thus, the magnetization inversion that above-mentioned ferromagnetism source or above-mentioned ferromagnetism are leaked, relative magnetized state between making above-mentioned ferromagnetism source and above-mentioned ferromagnetism being leaked changes, thus the rewriting of the information of carrying out.

48. any described memory element as in the claim 43 to 47 is characterized in that,

Have under the parallel magnetized situation with above-mentioned ferromagnetism leakage in above-mentioned ferromagnetism source, above-mentioned the 1st wiring is applied big voltage more than or equal to above-mentioned threshold value, according to the size of the leakage current in the above-mentioned transistor of the situation that between above-mentioned ferromagnetism source and the leakage of above-mentioned ferromagnetism, has applied the bias voltage of stipulating, carry out reading of information.

49. any described memory element as in the claim 44 to 47 is characterized in that,

Have under the parallel magnetized situation with above-mentioned ferromagnetism leakage in above-mentioned ferromagnetism source, through above-mentioned the 1st wiring above-mentioned gate electrode is applied the voltage bigger than threshold value, according to voltage drop by the above-mentioned load of the leakage current generating in the above-mentioned transistor at this moment, utilize resulting output voltage, carry out reading of information.

50. a memory circuit is characterized in that having:

Any described transistor in the claim 1 to 41, it is configured to rectangular;

The 1st wiring, it is respectively with above-mentioned ferromagnetism source ground connection;

Many word lines, its common a plurality of above-mentioned transistorized gate electrode separately of arranging along column direction that connects; And

Multiple bit lines, its common connection follows the above-mentioned transistorized ferromagnetism leakage separately that direction is arranged.

51. a memory circuit is characterized in that having:

Any described transistor in the claim 1 to 41, it is configured to rectangular;

Many word lines, its common a plurality of above-mentioned transistorized gate electrode separately of arranging along column direction that connects;

Multiple bit lines, its common connection follows the above-mentioned transistorized ferromagnetism leakage separately that direction is arranged;

Lead-out terminal, its end separately at this line forms; And

The 2nd wiring, it is connected with power supply through load from this bit line branch separately.

52. as claim 50 or 51 described memory circuits, it is characterized in that,

53. memory circuit as claimed in claim 52 is characterized in that,

Available above-mentioned word line and above-mentioned bit line, perhaps, in above-mentioned word line or the above-mentioned bit line either party replace the above-mentioned the 1st other wiring and the above-mentioned the 2nd other wiring, perhaps, in the above-mentioned the 1st other wiring or the above-mentioned the 2nd other wiring either party.

54. any described memory circuit as in the claim 50 to 53 is characterized in that,

By the above-mentioned the 1st other the wiring and the above-mentioned the 2nd other wiring, their above-mentioned word line and above-mentioned bit line have perhaps been replaced, perhaps replaced either party above-mentioned word line or the above-mentioned bit line in the above-mentioned the 1st other wiring or the above-mentioned the 2nd other wiring, and be not replaced as they a side the above-mentioned the 1st other wiring or the 2nd other the wiring in flow through electric current, utilize the magnetic field of inducting thus, the magnetization inversion that above-mentioned ferromagnetism source or above-mentioned ferromagnetism are leaked, relative magnetized state between making above-mentioned ferromagnetism source and above-mentioned ferromagnetism being leaked changes, thus the rewriting of the information of carrying out.

55. any described memory circuit as in the claim 50 to 54 is characterized in that,

Have under the parallel magnetized situation with above-mentioned ferromagnetism leakage in above-mentioned ferromagnetism source, above-mentioned word line is applied the voltage bigger than above-mentioned threshold value, according to the size of the leakage current in the above-mentioned transistor of the situation that between above-mentioned ferromagnetism source and the leakage of above-mentioned ferromagnetism, has applied the bias voltage of stipulating, carry out reading of information.

56. any described memory circuit as in the claim 51 to 54 is characterized in that,

Have under the parallel magnetized situation with above-mentioned ferromagnetism leakage in above-mentioned ferromagnetism source, through above-mentioned word line above-mentioned gate electrode is applied the voltage bigger than above-mentioned threshold value, according to voltage drop by the above-mentioned load of the leakage current generating in the above-mentioned transistor at this moment, utilize resulting output voltage, carry out reading of information.

57. any described memory circuit as in the claim 43 to 55 is characterized in that,

Magnetization inversion by above-mentioned ferromagnetism source or above-mentioned ferromagnetism are leaked carries out the rewriting of information.

58. a memory element is characterized in that having:

Any one the described the 1st and 2 transistors of the 2nd in the claim 1 to 41;

The 1st wiring, it connects the above-mentioned the 1st transistorized gate electrode and the above-mentioned the 2nd transistorized gate electrode jointly;

The 2nd wiring, it leaks with the 1st ferromagnetism that above-mentioned the 1st transistor is had and is connected and the 3rd wiring, and it leaks with the 2nd ferromagnetism that the 2nd transistor is had and is connected; And

The 4th wiring, the above-mentioned ferromagnetism source ground connection that it is common with the above-mentioned the 1st and the 2nd transistor.

59. a memory circuit is characterized in that,

Have the described memory element of claim 58 is decided to be memory cell, and this memory cell arrangements is become rectangular structure.

60. any described transistor as in the claim 1 to 3 is characterized in that,

As above-mentioned semiconductor layer, use unadulterated semiconductor or intrinsic semiconductor.

61. as claim 18 or 19 described transistors, it is characterized in that,

62. any described transistor as in the claim 4,6 to 9,14 to 17,20,22 to 30,36 to 41 is characterized in that,

Above-mentioned semiconductor layer as in the above-mentioned accumulation channels type uses unadulterated semiconductor or intrinsic semiconductor.

63. any described transistor as in the claim 5,10 to 15,17,21,31 to 41 is characterized in that,

Above-mentioned semiconductor layer as in the above-mentioned inversion channel type uses unadulterated semiconductor or intrinsic semiconductor.

64. any described transistor as in the claim 1 to 39 or 60,61 is characterized in that,

As the length of the conduction orientation of the charge carrier in the above-mentioned semiconductor layer or be defined as above-mentioned ferromagnetism source and the channel length at the interval of ferromagnetism between leaking, but the length that has charge carrier impact type ground to conduct in above-mentioned semiconductor layer, perhaps above-mentioned channel length is smaller or equal to the mean free path to energy relaxation of charge carrier.

65. any described transistor as in claim 1 to 17 or 60 or 64 is characterized in that,

On the interface of above-mentioned ferromagnetism metal and above-mentioned semiconductor layer, have and above-mentioned semiconductor layer between form schottky junction metal level or and above-mentioned ferromagnetism metal between form the semiconductor layer of schottky junction, perhaps metal/semiconductor schottky junction layer.

66. any described transistor as in claim 18 to 39 or 61 or 64 is characterized in that,

On the interface of above-mentioned semimetal and above-mentioned semiconductor layer, have and above-mentioned semiconductor layer between form schottky junction metal level or and above-mentioned semimetal between form the semiconductor layer of schottky junction, perhaps metal/semiconductor schottky junction layer.

67. any described transistor as in the claim 60 to 66 is characterized in that,

Leaking above-mentioned ferromagnetism source in above-mentioned ferromagnetism is under the situation of antiparallel magnetization, compares with parallel magnetized situation, and leakage current reduces.

68. any described transistor as in the claim 60 to 67 is characterized in that,

The relative direction of magnetization control transefer conductance that can utilize above-mentioned ferromagnetism source and above-mentioned ferromagnetism to leak.

69. a memory element is characterized in that,

Adopt any one described 1 transistor in the claim 60 to 68, utilize the relative direction of magnetization stored information of above-mentioned ferromagnetism leakage to above-mentioned ferromagnetism source, according to depending on the transistorized transefer conductance of above-mentioned ferromagnetism source, detect the information that is stored in the above-mentioned transistor with the relative direction of magnetization of above-mentioned ferromagnetism leakage.

70. any described memory element as in claim 42 to 49 or 58 is characterized in that,

As above-mentioned transistor, use any described transistor in the claim 60 to 68.

71. any described storage element circuit as in claim 50 to 57 or 59 is characterized in that,

72. a transistor is characterized in that having:

Source and leakage, it has the 1st conduction type, is made of the ferromagnetism semiconductor;

Semiconductor layer, it forms the raceway groove of above-mentioned the 1st conduction type with respect to above-mentioned source and above-mentioned leakage setting; And

Gate electrode, it forms with respect to above-mentioned semiconductor layer.

73. as the described transistor of claim 72, it is characterized in that,

Above-mentioned semiconductor layer is formed by unadulterated semiconductor or intrinsic semiconductor.

74. as claim 72 or 73 described transistors, it is characterized in that,

75. a transistor is characterized in that having:

The source, it is formed by formed 1pn knot between mutually different the 1st ferromagnetism semiconductor of conduction type and semiconductor layer;

Leak, it is formed by formed 2pn knot between mutually different the 2nd ferromagnetism semiconductor of conduction type and above-mentioned semiconductor layer; And

Gate electrode, it forms with respect to above-mentioned semiconductor layer.

76. as the described transistor of claim 75, it is characterized in that,

77. any described transistor as in the claim 72 to 76 is characterized in that,

78. any described transistor as in the claim 72 to 77 is characterized in that,

79. a memory element is characterized in that,

Adopt any one described 1 transistor in the claim 72 to 78, the relative direction of magnetization stored information of utilizing above-mentioned ferromagnetism source and above-mentioned ferromagnetism to leak, according to depending on the transistorized transefer conductance of above-mentioned ferromagnetism source, detect the information that is stored in the above-mentioned transistor with the relative direction of magnetization of above-mentioned ferromagnetism leakage.

80. any described memory element as in claim 42 to 49 or 58 is characterized in that,

As above-mentioned transistor, use any described transistor in the claim 72 to 78.

81. any described memory circuit as in claim 50 to 57 or 59 is characterized in that,

82. a transistor is characterized in that,

Have:

Ferromagnetism body ferromagnetism source, its inject spin polarization conduction carrier;

Ferromagnetism is leaked, and its ferromagnetism body by the spin polarization conduction carrier of having accepted to inject from this ferromagnetism source constitutes;

Semiconductor layer, it is set between above-mentioned ferromagnetism source and the leakage of above-mentioned ferromagnetism, forms the knot separately that leaks with above-mentioned ferromagnetism source and above-mentioned ferromagnetism; And

Gate electrode, it forms with respect to above-mentioned semiconductor layer,

The ferromagnetism metal is used for either party of above-mentioned source and above-mentioned leakage, semimetal is used for the opposing party.

83. any described transistor as in the claim 1 to 41,60 to 68,72 to 78,82 is characterized in that,

As the gate insulating film that forms between above-mentioned gate electrode and the above-mentioned semiconductor layer, use the insulator that forms by oxidation or deposit.

84. as the described transistor of claim 83, it is characterized in that,

Above-mentioned gate insulating film comprises high dielectric constant material.

85. any described transistor as in the claim 1 to 41,60 to 68,72 to 78,82,84 is characterized in that,

Above-mentioned transistor is MISFET.

86. any described transistor as in the claim 1 to 3,8,9,12,13,18,19,28,29,33,34,72 to 78,82 to 85 is characterized in that,

By in above-mentioned semiconductor layer, mixing, has transistorized function as depletion-mode with impurity.