CN106531883A - STT-MRAM (Spin Torque Transfer-Magnetic Random Access Memory) storage unit - Google Patents
STT-MRAM (Spin Torque Transfer-Magnetic Random Access Memory) storage unit Download PDFInfo
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- CN106531883A CN106531883A CN201611258855.XA CN201611258855A CN106531883A CN 106531883 A CN106531883 A CN 106531883A CN 201611258855 A CN201611258855 A CN 201611258855A CN 106531883 A CN106531883 A CN 106531883A
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- 238000003860 storage Methods 0.000 title abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 114
- 239000002184 metal Substances 0.000 claims abstract description 114
- 230000005291 magnetic effect Effects 0.000 claims abstract description 31
- 230000005294 ferromagnetic effect Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims description 31
- 230000008859 change Effects 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000009987 spinning Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910000531 Co alloy Inorganic materials 0.000 claims description 2
- 229910000640 Fe alloy Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 230000008878 coupling Effects 0.000 abstract description 5
- 238000010168 coupling process Methods 0.000 abstract description 5
- 238000005859 coupling reaction Methods 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 238000012546 transfer Methods 0.000 description 5
- 229910052742 iron Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000004873 anchoring Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005293 ferrimagnetic effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
Abstract
The invention provides an STT-MRAM (Spin Torque Transfer-Magnetic Random Access Memory) storage unit. The STT-MRAM comprises a selection transistor, a ferromagnetic metal free layer and a ferromagnetic metal fixing layer, wherein the selection transistor comprises a substrate, a first doping region, a second doping region and a grid, the ferromagnetic metal free layer is arranged on the first doping region, the magnetic moment direction of the ferromagnetic metal free layer can be changed, the ferromagnetic metal fixing layer is arranged on the second doping region, and the magnetic moment direction of the ferromagnetic metal fixing layer is fixed and unchanged. In the STT-MRAM storage unit provided by the invention, the whole selection transistor is used as a storage structure, the ferromagnetic metal free layer is arranged on the first doping region of the selection transistor, the ferromagnetic metal fixing layer is arranged on the second doping region of the selection transistor, thus, the coupling strength between the selection transistor and the ferromagnetic metal free layer and between the selection transistor and the ferromagnetic metal fixing layer is improved, and the integration and the stability of a product are improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of STT-MRAM memory cell.
Background technology
STT-MRAM (spin torque transfer magnetic random access memory spin transfer power
Square magnetic random memory) it is fast with non-volatile, operating rate, the unlimited inferior advantage of erasable number of times novel memory devices,
STT-MRAM had both had DRAM (dynamic random access memory) and SRAM (system management
Random access memory) high-performance, and the low-power consumption with flash memory and low cost.STT-MRAM memory technologies are most
It is possible to replace the advanced memory technology of DRAM and SRAM.
In prior art, STT-MRAM generally includes to be connected with each other magnetic tunnel-junction (magnetic tunneling
Junction, MJT) and selection transistor, MJT includes feeromagnetic metal fixed bed and feeromagnetic metal free layer and between the two
Barrier layer, realizes being stored and read out for data by the magnetic moment direction for accessing feeromagnetic metal free layer in current control MJT.It is existing
, through repeatedly read-write, barrier layer can be gradually aging, and the stability of MJT will be received for the barrier layer of MJT of the technology in STT-MRAM
To test.In prior art, the MJT of STT-MRAM typically can be integrated in postchannel process simultaneously, by the source/drain terminal of selection transistor
It is connected with MJT by metal connecting line (contact) so that MJT is weaker with the coupling of selection transistor, not only increases technique step
Suddenly, technology difficulty is increased, the performance of memory cell is also died down therewith.With the development of technology, semiconductor dimensions are required
Continuous diminution, require to improve integrated level in technique, reduce device cellar area, also require that in performance and to improve device cell
Stability and reliability.Therefore, the performance for how improving STT-MRAM memory cell is that those skilled in the art need to solve
One technical problem.
The content of the invention
It is an object of the invention to provide a kind of STT-MRAM memory cell, to solve STT-MRAM storages in prior art
The problem that the performance of unit has much room for improvement.
To solve above-mentioned technical problem, the present invention provides a kind of STT-MRAM memory cell, including selection transistor, ferromagnetic
Metal free layer and feeromagnetic metal fixed bed, the selection transistor include substrate, the first doped region, the second doped region and grid
Pole, the feeromagnetic metal free layer are arranged on first doped region, and the magnetic moment direction of the feeromagnetic metal free layer can change
Become, the feeromagnetic metal fixed bed is arranged on second doped region, and the magnetic moment direction of the feeromagnetic metal fixed bed is fixed
It is constant.
Optionally, in the STT-MRAM memory cell, via the feeromagnetic metal free layer, first doping
Area, the channel region of the selection transistor, second doped region to the feeromagnetic metal fixed bed constitute spinning current passage.
Optionally, in the STT-MRAM memory cell, negative pressure is connect in first doped region, make the feeromagnetic metal
The magnetic moment direction of free layer is identical with the magnetic moment direction of the feeromagnetic metal fixed bed.
Optionally, in the STT-MRAM memory cell, malleation is connect in first doped region, make the feeromagnetic metal
The magnetic moment direction of free layer is contrary with the magnetic moment direction of the feeromagnetic metal fixed bed.
Optionally, in the STT-MRAM memory cell, also including the first barrier layer and the second barrier layer, described first
Barrier layer is arranged between the feeromagnetic metal free layer and first doped region, and second barrier layer is arranged at the iron
Between magnetic metal anchoring layer and second doped region.
Optionally, in the STT-MRAM memory cell, first barrier layer and second barrier layer are nitrogen
The thickness for changing titanium, first barrier layer and second barrier layer is 1nm～2nm.
Optionally, in the STT-MRAM memory cell, also including first medium layer and second dielectric layer, described first
Dielectric layer is arranged between the feeromagnetic metal free layer and the grid, and the second dielectric layer is arranged on the feeromagnetic metal
Between fixed bed and the grid.
Optionally, in the STT-MRAM memory cell, the first medium layer and the second dielectric layer are oxygen
The thickness of SiClx or silicon nitride, the first medium layer and the second dielectric layer is 15nm～20nm.
Optionally, in the STT-MRAM memory cell, the material of the feeromagnetic metal free layer include iron, cobalt or
A combination of both thing.
Optionally, in the STT-MRAM memory cell, the selection transistor is N-type MOS field
Effect pipe, the substrate adulterate for p-type, and first doped region and the second doping structure are n-type doping.
In sum, in the STT-MRAM memory cell that the present invention is provided, using whole selection transistor as storage knot
Structure, by feeromagnetic metal free layer is arranged on the first doped region of selection transistor, feeromagnetic metal fixed bed is arranged on
On second doped region of selection transistor, so as to improve selection transistor with feeromagnetic metal free layer and consolidating with feeromagnetic metal
The stiffness of coupling of given layer, and the magnetic moment direction of feeromagnetic metal free layer is controlled realizing read-write operation by reset current, improve
Product integrated level and stability.
Description of the drawings
Fig. 1 is the cut-away view of the STT-MRAM memory cell of the embodiment of the present invention；
Fig. 2 is the cut-away view of the STT-MRAM memory cell of one embodiment of the embodiment of the present invention；
Fig. 3 is the cut-away view of the STT-MRAM memory cell of another embodiment of the embodiment of the present invention.
Specific embodiment
In order that objects, features and advantages of the present invention can become apparent from understandable, accompanying drawing is referred to.It should be clear that this explanation
Structure, ratio, size depicted in book institute accompanying drawings etc., only to coordinate the content disclosed in specification, for being familiar with this
The personage of technology understands and reads, and is not limited to enforceable qualifications of the invention, therefore does not have technical essence and anticipate
Justice, the modification of any structure, the change of proportionate relationship or the adjustment of size, in effect and institute for not affecting the present invention can be generated
Under the purpose that can be reached, still all should fall in the range of disclosed technology contents are obtained and can be covered.
As shown in figure 1, the present invention provides a kind of STT-MRAM memory cell, including selection transistor 10, feeromagnetic metal is certainly
By layer 20 and feeromagnetic metal fixed bed 30, the selection transistor 10 includes substrate 100, the first doped region 110, the second doped region
120 and grid 130, the feeromagnetic metal free layer 20 is arranged on first doped region 110, the feeromagnetic metal free layer
20 magnetic moment direction can change, and the feeromagnetic metal fixed bed 30 is arranged on second doped region 120, the feeromagnetic metal
The magnetic moment direction of fixed bed 30 immobilizes.
With continued reference to shown in Fig. 1, the STT-MRAM memory cell that the present invention is provided, via the feeromagnetic metal free layer
20th, first doped region 110, the channel region 140 of the selection transistor 10, second doped region 120 arrive described ferromagnetic
Metal anchoring layer 30 constitutes spinning current passage, i.e., in the case of turn-on current, electronics is advanced in spinning current passage, root
According to the spinning current passage for being formed electronics spin direction affecting the magnetic moment direction of feeromagnetic metal free layer, in the present embodiment
In, selection transistor 10 can adopt conventional design, the first doped region 110 and the second doped region 120 to be located in substrate 100, grid
130 on the substrate 100 and positioned between the first doped region 110 and the second doped region 120.
The STT-MRAM memory cell that the present invention is provided also includes the first barrier layer 111 and the second barrier layer 121, described the
One barrier layer 111 is arranged between the feeromagnetic metal free layer 20 and first doped region 110, second barrier layer
121 are arranged between the feeromagnetic metal fixed bed 30 and second doped region 120, by the first barrier layer 111 and second
Barrier layer 121 playing the protective effect of stop, to when being prevented feeromagnetic metal free layer 20 from being formed by the first barrier layer 11
The impact of one doped region 110, to the second doped region 120 when being prevented feeromagnetic metal fixed bed 30 from being formed by the second barrier layer 121
Impact, for example, feeromagnetic metal free layer and feeromagnetic metal fixed bed are formed by way of deposition, so as to prevent depositing
The first doped region and the second doped region are polluteed in journey.
Optionally, first barrier layer 111 and second barrier layer 121 are titanium nitride, and titanium nitride has preferable
Conductive characteristic, the thickness on first barrier layer 111 and second barrier layer 121 is 1nm～2nm, and by above-mentioned
Thickness range is formed and is preferably protected.As feeromagnetic metal free layer 20 and feeromagnetic metal fixed bed 30 are formed directly into selection crystalline substance
On body pipe 10, so as to improve coupling of the selection transistor 10 with feeromagnetic metal free layer 20 and with feeromagnetic metal fixed bed 30
Intensity, and then the performance of STT-MRAM memory cell can be improved.
The STT-MRAM memory cell that the present invention is provided also includes first medium layer 131 and second dielectric layer 132, described the
One dielectric layer 131 is arranged between the feeromagnetic metal free layer 20 and the grid 130, and the second dielectric layer 132 is arranged
Between the feeromagnetic metal fixed bed 30 and the grid 130, risen by first medium layer 131 and second dielectric layer 132
To the protective effect of isolation, electric effect of the feeromagnetic metal free layer 20 to grid 130 is prevented by first medium layer 131, by
Second medium is layer by layer 132 preventing electric effect of the feeromagnetic metal fixed bed 30 to grid 130, for example, the iron during read-write
Magnetic metal free layer 20, feeromagnetic metal fixed bed 30 and grid 130 need making alive respectively, are prevented by first medium layer 131
Leakage current is produced between feeromagnetic metal free layer 20 and grid 130, feeromagnetic metal fixed bed 30 is prevented by second dielectric layer 132
Leakage current is produced between grid 130, so as to the performance for preventing selection transistor 10 is affected.
Optionally, the first medium layer 131 and the second dielectric layer 132 are silica or silicon nitride, and described
The thickness of one dielectric layer 131 and the second dielectric layer 132 is 15nm～20nm,.
The material of the feeromagnetic metal free layer includes the combined alloy of iron, cobalt or both, by iron, cobalt or both
The material of combined alloy form ferromagnetic and Ferrimagnetic.
Optionally, the selection transistor 10 be N-type metal oxide semiconductor field effect tube (MOSFET), the substrate
100 adulterate for p-type, and first doped region 110 and second doped region 120 are n-type doping, N-type metal oxide half
Conductor FET is electronics as the carrier of conduction, so as to be suitable for more occasions.
In the present embodiment, when information " 0 " is write, negative pressure (V is met in first doped region 110<0), electric current passes through
Feeromagnetic metal free layer 20 flows to feeromagnetic metal fixed bed 30, and electronics is then from feeromagnetic metal fixed bed 30 by selection transistor
Channel region 140 flows to feeromagnetic metal free layer 20.Now, due in electric current electronics after feeromagnetic metal fixed bed 30, flow direction
Receive making for the electron spin angular momentum of electronics in feeromagnetic metal fixed bed 30 in the electron spin direction of the electronics of selection transistor 10
With under, the electron spin direction phase of the electron spin direction of electronics and electronics in feeromagnetic metal fixed bed 30 in selection transistor 10
Together, i.e., so that its electron spin direction of electronics that electron spin direction is different from electronics in feeromagnetic metal fixed bed 30 is turned over
Turn.Specifically, as shown in Fig. 2 electron spin direction is downward in feeromagnetic metal fixed bed；It is solid with feeromagnetic metal in channel region 140
The different electronics of the electron spin of given layer 30 is subject to the spin angular motion of the downward electronics of electron spin in feeromagnetic metal fixed bed 30
There is upset in the presence of amount so that the electron spin direction of electronics is all directed to downwards in channel region 140；Then electronics via
The channel region 140 of selection transistor 10 and the first doped region 110；Feeromagnetic metal free layer 20 is reached finally；Wherein, ferromagnetic gold
Category free layer 20 is affected by the downward electronics in electron spin direction in the channel region 10 of selection transistor 10, is turned round by spin transfer
Square effect make the electron spin direction of electronics in electron spin direction and the channel region 140 of the electronics of feeromagnetic metal free layer 20 with
And in feeromagnetic metal fixed bed 30 electronics electron spin direction it is identical, i.e., the electron spin direction of electronics in ferromagnetic free layer 20
And downwards, make the magnetic moment direction of the feeromagnetic metal free layer 20 and the magnetic moment direction phase of the feeromagnetic metal fixed bed 30
Together, now whole memory cell resistance is little, data " 0 " write.In the same condition, when the current potential for measuring the first doped region 110
When, electronegative potential is measured, is then data " 0 ".
In the present embodiment, when information " 1 " is write, malleation (V is met in first doped region 110>0), electric current passes through
Feeromagnetic metal free layer 20 flows to feeromagnetic metal fixed bed 30, and electronics is from feeromagnetic metal free layer 20 by selection transistor 10
Channel region 140 flows to feeromagnetic metal fixed bed 30.Now, as electric current is after feeromagnetic metal free layer 20, from feeromagnetic metal
Free layer 20 flow to the electron spin direction of the electronics of channel region 140 be it is random, it is existing upwards, also have downward.Specifically
, as shown in figure 3, the downward electronics in electron spin direction can smoothly pass through feeromagnetic metal fixed bed 30, and channel region 140
The electron spin direction of middle electronics electronics upwards due to spin transfer torque effect be reflected back, in channel region 140 these
When electron spin direction electron reflection upwards reaches the interface of feeromagnetic metal free layer 20, and made by spin transfer torque effect
The electron spin direction of the electronics of feeromagnetic metal free layer 20 is identical with the electron spin direction of electronics in channel region 140, even if
In ferromagnetic free layer 20 the electron spin direction of electronics upwards, make the magnetic moment direction of the feeromagnetic metal free layer 20 with it is described
The magnetic moment direction of feeromagnetic metal fixed bed 30 is contrary so that whole memory cell resistance is big, data " 1 " write.In same condition
Under, when the current potential of the first doped region 110 is measured, measure high potential, be then data " 1 ".
In a particular embodiment, the first doped region is connect into bit line, grid connects wordline, realizes read-write operation, wherein,
First doped region and the second doped region respectively become the source/drain of selection transistor, selection transistor by source drain dopant technique
For the switching device of such as metal-oxide-semiconductor, the conventional description of this area is with regard to the first doped region and the second doped region.The present invention's
In STT-MRAM memory cell, the direction being related to using the definition on ordinary meaning, wherein, feeromagnetic metal free layer and ferromagnetic gold
Direction of the magnetic moment direction of category fixed bed using the substrate perpendicular to selection transistor, the spin direction of electronics be also adopted by perpendicular to
The direction of the substrate of selection transistor, any conversion that those skilled in the art are made to this is still in the protection model of the present invention
Enclose.
In sum, in the STT-MRAM memory cell that the present invention is provided, using whole selection transistor as storage knot
Structure, by feeromagnetic metal free layer is arranged on the first doped region of selection transistor, feeromagnetic metal fixed bed is arranged on
On second doped region of selection transistor, so as to improve selection transistor with feeromagnetic metal free layer and consolidating with feeromagnetic metal
The stiffness of coupling of given layer, and by the magnetic moment direction of feeromagnetic metal free layer and feeromagnetic metal fixed bed realizing read-write operation,
The structure of STT-MRAM memory cell has less volume, improves the utilization rate of selection transistor, and it is integrated to improve product
Degree and stability.
Foregoing description is only the description to present pre-ferred embodiments, not any restriction to the scope of the invention, this
Any change that the those of ordinary skill in bright field is done according to the disclosure above content, modification, belong to the protection of claims
Scope.
Claims (10)
1. a kind of STT-MRAM memory cell, it is characterised in that the STT-MRAM memory cell includes：
Selection transistor, the selection transistor include substrate, the first doped region, the second doped region and grid；
Feeromagnetic metal free layer, the feeromagnetic metal free layer are arranged on first doped region, the feeromagnetic metal freedom
The magnetic moment direction of layer can change；
Feeromagnetic metal fixed bed, the feeromagnetic metal fixed bed are arranged on second doped region, and the feeromagnetic metal is fixed
The magnetic moment direction of layer immobilizes.
2. STT-MRAM memory cell according to claim 1, it is characterised in that via the feeromagnetic metal free layer,
First doped region, the channel region of the selection transistor, second doped region are constituted to the feeromagnetic metal fixed bed
Spinning current passage.
3. STT-MRAM memory cell according to claim 1, it is characterised in that connect negative pressure in first doped region,
Make the magnetic moment direction of the feeromagnetic metal free layer identical with the magnetic moment direction of the feeromagnetic metal fixed bed.
4. STT-MRAM memory cell according to claim 1, it is characterised in that connect malleation in first doped region,
Make the magnetic moment direction of the feeromagnetic metal free layer contrary with the magnetic moment direction of the feeromagnetic metal fixed bed.
5. STT-MRAM memory cell as claimed in any of claims 1 to 4, it is characterised in that the STT-
Mram memory cell also includes the first barrier layer and the second barrier layer, and first barrier layer is arranged at the feeromagnetic metal freedom
Between layer and first doped region, second barrier layer is arranged at the feeromagnetic metal fixed bed with second doped region
Between.
6. STT-MRAM memory cell according to claim 5, it is characterised in that first barrier layer and described second
Barrier layer is the thickness of titanium nitride, first barrier layer and second barrier layer and is 1nm～2nm.
7. STT-MRAM memory cell as claimed in any of claims 1 to 4, it is characterised in that the STT-
Mram memory cell also includes first medium layer and second dielectric layer, and the first medium layer is arranged on the feeromagnetic metal freedom
Between layer and the grid, the second dielectric layer is arranged between the feeromagnetic metal fixed bed and the grid.
8. STT-MRAM memory cell according to claim 7, it is characterised in that the first medium layer and described second
Dielectric layer is the thickness of silica or silicon nitride, the first medium layer and the second dielectric layer and is 15nm～20nm.
9. STT-MRAM memory cell as claimed in any of claims 1 to 4, it is characterised in that the ferromagnetic gold
The material of category free layer includes the combined alloy of iron, cobalt or both.
10. STT-MRAM memory cell as claimed in any of claims 1 to 4, it is characterised in that the selection is brilliant
Body pipe is N-type metal oxide semiconductor field effect tube, and the substrate is that p-type is adulterated, first doped region and described second
Doped region is n-type doping.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611258855.XA CN106531883A (en) | 2016-12-30 | 2016-12-30 | STT-MRAM (Spin Torque Transfer-Magnetic Random Access Memory) storage unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611258855.XA CN106531883A (en) | 2016-12-30 | 2016-12-30 | STT-MRAM (Spin Torque Transfer-Magnetic Random Access Memory) storage unit |
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| US20070164336A1 (en) * | 2006-01-17 | 2007-07-19 | Yoshiaki Saito | Spin fet and spin memory |
| CN101202302A (en) * | 2002-07-25 | 2008-06-18 | 科学技术振兴机构 | Spin transistor based on the spin-filter effect, and non-volatile memory using spin transistors |
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| CN101202302A (en) * | 2002-07-25 | 2008-06-18 | 科学技术振兴机构 | Spin transistor based on the spin-filter effect, and non-volatile memory using spin transistors |
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Application publication date: 20170322 |