CN1729731B - 具有用于将封装件衬底接合到印刷电路板的复合电子触点的电子组件 - Google Patents

具有用于将封装件衬底接合到印刷电路板的复合电子触点的电子组件 Download PDF

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CN1729731B
CN1729731B CN038028867A CN03802886A CN1729731B CN 1729731 B CN1729731 B CN 1729731B CN 038028867 A CN038028867 A CN 038028867A CN 03802886 A CN03802886 A CN 03802886A CN 1729731 B CN1729731 B CN 1729731B
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爱德华·N·马丁
拉里·比格斯
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Abstract

一种电子触点被提供用于将半导体封装件衬底接合到印刷电路板上，所述电子触点包括球状核和所述核上的接合层。球状核由高熔化温度的铜制成，接合层由低熔化温度的共晶体制成。接合层在回流工艺过程中熔化。球状核不熔化，因而控制了封装件衬底朝向印刷电路板的移动或“塌陷”。

Description

具有用于将封装件衬底接合到印刷电路板的复合电子触点的电子组件
技术领域
本发明涉及一种其类型是具有被接合到印刷电路板上的半导体封装件衬底的电子组件。
背景技术
在其中形成有集成电路的半导体管芯经常被安装在封装件衬底上。集成电路通过封装件衬底上表面上的接触焊盘和封装件衬底中的金属线路被电连接到封装件衬底下表面上的接触焊盘。各个焊球被接合到封装件衬底下表面上的相应的接触焊盘上。焊球被放置在水平面中的阵列内。
随后焊球被放置在印刷电路板上表面上的接触端子上。然后焊球被加热到其熔化温度以上，使得它们回流到印刷电路板上的接触端子上。随后对焊球进行冷却并使其凝固，从而将它们固定到接触端子上。
当焊球回流时，封装件衬底通常会朝向印刷电路板塌陷。过去不需要最小化这种塌陷，因为塌陷并不直接地影响印刷电路板和封装件衬底之间的结构或电的配合。
附图说明
参照附图，通过示例来描述本发明，其中：
图1是图示了根据本发明的原理被装配的电子组件的侧视图；
图2是图示了在接合到封装件衬底上的接触焊盘之前被放置在装配架上的电子触点的侧视图；
图3是在使电子触点与接触焊盘开始接触，并且部分组件被翻转使得电子触点位于顶部之后的类似图2的视图；
图4是在加热、冷却并去除焊剂之后的类似图3的视图；
图5是在图4的组件被翻转使得电子触点位于底部，并随后被放置在底板组件的接触端子上之后的类似图4的视图；
图6是图示了图5的电子组件在被加热并冷却，以将电子触点的接合层与接触端子接合之后，电子触点的球状核用作控制封装件衬底朝向底板组件移动的支座时的类似图5的视图。
具体实施方式
附图中的图1示出了根据本发明的原理构建的电子组件10。现在参照图2到图6对电子组件10的构建方式作进一步的描述。
图2示出了连同触点固定装配架14的部分被构建的半导体组件12的元件。半导体组件12包括衬底子组件16、半导体管芯子组件18和电子触点20。
衬底子组件16包括封装件衬底22以及在封装件衬底22下表面上的多个接触焊盘24.封装件衬底22是多层衬底，包括交替的电介质和金属线路(未示出).接触焊盘24由金属制成，并被电连接到金属线路.更多的接触焊盘(未示出)形成在封装件衬底22的上表面上.封装件衬底22上表面上的接触焊盘也与金属线路电连接，并通过金属线路与接触焊盘24电连接.
半导体管芯子组件18包括半导体管芯26和多个电连接物28。管芯26在其下表面内形成有集成电路(未示出)，电连接物28形成在集成电路下表面上的端子上(未示出)。电连接物28被放置于在封装件衬底22上表面上的接触焊盘的上表面上，随后在热回流工艺过程中被焊接到接触焊盘上。管芯26因而通过电连接物28而在结构上被固定到封装件衬底22上。接触焊盘24也通过封装件衬底22中的金属线路以及电连接物28而与管芯26的集成电路电连接。
每个电子触点20具有球状核32和完全包围球状核32的接合层34，即接合层34均匀地位于球状核32的全部表面上。在优选的实施例中，球状核32由纯铜制成，直径约为0.7mm。在优选的实施例中，接合层34由纯的锡银共晶体制成，含有按重量计的3.5％的银，并且厚度约为0.025mm。这种电子触点可以从日本大阪的Sumitomo Special Metals有限公司获得。
在装配架14的上表面中形成有凹坑36。凹坑36与接触焊盘24相对准，并且各个电子触点20位于相应的凹坑36内。从而，每个电子触点20直接在相应的接触焊盘24下方被对准。
接触焊盘24的下表面选择性地用焊剂38进行模版印刷。随后，将装配架14沿方向40垂直向上移动。电子触点20与装配架14一起沿方向40移动，并渗入焊剂38。
在电子触点20和接触焊盘24被带到一起之后，将整个组件翻转过来，这样使得装配架14位于顶部。装配架14然后被提起，将电子触点20留在接触焊盘24上。图3示出了装配架14被提起之后的半导体组件12。焊剂38的粘性防止了电子触点20滚离接触焊盘24。
图4示出了在被加热并随后被冷却之后，并且焊剂38被去除之后的图3的半导体组件12。半导体组件12被加热至约230℃的温度。层34的材料在约227℃熔化。层34浸润接触焊盘24。由熔化温度为1083℃的铜制成的球状核32不会熔化。随后半导体组件12被冷却至层34的材料的熔化温度以下，从而将层34接合到接触焊盘24上。
如图5所示，半导体组件12随后被翻转过来，使得电子触点20位于底部并被放置在底板组件42上。底板组件42包括印刷电路板44和形成在印刷电路板44上表面上的接触端子46。焊剂47被模版印刷在每个接触端子46上。每个层34的下部分渗入焊剂47，并放置在相应的接触端子46上。
然后再次将图5的被部分制造的电子组件48加热至约230℃，再冷却到室温。图6示出了被加热并冷却之后的电子组件48。230℃的温度再次使层34的材料熔化，这样使得它们润湿接触端子46。
层34的熔化还造成封装件衬底22和管芯26在方向50上朝向印刷电路板44稍许移动或“塌陷”.球状核32不会在230℃的温度下熔化.因而，球状核32在整个回流工艺过程中保持其球状形状，并且直到各个球状核32接触接触焊盘24和其相对侧的接触端子46时，用作限制方向50中的移动的支座.球状核32禁止了封装件衬底22在方向50上朝向印刷电路板44的进一步移动.这样，在相对的接触焊盘24和接触端子46之间的余留距离被球状核32的直径限制.随后，冷却电子组件48，使得接合层34凝固，从而使它们与接触端子46和接触焊盘24固定.
各个接触端子46通过相应的层34而被固定到相应的接触焊盘24。接触端子46还通过接合层34和球状核32两者而被电连接到接触焊盘24。
再次参照图1，电容器52被接合到封装件衬底22的下表面。电容器52完全被电子触点20所包围。每个电容器52具有下表面，所述下表面与封装件衬底22顶部的下表面以一定距离隔开，该距离小于封装件衬底22的下表面与印刷电路板44的上表面之间的间隔。这样，在每个电容器52的下表面与印刷电路板44的上表面之间界定有间隙54。通过球状核32，防止了电容器52和印刷电路板44之间的接触。
球状核32的直径主要取决于电容器52的高度。在其他实施例中，球状核32的直径可以在0.5mm与0.8mm之间。在其他实施例中，接合层34的厚度可以在0.015mm与0.035mm之间。
在另一实施例中，含有按重量计的0.7％的铜的锡铜共晶体可以被用来代替层34的锡银共晶体。但是，锡铜共晶体的熔化温度为232℃，稍高于锡银共晶体的熔化温度。因而，锡银共晶体比锡铜共晶体更为优选。
另一种可被用来代替层34的锡银共晶体的共晶体是含有按重量计的37％的铅的锡铅共晶体。这种锡铅共晶体具有相对低的熔化温度，约为183℃。这种共晶体的缺点在于其含有对环境不利的铅。或者，也可以使用纯锡用作接合层，但是纯锡具有相对高的熔化温度。
代替铜，球状核32还可以由银制成。镀银球可从日本枥木的SejuMetal Industry有限公司获得。但是，与铜相比较，银有毒并且昂贵。(层34的共晶体中含有少量银是无关紧要的。)
球状核32或者可以由聚合物制成。聚合物球可从日本大阪的SekisuiChemical有限公司获得。在聚合物球的情况下，接合层34将提供接触焊盘24和接触端子46之间的全部电连接。
铝或青铜也可用来代替铜用作球状核，但是在铝或青铜上形成接合层可能较困难。
在所有其他的实施例中，核和接合层的熔化温度优选地至少相差30℃。
在所述的实施例中，装配架用来放置图2中所示的触点20，然后组件被翻转，如图3所示。另一实施例可以在顶部使用真空夹盘，通过背面的真空密封来固定触点。然后可以将触点浸在焊剂中。真空夹盘接着将触点移至与下面的封装件衬底相接触。
虽然已经在附图中示出并描述了某些示例性实施例，但应该理解，这些实施例仅是示意性的，并非限制本发明，因为本领域的普通技术人员可以想到对所示出和所描述的具体结构和布置的更改，所以本发明并不限于所示出和所描述的具体结构和布置。

Claims (24)

1.一种电子组件，包括：
底板；
在所述底板上表面上的多个接触端子，其中所述底板的上表面包括底阻挡表面；
含有集成电路的电子器件；
在所述电子器件下表面上的多个接触焊盘，所述接触焊盘的每个被电连接到所述集成电路，其中所述电子器件的下表面包括顶阻挡表面；
多个支座部件，所述支座部件的每个被接合到相应的接触焊盘的下表面，其中所述多个支座部件被设置在所述顶和底阻挡表面之间，所述支座部件没有任何部分突出超过所述顶或底阻挡表面，由此在所述顶和底阻挡表面之间提供最小的间隙距离；和
多个接合层，所述接合层的每个被设置在相应的支座部件和相应接触端子的相应上表面之间，其中所述多个接合层具有比所述相应的支座部件的熔化温度低的熔化温度，并且所述多个接合层被焊接到相应的接触端子的相应的上表面上。
2.如权利要求1所述的电子组件，还包括：
被安装到所述电子器件下表面上的电子元件，所述电子元件具有与所述底板上表面隔开的下表面。
3.如权利要求2所述的电子组件，其中所述电子元件被放置在所述支座部件之间。
4.如权利要求2所述的电子组件，其中所述电子元件是电容器。
5.如权利要求1所述的电子组件，其中所述各个接合层的熔化温度比所述相应的支座部件的熔化温度低至少30℃。
6.如权利要求1所述的电子组件，其中所述各个接合层的熔化温度在232℃以下。
7.如权利要求1所述的电子组件，其中所述各个接合层是从由纯锡、锡银共晶体和锡铜共晶体组成的一个组中所选择的。
8.如权利要求7所述的电子组件，其中所述共晶体是锡银共晶体。
9.如权利要求1所述的电子组件，其中所述各个接合层不含铅。
10.如权利要求1所述的电子组件，其中所述各个支座部件不含铅。
11.如权利要求1所述的电子组件，其中所述各个支座部件大致为球状，并且所述各个接合层大致包围所述相应的支座部件。
12.如权利要求11所述的电子组件，其中各个接合层中的每个被焊接到相应的接触焊盘上。
13.如权利要求11所述的电子组件，其中所述各个支座部件的直径在0.5mm与0.8mm之间。
14.如权利要求13所述的电子组件，其中所述各个接合层的厚度在0.015mm与0.035mm之间。
15.如权利要求11所述的电子组件，其中所述各个支座部件包括从由铝、青铜、聚合物、银和铜组成的一个组中所选择的材料。
16.如权利要求15所述的电子组件，其中所述各个支座部件由基本上纯的铜制成。
17.如权利要求1所述的电子组件，其中所述电子器件包括封装件衬底，所述集成电路被安装到所述封装件衬底的上表面。
18.一种电子组件，包括：
底板；
在所述底板上表面上的多个接触端子，其中所述底板的上表面包括底阻挡表面；
封装件衬底；
被安装在所述封装件衬底上表面上的集成电路；
在所述封装件衬底下表面上的多个接触焊盘，所述接触焊盘的每个通过所述封装件衬底被电连接到所述集成电路，其中所述电子器件的下表面包括顶阻挡表面；
多个大致为球状的支座部件，其中所述多个球状支座部件被设置在所述顶和底阻挡表面之间，所述球状支座部件没有任何部分突出超过所述顶或底阻挡表面，由此在所述顶和底阻挡表面之间提供最小的间隙距离；和
多个接合层，所述接合层的每个被放置在相应的支座部件的周围，具有比所述相应的支座部件低的熔化温度，具有被焊接到相应的接触焊盘上的上部，并且具有被焊接到相应的接触端子的下部。
19.如权利要求18所述的电子组件，其中所述各个接合层的熔化温度比所述相应的支座部件的熔化温度低至少30℃。
20.如权利要求19所述的电子组件，其中所述各个支座部件包括从由铝、青铜、聚合物、银和铜组成的一个组中所选择的材料。
21.如权利要求20所述的电子组件，其中所述各个接合层是从由纯锡、锡银共晶体和锡铜共晶体组成的一个组中所选择的。
22.一种装配电子组件的方法，包括：
将多个支座部件接合到电子器件的各个接触焊盘上，其中所述电子器件的下表面包括顶阻挡平面，每个支座部件具有接合层，所述接合层的至少一部分在所述支座部件与所述电子器件相对的一侧上，所述接合层通过所述接触焊盘被电连接到所述电子器件的集成电路，并且具有比所述支座部件的熔化温度低的熔化温度，其中所述接合层的一部分被靠住所述接触焊盘放置、被加热并使得被冷却，以将所述接合层和所述支座部件接合到所述接触焊盘；
将所述接合层的所述部分靠着底板上的接触端子放置，其中所述底板的上表面包括底阻挡表面；
加热所述部分；以及
使得所述部分冷却，以将所述部分接合到所述接触端子，其中所述多个支座部件被设置在所述顶和底阻挡表面之间，所述支座部件没有任何部分突出超过所述顶或底阻挡表面，由此在所述顶和底阻挡表面之间提供最小的间隙距离。
23.如权利要求22所述的方法，其中，加热靠住所述底板上的所述接触焊盘的所述接合层的一部分进一步包括施加力，从而将所述电子器件和所述底板更近地压向一起。
24.如权利要求23所述的方法，其中将所述多个支座部件接合到所述电子器件的各个接触焊盘上还包括：
接触保持装配架，在该装配架的上表面具有凹坑；
将多个支座构件设置在所述装配架的凹坑中，其中所述支座构件基本上是球状的；
翻转该电子器件，使所述球状支座构件设置在所述各个接触焊盘上；
加热；并且
冷却，以将所述球状支座构件接合到所述各个接触焊盘。
CN038028867A 2002-02-04 2003-01-10 具有用于将封装件衬底接合到印刷电路板的复合电子触点的电子组件 Expired - Fee Related CN1729731B (zh)

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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60325620D1 (de) * 2002-09-27 2009-02-12 Neomax Materials Co Ltd Lotbeschichtete kugel und verfahren zu ihrer herstellung und verfahren zur bildung einer halbleiterverbindungsstruktur
US7339263B2 (en) * 2004-06-28 2008-03-04 Intel Corporation Integrated circuit packages, systems, and methods
JP4040644B2 (ja) * 2005-07-28 2008-01-30 シャープ株式会社 半田付け実装構造の製造方法および半田付け実装方法
CA2648900A1 (en) * 2006-04-10 2007-11-08 Innovatier, Inc. An electronic inlay module for electronic cards and tags
US20070290048A1 (en) * 2006-06-20 2007-12-20 Innovatier, Inc. Embedded electronic device and method for manufacturing an embedded electronic device
US20080160397A1 (en) * 2006-08-25 2008-07-03 Innovatier, Inc Battery powered device having a protective frame
US20080055824A1 (en) * 2006-08-25 2008-03-06 Innovatier, Inc. Battery powered device having a protective frame
US20110278725A1 (en) * 2007-01-31 2011-11-17 Nichepac Technology Inc. Stacking of transfer carriers with aperture arrays as interconnection joints
AU2008232405A1 (en) * 2007-03-23 2008-10-02 Innovatier, Inc. A step card and method for making a step card
US7786001B2 (en) * 2007-04-11 2010-08-31 International Business Machines Corporation Electrical interconnect structure and method
US20080282540A1 (en) * 2007-05-14 2008-11-20 Innovatier, Inc. Method for making advanced smart cards with integrated electronics using isotropic thermoset adhesive materials with high quality exterior surfaces
US20090096614A1 (en) * 2007-10-15 2009-04-16 Innovatier, Inc. Rfid power bracelet and method for manufacturing a rfid power bracelet
US20090181215A1 (en) * 2008-01-15 2009-07-16 Innovatier, Inc. Plastic card and method for making a plastic card
DE102010003562B4 (de) * 2010-03-31 2021-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Verfahren und Wiederaufschmelzsystem zum Verbinden eines Halbleiterchips mit einem Gehäusesubstrat
CN102569211A (zh) * 2011-12-10 2012-07-11 中国振华集团永光电子有限公司 晶体管焊接层厚度的控制方法及焊接层结构
US9768137B2 (en) * 2012-04-30 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Stud bump structure for semiconductor package assemblies
JP5692314B2 (ja) * 2013-09-03 2015-04-01 千住金属工業株式会社 バンプ電極、バンプ電極基板及びその製造方法
CN106304825B (zh) * 2015-06-24 2019-01-22 启碁科技股份有限公司 电子装置及雷达装置
KR102420126B1 (ko) 2016-02-01 2022-07-12 삼성전자주식회사 반도체 소자
CN106229721B (zh) * 2016-07-22 2019-05-14 广东小天才科技有限公司 连接触点、充电数据线、电子设备及连接触点的制备方法
CN107335879B (zh) * 2017-06-21 2019-11-08 深圳市汉尔信电子科技有限公司 一种面阵列的封装方法
US11664300B2 (en) * 2019-12-26 2023-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fan-out packages and methods of forming the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087597A (en) * 1994-07-22 2000-07-11 Nec Corporation Connecting member and a connecting method with ball and tapered via

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3303393A (en) 1963-12-27 1967-02-07 Ibm Terminals for microminiaturized devices and methods of connecting same to circuit panels
US5536637A (en) * 1993-04-07 1996-07-16 Genetics Institute, Inc. Method of screening for cDNA encoding novel secreted mammalian proteins in yeast
US5801446A (en) * 1995-03-28 1998-09-01 Tessera, Inc. Microelectronic connections with solid core joining units
US5931371A (en) * 1997-01-16 1999-08-03 Ford Motor Company Standoff controlled interconnection
US5841198A (en) * 1997-04-21 1998-11-24 Lsi Logic Corporation Ball grid array package employing solid core solder balls
JP3420917B2 (ja) * 1997-09-08 2003-06-30 富士通株式会社 半導体装置
US6002168A (en) * 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US6303408B1 (en) * 1998-02-03 2001-10-16 Tessera, Inc. Microelectronic assemblies with composite conductive elements
US6271111B1 (en) * 1998-02-25 2001-08-07 International Business Machines Corporation High density pluggable connector array and process thereof
US6324754B1 (en) * 1998-03-25 2001-12-04 Tessera, Inc. Method for fabricating microelectronic assemblies
US6158644A (en) * 1998-04-30 2000-12-12 International Business Machines Corporation Method for enhancing fatigue life of ball grid arrays
US6076726A (en) * 1998-07-01 2000-06-20 International Business Machines Corporation Pad-on-via assembly technique
US6184062B1 (en) * 1999-01-19 2001-02-06 International Business Machines Corporation Process for forming cone shaped solder for chip interconnection
TW445612B (en) * 2000-08-03 2001-07-11 Siliconware Precision Industries Co Ltd Solder ball array structure to control the degree of collapsing
US6610591B1 (en) * 2000-08-25 2003-08-26 Micron Technology, Inc. Methods of ball grid array

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087597A (en) * 1994-07-22 2000-07-11 Nec Corporation Connecting member and a connecting method with ball and tapered via

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