CN1720516A - Cellular engine for a data processing system - Google Patents
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Abstract
The invention relates to a data-processing system (102) which includes an associated memory device (104) comprising a plurality of units, wherein, each one of the plurality of units comprises a processing circuit (130). One of a plurality of instructions is sent to the associated memory device (104) through a controller (100) while a synchronous clock signal consisting of a clock period with a predetermined amount is outputted by a clock device (106) each second. The clock device (106) outputs the synchronous clock signal to the associated memory device (104) and the controller. The controller transfers one of a plurality of instructions to all the units wholly at the same time within one clock period.
Description
The cross reference of related application
The application requires the right of priority of No. 60/431,154, the U.S. Provisional Application of " ENHANCED VERSIONOF CONNEX MEMORY (the enhancement mode connection storer) " by name submitted on Dec 5th, 2002, and its full content is incorporated into herein, for your guidance.The pending trial U.S. Patent application 09/928 that the application's theme relates to August 10 calendar year 2001 " A MEMORY ENGINE FOR THEINSPECTION AND MANIPULATION OF DATA (being used to check the memory engine with manipulation data) " by name of submitting to, " the DATA PROCESSING SYSTEM FOR A CARTESIANCONTROLLER (data handling system that is used for Cartesian controller) " by name that submits in No. 151 and on Dec 4th, 2003, the content of these two patented claims is all incorporated into herein, for your guidance.
Technical field
The present invention relates generally to a kind of engine that is used for data handling system, and be specifically related to a kind of cellular engine (cellular engine) that is used for data handling system, described data handling system realizes the active content-addressed memory (CAM) or the engine that links, to improve data processing speed and efficient.
Background technology
Robotization or semi-automatic data handling system all are integrated package in multiple application.Usually, data management system is embedded in the large-scale computerized equipment or system, and such as providing auxiliary and convenient by carrying out necessary Arithmetic Operator, data conversion or the like to the application that those operate in the mainframe computer system.
Just as known, basic data handling system can be categorized as single instrction, single data stream (SISD) device, and typically use processor, interface and storage arrangement with their the simplest expression-forms.The task (directed task) of guidance is carried out in the instruction that another assembly of described processor response user or total system is imported.In the task process of carrying out its appointment, described processor relies on interface to the order of memory transfer such as request of data, and receives the specific data that is stored in the storage arrangement by this interface.
The given data disposal system is mostly used the storage arrangement of conventional addressing.That is to say that known data system has used the storage arrangement that comprises the defined local family of languages (locale) therein, each local family of languages all has its oneself special address.In such a way, last numerical value adds the numerical value that is stored on the B of address if processor wishes to be stored in address A, this storage arrangement will before forward specific position of addressing or unit in the storer to, and via interface these numerical value are passed to the suitably processor of summation take place.In this type systematic, the characteristic of integrated package and function, just the characteristic of processor and storage arrangement and function all are univocal and are mutually different.Fig. 1 has depicted the known data handling system of this class, and processor 2 responses are therein operated via the task of incoming line 4 inputs.Thereafter, the instruction that utilizes interface 6 to transmit such as request of data to storage arrangement 8, and receive the specific data that is stored in the storage arrangement 8 whereby.
Simultaneously, it is also known that: data handling system can comprise more than one processor and storer, and further, described these a plurality of assemblies can be parts of carrying out the system of multiple instruction flow.These multiple-instruction-stream multiple-data stream (MIMD) device can be regarded as the large set of tight coupling SISD device, though each processor and other integrated processor overall coordination work in the system therein is responsible for the specified portions of big task.That is to say that the usefulness of MIMD device is subject to those specific occasions (arenas) usually, here, problem to be solved is suitable for being broken down into a plurality of similar relatively independent again subproblems.The characteristic of those integrated packages of MIMD device and function equally also are univocal and different.
Another kind of known data handling system comprises single instruction stream multiple data stream (SIMD) device.These SIMD devices have used the processor of any amount, all carry out same program in mode synchronized with each other, but all that present instruction is the specified operational character of each processor acts on different operands and produces its oneself result thus.Processor access integrated memory in the SIMD device is to obtain operand and event memory.Equally, the characteristic of those integrated packages of SIMD device and function all are univocal and different, are by possessing certain type visit of storer to be carried out with the processor of finishing its operation because calculate.
Therefore although known data handling system can be handled lot of data, the defined and constant characteristic limitations of processor and storage arrangement can finish the speed and the efficient of various operations.
In addition, also constructed the various structure of other class storeies that use unconventional addressing.Usually, these storeies are called " (associative) links " storer, and as indicated, these storeies are not to come these data bit catalog (catalog) by the position of each data bit in storer.On the contrary, content-addressed memory (CAM) is by wherein the characteristic or the intrinsic property of institute's canned data come their data bit is carried out " addressing ".That is to say that the data in the content-addressed memory (CAM) are not that the title by their positions identifies, but identify according to the attribute of the data in each discrete cell that is stored in storer.
In most of content-addressed memory (CAM) devices, to whole key fields of storing data additional fastening size.Then, a particular data field or a plurality of data field that can utilize search key from the content-addressed memory (CAM) device, to select key field that it added and this search key to be complementary, and no matter follow-up processing why, is carried out for the instruction according to appointment in the position of its name.
Therefore, although the embodiment of content-addressed memory (CAM) is known, but these devices always are used as the dedicated block or the assembly of known data handling system inside, and described known data handling system has adopted the storer of processor, interface and the conventional addressing of standard.That is to say that although known content-addressed memory (CAM) does not adopt conventional addressing agreement, they self can not rely on known processor and external memory storage and to come process information with known SISD, SIMD and the corresponding to mode of MIMD structure.
With the forgoing problems and concerns in mind, therefore the present invention attempts by using the active content-addressed memory (CAM) that a kind of engine that is used for data handling system that overcomes above-mentioned defective is provided, described active content-addressed memory (CAM) uses variable-sized key word, by not only serving as processor but also serve as storer selectively, independently storage block needn't be visited in its each unit when carrying out their operation, therefore shortened processing, calculating and call duration time in fact.
Summary of the invention
An object of the present invention is to provide a kind of active data disposal system.
Another importance of the present invention is, a kind of cellular engine that is used for data handling system is provided, and it realizes the initiatively content-addressed memory (CAM) or the engine apparatus that links according to the mode that improves data processing speed and efficient.
Another importance of the present invention is, a kind of cellular engine that is used for data handling system is provided, it realizes the initiatively content-addressed memory (CAM) or the engine apparatus that links, by not only serving as processor but also serve as storer selectively, initiatively, storage block needn't be visited independently so that finish their operation in each unit of the described active content-addressed memory (CAM) or the engine apparatus that links.
Another importance of the present invention is, a kind of cellular engine that is used for data handling system is provided, it realizes the initiatively content-addressed memory (CAM) or the engine that links, each unit of the described active content-addressed memory (CAM) or the engine that links can be provided with according to the instruction of propagating or inquiry by the overall situation they separately state handle given instruction selectively.
Another importance of the present invention is, a kind of cellular engine that is used for data handling system is provided, it realizes the initiatively content-addressed memory (CAM) or the engine that links, each unit of the described active content-addressed memory (CAM) or the engine that links, can be all within the single clock period according to they states separately, parallel processing designated order selectively.
Another importance of the present invention is to provide a kind of cellular engine that is used for data handling system, the Initiative Inventory Management apparatus or the cellular engine of its realization permission use variable-length key field.
Another importance of the present invention is, a kind of cellular engine that is used for data handling system is provided, it realizes Initiative Inventory Management device or cellular engine, described Initiative Inventory Management device or cellular engine are isomorphisms, thus during executive routine, allow the different time being stored in identical message block in the storer as key field or data field (a part).
Another object of the present invention is, a kind of cellular engine that is used for the active data disposal system is provided, and it makes the dynamic qualification (dynamic limitation) that can carry out the search volume in the active content-addressed memory (CAM).
Another object of the present invention is, a kind of cellular engine that is used for the active data disposal system is provided, and it provides the selectable accessibility to the arbitrary end of cell array.
Another object of the present invention is, is provided for the engine of active data disposal system, and it can regulate the data transmission between two or more unit in the content-addressed memory (CAM).
According to one embodiment of present invention, a kind of data handling system comprises the content-addressed memory (CAM) that contains n unit, and each in n unit all comprises a treatment circuit.Utilize controller to send in many instructions one to content-addressed memory (CAM), and the synchronizing clock signals that utilizes the output of clock apparatus per second to form by the clock period of predetermined number.Described clock apparatus is exported synchronizing clock signals to content-addressed memory (CAM), and described controller side by side passes to all n unit with one in many instructions in a clock period therein globally.
Consider instructions, claim and accompanying drawing by integral body, these and other purpose of the present invention and their preferred embodiment can become clear.
Description of drawings
Fig. 1 is the block diagram that illustrates known SISD data processing structure.
Fig. 2 is the block diagram that a general configuration of according to an embodiment of the invention, data handling system is shown, and described data handling system comprises memory engine and synchronous clock element.
Fig. 3 is the more detailed block diagram that the memory engine shown in Fig. 2 is shown.
Fig. 4 is the block diagram that the structure of according to an embodiment of the invention, unit or treatment element is shown.
Fig. 5 is the block diagram that the structure of code converter is shown.
Embodiment
Fig. 2 has depicted the structural relation between controller 100 (hereinafter being called Cartesian controller (CC)) and the cellular engine 102 (hereinafter be called and connect engine (CE)).Utilize synchronous clock circuit 106 to coordinate the operation of CC 100 and CE 102, so that can send in many instructions and send CE 102 to, for executed in parallel and processing by CC100.
The clock period that described clock circuit 106 per seconds can be exported predetermined number, and described CC100 can carry out built-in function, CC 100 can carry out a kind of in the multiple built-in function like this, sends in many instructions one to CE 102 concurrently simultaneously in the single clock period.
As in Fig. 3, depicting, described CE 102 is made up of the array of active cell or treatment element, and be embodied in the RAM (random access memory) that connects storer (CM) 104 and comprise a plurality of vectors 108, each vector all has the memory capacity identical with CM 104, and therefore can store the full content of CM 104 selectively.That is to say that described CE 102 comprises CM 104 with n unit and the vector memory 108 that is associated, it is under the control of the CC 100 of serial.In one embodiment of the invention, as will be the more detailed argumentation after a while, the purposes of memory vectors 108 be make it possible to carry out on open ended character string is longer in than CM 104 the character string that search is searched, insertion and deletion action, and be used to provide cheaply embodiment and reduce power consumption.
Should be appreciated that under the prerequisite that does not break away from aspect the broad model of the present invention, the present invention will cover such situation, CE 102 can have the configuration of any amount of particular electrical circuit, as long as CC100 can give an order and receives data there from it to CE 102.
With reference to figure 3, each the n bit location among the CM 104 all comprises column register down:
' mark '---1 flag register;
' w '---master register, it is playing the part of the role of totalizer in the similar conventional design, and simultaneously it also is associated with many general-purpose registers that quantity equals the memory vectors number.
Mark: establishing x is the bit field of length m, and y is the bit field of length n, and then: { x, y} represent by y being added to the bit field of the last length m+n that constitutes of x.This mark can be generalized to any amount of bit field, for example, to the bit field of three variablees: { a, b, c}={a, { b, c}}={{a, b}, c}
Suppose that r is (n+1) bit register and n 〉=k 〉=0, then: r[k] expression from right-hand member (k=0) to left end (k=n) begin several r (k+1) position.
Suppose that r is (n+1) bit register and n 〉=m＞k 〉=0, then: r[m:k] expression length m-k+1 bit field, r[m], r[m-1] ..., r[k] }.
Therefore, the content of the m bit location in CM 104 is the content that the content of its w register adds its mark register:
Unit [m-1:0]={ mark, value}
Numerical value [m-2:0]={ ext, symbol}
Symbol [m-3:0]
Wherein ext represents extension bits, is used for creating the alphabet of special value (for the situation of ext=1).
An importance of the present invention is: the ability of the active process data except that the storage data of each the m bit location in the CM 104.The processing of data can occur in each m bit location inside, and perhaps the processing of data takes place in left side by influencing scheduled unit or right side next-door neighbour's unit.Should be noted that: by improving the functional of each m bit location in the CM 104 in such a way, the present invention shows system-level behavior, just more complicated behavior, and surpassed the performance of other data handling system.
Another importance of the present invention is: the ability of each unit by will " mark " partly realizes the ability of the active process data of the cell level in the CM 104, this is the part of conditioned disjunction attribute, it is appointed as adjacent cells in itself or the CM 104 will be executed the task subsequently or the unit of executable operations number.
Turn back to Fig. 3, for purpose of the present invention, if one internal element register mark=1 then is considered as the unit " mark ", if mark=0 then be considered as " unmarked ".In addition, described CM104 has " the left boundary " and " right boundary " that can dynamically be regulated by sending special instruction.In addition, CM 104 " search volume " is the segmentation (segment) by the CM 104 of left boundary and the description of right boundary.Be appreciated that internal element register mark can be greater than one aspect length under the prerequisite that does not break away from aspect the broad model of the present invention.
Just as mentioned previously, the execution that offers the code of CE 102 is driven by CC 100.Described CE 102/CC 100 interfaces have used four special registers, as shown in Figure 3:
' INR ' 112---data input register---, and their (immediately) data variable (if any) all is provided from INR (being provided by CC 100) in all CE 102 instructions;
' OUTR ' 114 is according to output---comprise " unmarked " position and numerical value.If one of them unit is labeled, then OUTR comprises 0, and first contained numerical value in indexing unit is followed in the back; Otherwise OUTR comprises 1, and the special value relevant with embodiment followed in the back, such as 11...1;
' OPR ' 116---order register, and it comprises the operational code (this source is the specific field in CC 100 instructions) of current C E 102 instructions;
' VAR ' 118---be used for the address register of vector memory.Described VAR 118 registers are to be upgraded by specific CC 100 instructions, and are used as the variable of the instruction of explicit operation vector; Described VAR 118 registers also are used in to carry out and relate in all operations of the general-purpose register that is associated with the unit.
As further in Fig. 3, representing, can utilize input/output line 120 to visit the two ends of CM 104 selectively.As used herein, described input/output line 120 has following meanings:
' left_in ' 122={w, mark, eq, first}, all are 0 (eq=1 are meant that two operands in the unit equate as acquiescence; First=1 is meant that described unit is first unit of mark);
' left_out ' 124={w, mark, eq, first} is from first unit;
' right_in ' 126={w, mark, eq, first}, all are 0 as acquiescence;
' right_out ' 128={w, mark, eq, first} is from last unit.
Fig. 4 shows an embodiment of the inner structure of the m bit location in the CM 104.As shown in Figure 4, the inner structure of each unit all comprises column circuits down:
ALU: arithmetic logical unti 130, it carries out addition, subtraction, comparison and logic function by turn
LeftMux: multiplexer 131, it selects to be used for the left operand of ALU from following:
W: be stored in the numerical value in the accumulator register 134
In: the numerical value that in input register 112c, receives
MemOut: the numerical value that from vector memory, reads by vector address register VAR 118 addressings
AluMux: multiplexer 133, its selection from following will be loaded into the numerical value in the accumulator register (w 134):
W: be stored in the numerical value in the accumulator register 134
FromLeft: be stored in the numerical value in the accumulator register of left cell
FromRight: be stored in the numerical value in the totalizer of right sided cell
The output of ALU 130
W: accumulator register 134
Mark: flag register
Tristate output buffer
DECODE: combinational circuit 137, it is according to being come instruction is deciphered by the local environment of following generation:
LocalFlags: produce by ALU
LeftFlags: the sign that is received from left cell
RightFlags: the sign that is received from right sided cell
Class_i: the classification code that is received from TRANSCODER (code converter)
TRANSCODER produces:
The command code that is used for leftMux, rightMux, ALU, aluMux, mark, three-state buffer
Sign from adjacent unit
The state_i position that is used for the unit of TRANSCODER
Code converter
Fig. 5 shows the tissue of TRANSCODER (code converter), and it is with the integrated circuit of CE 102 and serves as a part of controlling interconnection network.That is to say, utilize TRANSCODER, according to following content:
Its mode bit (state i), (being local state)
The mode bit of all unit (being global state)
The present instruction that will carry out,
Following classification is assigned in each unit:
Indexing unit
First is indexing unit
Last is indexing unit
Unit in compass (this boundary is stored in the memory block of TRANSCODER)
Active cell.
Be appreciated that under the prerequisite that does not break away from aspect the broad model of the present invention, other unit classification can be added in the above-mentioned classification.
Described TRANSCODER from each unit the accepting state position (state_0, state_1 ..., state_ (n-1)), and will specify 3 all kinds of codes that it belongs to (class_0, class_1 ..., class_ (n-1)) send back to each unit.
The tectonic block of code converter (building block) is:
OR toe-in (Prefixes): the main circuit 140 that comes the relative position of computing unit according to the classification that will carry out
Boundary storer: be used to store two latchs 141 about the information of described boundary
MUXs: multiplexer 142, it selects the class of each unit according to present instruction
Can realize TRANSCODER by following two kinds of different modes, so that its size of optimization and speed:
The linear version that is used for little n value
(being used for big n value) two-dimentional version, it comprises LINE TRANSCODER and COLUMN TRANSCODER, and each all has the size of O (n1/2) magnitude.
Therefore, another importance of the present invention is this ability of CC 100: CC 100 gives an order to CE 102, and makes the instruction of this class be broadcast to all unit in the CM 104 concurrently in the single clock period.For example, those meet the unit of the standard that set by the instruction from CC 100, can in the identical clock period, carry out mark to self independently and selectively simultaneously, thus, in the back in the clock period, can in the single clock period, carry out follow-up instruction or operation once more concurrently according to this classification results.
Therefore, another importance of the present invention is: TRANSCODER (code converter) not only according to its local state (for example, it is mark or unlabelled state) classified in each unit, but also come to be classified in each unit according to its global state and present instruction.That is to say, the local state that may be discrete cell when an aspect of the unit classification of being undertaken by TRANSCODER (code converter) is " mark ", but it is also important that for this class unit and will " know " its " global state " with respect to all other unit, is " first is mark " unit or " last is mark " unit such as the unit of " mark ".
By an example, suppose in the clock period formerly, via attribute, these unit in the CM 104 have been carried out following mark: (the runic numeral is used in the unit of mark in this string) from some pointed unit of the instruction of CC 100:
CM：2?5?2?7?6?4?10...
Suppose that next will instruct " addr 5 " to be broadcast to all unit in the CM 104 again concurrently, wherein the vector 5 in the vector memory 108 is as follows in the single clock period:
The 5th row: 347825 12...
So all in the CM 104 will be added the content of their data field in the content of the corresponding element in the vector 5 unit of mark, consequently this operation is stored in each unit of CM104, and is as follows:
CM：5?9?2?7?6?9?10...
As top example was described, the mark/unmarked state of each unit in the CM 104 (was not referred in this example by the influence of the specific instruction sent by CC 100; Although just as mentioned, some instruction may influence the state of the mark of each unit in the CM 104).In addition, all additive operations all (be that is to say parallel ground) by side by side and carry out in the indexing unit at each in the single clock period.
As further illustrating in the above example, data handling system of the present invention can realize the operation of the vector definition of logarithm value on system-level; In this example, vector value is the vector 5 of CM 104 data and vector memory 108.In this, data handling system of the present invention comprises: have the CE of the CM 104 of the active cell of having (that is, treatment element) linear array, wherein each unit in the CM 104 all has one or more marker bits and a totalizer (134); Meanwhile, on the rank of each unit, can see the corresponding element of all vectors as one group of register that is associated.(number of the register that therefore, is associated equals the number of vector 108).
In addition, another importance of the present invention is: link by the independent related register that makes each unit in each totalizer and the CM 104 respectively respectively, data handling system of the present invention provides the operation of logarithm value vector, but realization matrix calculates or the like thus.
Compare with the MIMD system with the SIMD that is discussed in background technology of the present invention, data handling system of the present invention does not rely on the constant and strict description between the operation of processor and the storage arrangement that is linked.
In data handling system of the present invention, can store and be used for the message of searching for, but not be with conventional " storage address " notion at CM 104; Although each unit self in the CM 104 can respond order that the overall situation sends process information selectively, itself is not a processor, but such just as previously discussed, and each unit in the CM 104 all comprise treatment circuit; And the performance of data handling system of the present invention is the linear function of its size strictly, and it can be by mode that other known programmable machine had not showed and be applicable to the programs/applications of wide region.
Be appreciated that aspect the characteristic of the treatment circuit that is comprised in each unit in the n of data handling system of the present invention in CM 104 unit and the configuration unrestricted.
According to the present invention, described CE 102 has abundant instruction set, is divided into groups by following class:
Global administration's instruction---the setting and the replacement of CM 104 boundaries; Swap data between CM 104 and RAM vector 108;
Search/access instruction---the visit that links that one or more unit of CM 104 are carried out;
The mark control command;
Data storage and move instruction;
The arithmetic sum logical order;
Conditional order; With
Index.
Attention: all instructions that are used for CE 102 are all carried out in the cycle at individual machine.
It self does not possess described CE 102 program storage is conducted interviews to take out the access right of its instruction---and each cycle, the operational code of obtaining in the special register was all waited in its unit, but it will adopt different entities, in this example, utilize CC 100 to come to do this for them; Described code for order and need individual access point with its taking-up.Therefore, the groundwork of described CC 100 is exactly the program implementation that drives CE 102, that is, and and the instruction that taking-up will be carried out by independent unit, and place them in the internal register; Simultaneously, it serves as the gateway of CE 102 and therefore is responsible for all I/O mutual.Described CC 100 also carries out simple sequential operation, then it can not write significant code for this class machine as if the words that do not have described operation: a class of this generic operation is exactly so-called " control primitive ", it is the instruction of those decision sequence (for example, if, while, repeat or the like) that are used to encode.
False code
Hereinafter, utilize false code to come the semanteme of the major part instruction of regulation CE 102 off the record, false code is used a kind of mark that inspired by the c program design language.Be appreciated that this explanation is not to limit the actual expression that realizes of instruction, but the present invention has also imagined other expression.
Special-purpose pseudo-statement forall describes the action by unit group executed in parallel; Its syntax can be expressed as:
·<forall?statement>∷＝forall[(<forall?condition>)]<statement>；
·<forall?condition>∷＝marked
|in?searchSpace；
Consider following three kinds of variations of forall:
1.forall
<action>；
2.forall(in?searchSpace)
<action>；
3.forall(marked)
<action>；
On the rank of each unit, carry out the title that all instruct needed complete data set to use in false code together with them, be:
The register of unit (comprising the register that is associated), i.e. w, mark, r0, r1 ..., rN; With
The content of unit the right and left adjacent cells promptly is respectively right_w, right_mark and left_w, left_mark.
Simultaneously, can on the unit rank, estimate prediction to first_mark and last_mark; The former is true to the indexing unit of the leftmost side among the CM, and the latter is true for the indexing unit of the rightmost side.
Global administration's instruction
Ldl＜value 〉: instant load rows (load line immediate); According to reduce the content of all CM unit (mark and w register) by the selected memory vectors of numerical value that the input of VAR is produced:
CM＝RAM[VAR]；
Stl＜value 〉: instant storage line (store line immediate); The content (mark and w register) of all CM unit is saved in the selected memory vectors of numerical value that is produced by the input to VAR:
RAM[VAR]＝CM；
Llim: left boundary (left limit); The left boundary of search volume is set to first indexing unit.Do not influence mark.Notice that described left boundary is searched for/unit, the leftmost side of the influence of access instruction.
Rlim: right boundary (right limit); The right boundary of search volume is set to first indexing unit.Do not influence mark.Notice that described right boundary is the unit, the rightmost side that is subjected to the influence of basic search/access instruction.
Droplim: deletion boundary; Left boundary is set to the CM unit of the leftmost side, and right boundary is set to the CM unit of the rightmost side.Do not influence mark.
Search/access instruction
Attention: all instructions of describing in this section are only moved in the compass of search volume; Variable is a m-1 bit value available in input register (INR).
Find＜value 〉: identify the unit that all have the numerical value that equals described variable.For each unit, the marker bit of adjacent unit, its right side is set to 1 when finding coupling; All other marker bit is set to 0:
forall(in?searchSpace)
mark＝(left_w＝＝INR)？1:0；
Match＜value 〉: will be stored in all the numerical value in the indexing unit compare with described variable.If find coupling in the unit of appointment, then just the marker bit of the following units is set to 1; All other marker bit is set to 0:
forall(in?searchSpace)
mark＝(left_mark?&&?left_w＝＝INR)？1:0；
Lfind＜value 〉: search left and mark (find and mark left); Identify the unit that all have the numerical value that equals described variable.For each unit, the marker bit of adjacent unit, its left side is set to 1 when finding coupling; All other marker bit is set to 0:
forall(in?searchSpace)
mark＝(right_w＝＝INR)？1:0；
Lmatch＜value 〉: mate left and mark (match and mark left); Be stored in all the numerical value in the indexing unit compare with described variable.If find coupling in the unit of appointment, then the marker bit of the unit of front is set to 1; All other marker bit is set to 0:
forall(in?searchSpace)
mark＝(right_mark?&&?right_w＝＝INR)？1:0；
Markall: all unit in the mark search volume:
forall(in?searchSpace)
mark＝1；
Addmark＜value 〉: all comprise the unit of the numerical value that equals described variable mark; Do not influence other mark:
forall(in?searchSpace){
if(w＝＝INR)
mark＝1；
}
Mark＜value 〉: all comprise the unit of the numerical value that equals described variable mark; All other marker bit is set to 0.
forall(in?searchSpace)
mark＝(w＝＝INR)？1:0；
Clr＜value 〉: remove the marker bit that all comprise the unit of the numerical value that equals described variable.
forall(in?searchSpace){
if(w＝＝INR)
mark＝0；
}
The mark control command
Clrf: remove first; Remove first (that is the leftmost side) mark.
forall{
if(first_mark)
mark＝0；
}
Trace: never mark left.
forall{
if(right_mark)
mark＝1；
if(mark)
mark＝1；
}
Keepl: keep last; Underlined except removing institute outside last (that is the rightmost side) one.
forall{
if(！last_mark)
mark＝0；
}
Clrl: remove last; Remove last (that is the rightmost side) mark.
forall{
if(last_mark)
mark＝0；
}
Left: with the underlined mobile to the left unit of institute.
Forall
mark＝right_mark；
Right: with the underlined mobile to the right unit of institute.
forall
mark＝left_mark；
Cright: with good conditionsi moving to right; With the underlined mobile to the right unit of institute,, and replace this numerical value with 11...1 in such cases unless adjacent unit, their right sides comprises the numerical value that equals described variable.
forall{
if(left_mark?&&?w＝＝INR){
mark＝0；
w＝11...1；
}
if(left_mark?&&?w！＝INR)
mark＝1；
if(mark)
mark＝0；
}
Cleft: with good conditionsi moving to left; With the underlined mobile to the left unit of institute,, and replace this numerical value with 11..1 in such cases unless their adjacent unit, left side comprise the numerical value of appointment.
forall{
if(right_mark?&&?w＝＝INR){
mark＝0；
w＝11..1；
}
if(right_mark?&&?w！＝INR)
mark＝1；
if(mark)
mark＝0；
}
Data storage and transfer instruction
Nop: do not have operation:
Reset＜value 〉: store the numerical value in all unit.Do not influence mark.
forall
w＝INR；
Get: will be stored in first the numerical value in the indexing unit send to CM output, and its mark position that moves right.Do not influence other mark.
forall{
if(first_mark){
OUTR＝w；
mark＝0；
}
if(left_mark?is?first_mark)
mark＝1；
}
Back: will be stored in first the numerical value in the indexing unit send to CM output, and its mark is moved to the left a position.Do not influence other mark.
forall{
if(first_mark){
OUTR＝w；
mark＝0；
}
if(right_mark?is?first_mark)
mark＝1；
}
Set＜value 〉: store first numerical value in indexing unit.Do not influence mark.
forall(marked){
if(first_mark)
w＝INR；
}
Setall＜value 〉: store all numerical value in the indexing unit.Do not influence mark.
forall(marked)
w＝INR；
Ins＜value 〉: insert numerical value before the unit of mark at first.The content of all unit on right side, insertion point is shifted a position to the right.Attention: in this process, the numerical value that is kept at first in the unit, the rightmost side is lost.
forall{
if(right?of?first_mark)
w＝left_w；
if(first_mark)
w＝INR；
mark＝left_mark；
}
Del: deletion is stored in first numerical value in indexing unit.Described unit keeps the state of mark, and the content that will delete all unit on some right sides shifts a position left.
forall{
if(first_mark)
w＝right_w；
if(right?of?first_mark){
w＝right_w；
mark＝right_mark；
}
}
Cpr: duplicate to the right; For all unit of mark, whole unit content (w register and mark) is copied to adjacent unit, right side.
forall{
if(left_mark)
w＝left_w；
mark＝left_mark；
}
Cpl: duplicate left; For all unit of mark, whole unit content (w register and mark) is copied to adjacent unit, left side.
forall{
if(right_mark)
w＝right_w；
mark＝right_mark；
}
Ccpr＜value 〉: with good conditionsily duplicate to the right; For all unit of mark, the numerical value that is kept among the register w is copied to adjacent unit, right side; Also never mark is unless store the numerical value that equals described variable in the w register.
forall{
if(left_mark?&&?left_w！＝INR){
w＝left_w；
mark＝1；
}
else
mark＝0；
}
Ccpl＜value 〉: with good conditionsily duplicate left; For all unit of mark, the numerical value that is kept among the register w is copied to adjacent unit, left side; Also never mark is unless store the numerical value that equals described variable in the w register.
forall{
if(right_mark?&&?right_w！＝INR){
w＝right_w；
mark＝1；
}
else
mark＝0；
}
Ld＜address 〉: the instant loading; For all unit of mark, will be kept at register＜r〉in numerical value be loaded in the w register, with a part as the selected RAM vector of numerical value that produces by input to VAR.
forall(marked)
w＝<r>；
St＜address 〉: instant storage; For the unit of mark, the numerical value that is kept in the w register is moved to register＜r for all 〉, with a part as the selected RAM vector of numerical value that produces by input to VAR.
forall(marked)
w＝<r>；
The arithmetic sum logical order
All arithmetic instructions all are that the m-2 bit digital represented with 2 complement code is carried out: operand＜op〉be one of them location register that is associated (part of the selected RAM vector of numerical value that produces by input) to VAR, or the m-2 bit digital that provides by controller:
＜op〉∷=INR[m-3:0] (instant numerical value) | r (RAM vector element)
Add＜op 〉: operand is added to all in the w register of indexing unit.Do not influence mark.
forall(marked)
w+＝<op>；
Fadd＜op 〉: add fully, wherein the right side expansion is worked as carry (referring to add).
forall{
if(mark)
w+＝(<op>+right_w[m-2])；
if(left_mark)
w[m-2]＝0；
}
Sub＜op 〉: deduct operand value in the numerical value the w register of indexing unit from being stored in all.Do not influence mark.
forall(marked)
w-＝<op>；
Fsub＜op 〉: deduct fully, wherein the right side expansion is worked as carry (referring to sub).
forall{
if(mark)
w-＝(<op>+right_w[m-2]))；
if(left_mark)
w[m-2]＝0；
}
Half[＜op 〉]: for all unit of mark, with the register manipulation number divided by 2 and the result is stored in the w register.Do not influence mark.
forall(marked)
w＝{<op>[m-2:m-3]，<op>[m-3:1]；
Fhalf[＜op 〉]: complete half; For all indexing units, the register manipulation number divided by 2 and the result is stored in the w register, if the least significant bit (LSB) of left cell is 1, is then added to 100..0 wherein.Do not influence mark.
forall(marked)
w＝{<op>[m-2]，left_w[0]，<op>[m-3:1]；
Lt＜op 〉: less than (or equaling); For all unit of mark, check whether register w holds and be less than or equal to be kept at＜op〉in the value of numerical value; If w＜op, then the w extension bits is set to 1; If op＞w, then this marker bit is set to 0.
forall(marked){
if(w＜<op>)
w[m-2]＝1；
if(w＞<op>)
mark＝0；
}
Flt＜op 〉: complete lt; For all unit of mark, when w＜op or its adjacent unit, left side have when being set to 1 w extension bits, this extension bits is set to 1; Remove the left side extension bits, and if w＞op, then also remove this mark.This instruction was used in conjunction with when test, a plurality of continuous unit was compared being used for.
forall{
if(mark?&&?(w＜<op>‖left_w[m-2]))
w[m-2]＝1；
if(right_mark)
w[m-2]＝0；
if(mark?&&?w＞op?&&！left_w[m-2])
mark＝0；
}
Gt＜op 〉: greater than (or equaling); For all unit of mark, check whether register w has more than or equal to being kept at＜op〉in the value of numerical value; If w＞op, then the w extension bits is set to 1; If w＜op, then this marker bit is set to 0.
forall(marked){
if(w＞<op>)
w[m-2]＝1；
if(w＜<op>)
mark＝0；
}
Fgt＜op 〉: for all unit of mark, when w＞op or its adjacent unit, left side have when being set to 1 w extension bits, this extension bits is set to 1; This left side extension bits is eliminated, and if w＜op, then also remove this mark.This instruction was used in conjunction with when test, a plurality of continuous unit was compared being used for.
forall{
if(mark?&&(w＞<op>‖left_w[m-2]))
w[m-2]＝1；
if(right_mark)
w[m-2]＝0；
if(mark?&&w＜op?&&！left_w[m-2])
mark＝0；
}
Test: for all indexing units that comprises the numerical value that equals INR, marker bit is set to 0, and if the extension bits of left cell be 1, be 11..1 and the extension bits of removing left cell then with register w assignment.
forall{
if(right_mark?&&?right_w＝＝INR)
w[m-2]＝0；
if(mark?&&?w＝＝INR?&&?left_w[m-2])
w＝11...1；
else?if(mark?&&?w＝＝INR)
mark＝0；
}
And＜op 〉: step-by-step with; For all unit of mark, register w and＜op＞between carry out step-by-step with.Do not influence mark.
forall(marked)
w&＝<op>；
Or＜op 〉: step-by-step or; For all unit of mark, register w and＜op between carry out step-by-step or.Do not influence mark.
forall(marked)
w|＝<op>；
Xor＜op 〉: the step-by-step XOR; For all unit of mark, register w and＜op between carry out the step-by-step XOR.Do not influence mark.
forall(marked)
w^＝<op>；
Conditional order
Operand register＜r are used in following two instructions〉(part of the selected RAM vector of numerical value that produces by input) and the m-1 bit value that comes from INR to VAR.
＜r〉∷=w (being used for register w) | r (RAM vector element)
Cond＜value〉[＜r 〉]: whether for all unit of mark, checking has at least one to be set to 1 carry out the step-by-step AND-operation between two operands after.
forall(marked)
mark＝((<r>&INR)！＝0)？1:0；
Ncond＜value〉[＜r 〉]: for all unit of mark, check whether the result who carries out the step-by-step AND-operation between two operands is 0.
forall(marked)
mark＝((<r>&INR)＝＝0)？1:0；
Indexed instruction
Index:, be the numerical value of unit with respect to the relative position of unit, the CM leftmost side (it has index 0) with register w assignment for all unit of mark.
As can seeing from above-mentioned instructions and accompanying drawing, the present invention provides the novel method of deal with data in such a way, and described mode just provides the processing power of enhancing, and significantly reduces processing time, silicon area and power consumption.Such just as discussed, data handling system of the present invention provides the instruction of any appointment and the operand that will transmit thereof to each CM unit concurrently, and described instruction is carried out in described each CM unit in the identical clock period.
The inherent advantage of another of data handling system of the present invention just is: each unit in the cellular engine not only executes instruction in the single clock period simultaneously, but also those carry out the ability of these unit of overall broadcasting instructions by utilizing local state information and global state information to come dynamic constraints.Specifically, by usage flag position on independent unit rank, the actual cell in the content-addressed memory (CAM) can influence those unit on indexing unit left side or right side in a kind of unknown up to now mode.Therefore, on system level, the present invention that is to say by the mechanism of linking, and the characteristic of the content by each unit in the CM 104 or attribute but not wherein specific assigned address address provide and selectively activated or the change of flag state.
Therefore, the present invention will handle with storer on very contiguous rank and be made up, and this means: storage block need not visited independently so that finish its operation in the independent unit of CM 104.In addition, operand resides on cell level in their local space, therefore makes the result keep motionless, thereby has saved communication and processing time, silicon area and power.
Should be noted that: some instruction operands is actually to be broadcasted away by CC 100 in overall broadcasting instructions.
Although the present invention has been described with reference to preferred embodiment, those skilled in the art will appreciate that under the situation that does not break away from essential scope of the present invention, can make various tangible changes, also can replace its element with equivalent.Therefore, the present invention does not want to be confined to disclosed specific embodiment, but the present invention includes the embodiment in all scopes that fall into claims.
Claims (82)
1. cellular engine that is used for data handling system, described engine comprises:
Data set with n unit, each in the described n unit can both be stored the m position;
The vector memory that comprises p vector, each in the described p vector all has the memory capacity of n * m position;
The control interconnection network, it comes in the described n unit each is classified according to each the local state in the described n unit;
Order register is used to receive the instruction that slave controller sends;
Clock apparatus is used for the synchronizing clock signals that per second output was made up of the clock period of predetermined number, and described clock apparatus is exported described synchronizing clock signals to described data set and described vector memory; And
Wherein said engine is in described clock period therein, side by side transmit described instruction globally to all described n unit, all in a described clock period, by each selected in described data set unit, according to each described classification in described n the unit that is undertaken by described control interconnection network, the described instruction of executed in parallel.
2. the cellular engine that is used for data handling system according to claim 1, wherein:
Described instruction is by all the described n unit executed in parallel in the described data set.
3. the cellular engine that is used for data handling system according to claim 1 further comprises:
The data interconnect network, it is connected respectively to each unit its right side adjacent cells and left side adjacent cells.
4. the cellular engine that is used for data handling system according to claim 1, wherein:
Described control interconnection network come in the described n unit each is classified according to each the local state and the global state of all described n unit in the described n unit.
5. the cellular engine that is used for data handling system according to claim 4, wherein:
In the described n unit each all comprises mode field and data field, and described mode field comprises and is used for marker bit that each local state of a described n unit is encoded; And
Wherein said marker bit is in a state in the flag state and unmarked state.
6. the cellular engine that is used for data handling system according to claim 5, wherein:
Described mode field is to utilize the machine-processed correct that links, and the described mechanism of linking is that the execution by the described instruction that belongs to the specific instruction subclass realizes.
7. the cellular engine that is used for data handling system according to claim 6, wherein:
Described data field is to revise by logic and the arithmetic instruction carried out in the described n unit according to the classification of each in described n the unit that is undertaken by described control interconnection network.
8. the cellular engine that is used for data handling system according to claim 3, wherein:
Described data interconnect network and described control interconnection network both are extendible.
9. the cellular engine that is used for data handling system according to claim 1, wherein:
Described data set is the content-addressed memory (CAM) device.
10. the cellular engine that is used for data handling system according to claim 9, wherein:
In described n the unit in the described content-addressed memory (CAM) device each comprises treatment circuit.
11. an engine that is used for data handling system, described engine comprises:
The storage arrangement that comprises n unit;
Controller is used for sending instruction to described storage arrangement selectively;
The local state of each in the unit sorter, itself and a described n unit is operated explicitly;
Clock apparatus is used for the synchronizing clock signals that per second output was made up of the clock period of predetermined number, and described clock apparatus is exported described synchronizing clock signals to described storage arrangement and described controller; And
Wherein said engine transmits described instruction to all n unit globally simultaneously in a described clock period; And
Wherein, carry out described instruction by selected each unit in the described storer according to the described local state of described n the unit that is pointed to by described unit sorter, the described execution of described instruction is simultaneous in each unit in a described clock period, in described selected each unit.
12. the engine that is used for data handling system according to claim 11, wherein:
Described instruction is to be carried out by all the described n in the described storage arrangement unit.
13. the engine that is used for data handling system according to claim 11, wherein:
Described storage arrangement is not conventional addressing.
14. the engine that is used for data handling system according to claim 11, wherein:
Described storage arrangement is the content-addressed memory (CAM) device.
15. the engine that is used for data handling system according to claim 11, wherein:
In the described n unit each all comprises treatment circuit.
16. the engine that is used for data handling system according to claim 15, wherein:
Described treatment circuit has totalizer.
17. the engine that is used for data handling system according to claim 11, wherein:
In the described n unit each all comprises the field with marker bit; And
Described local state reflects the flag state of described marker bit and a state in the unmarked state.
18. the engine that is used for data handling system according to claim 11, wherein:
The global state of a described unit sorter and a described n unit is operated explicitly; And
Wherein, described instruction is by each the selected unit in the described storage arrangement, carry out according to the described local state of described n the unit that is pointed to by described unit sorter and described global state, the described execution of described instruction is simultaneous in each unit in a described clock period, in described selected each unit.
19. the engine that is used for data handling system according to claim 18, wherein:
Determined by the described local state of all described n unit by the described global state that described sorter uses.
20. the engine that is used for data handling system according to claim 17, wherein:
Described instruction is only carried out in having those n unit of the described marker bit that is set to described flag state.
21. the engine that is used for data handling system according to claim 11, wherein:
In the described n unit each all comprises the field with a plurality of marker bits.
22. a data handling system, described data handling system comprises:
The content-addressed memory (CAM) device that comprises n unit, each in the described n unit all comprises the memory capacity of treatment circuit and m position;
Controller is used for sending of many instructions to described content-addressed memory (CAM);
Clock apparatus is used for the synchronizing clock signals that per second output was made up of the clock period of predetermined number, and described clock apparatus is exported described synchronizing clock signals to described content-addressed memory (CAM) device and described controller; And
Wherein said controller is in a described clock period, transmit in described many instructions one simultaneously to all described n unit globally.
23. data handling system according to claim 22 further comprises:
Sorter is used for selectively operating explicitly with each local state of a described n unit; And
One in wherein said many instructions by each the selected unit in the described content-addressed memory (CAM) device, described local state according to described n the unit that is pointed to by described sorter is carried out, generation simultaneously in the described execution of described instruction each unit in a described clock period, in described selected each unit.
24. data handling system according to claim 23, wherein:
In the described n unit each all comprises mode field and data field, described mode field comprises and is used for marker bit that each local state of a described n unit is encoded, indicates the flag state of each and a state in the unmarked state in the described n unit thus.
25. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " load lineimmediate " order, uses the indicated data of described " load line immediate " order to replace being in the content of all described n unit of described flag state whereby.
26. data handling system according to claim 25 further comprises:
The vector memory that comprises p vector, each in the described p vector comprises n element, and each in the described n element all has the m position; And
Order the described data of indication corresponding to one in the described p vector by described " load line immediate ".
27. data handling system according to claim 24 further comprises:
One in described many instructions of being sent by described controller is " store lineimmediate " order, and the content that will be in all described n unit of described flag state whereby is saved in described " store line immediate " orders in the indicated memory vectors.
28. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " left limit " order, and the left boundary of search volume is set to be in the unit, the leftmost side of described n unit under the described flag state whereby.
29. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " right limit " order, and the right boundary of search volume is set to be in the unit, the leftmost side of described n unit under the described flag state whereby.
30. data handling system according to claim 24, wherein:
Described controller can be in a described n unit limit search space dynamically.
31. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " find " order, identifies in described n the unit that maintains the numerical value that equals the indicated variable of described " find " order each whereby; And
Wherein, described " find " orders each in described n the unit that is arranged in the described n that has identified right side, unit, described marker bit is set to described flag state, and at all in other described n the unit described marker bit be set to described unmarked state.
32. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " match " order, identify each in the described n unit whereby, each in the described n unit has and is in the marker bit under the described flag state and has and described data field that the indicated variable of described " match " order is complementary; And
In wherein said " match " order each in described n the unit that is right after the described n that has identified back, unit, described marker bit is set to described flag state, and at all in other described n the unit described marker bit be set to described unmarked state.
33. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " find and markleft " order, identifies whereby to maintain to equal by in described n the unit of the numerical value of the indicated variable of described " find and mark left " order each; And
Wherein said " find " orders each in described n the unit that is arranged in left side, the described n that has identified unit, described marker bit is set to described flag state, and at all in other described n the unit described marker bit be set to described unmarked state.
34. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " match and markleft " order, identify each in the described n unit whereby, each in the described n unit has and is in the marker bit under the described flag state and has and described data field that the indicated variable of described " match " order is complementary; And
Wherein said " match " orders each in described n the unit that is arranged in left side, the described n that has identified unit, and described marker bit is set to described flag state.
35. data handling system according to claim 28, wherein:
One in described many instructions of being sent by described controller is " markall " order, and the described marker bit of each in described n the unit in the described whereby search volume is set to described flag state.
36. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " addmark " order, comprises each the described marker bit that equals by in described n the unit of the numerical value of the indicated variable of described " addmark " order whereby and is set to described flag state; And
Described " addmark " order does not influence any other described marker bit of described n unit.
37. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " mark " order, comprises each the described marker bit that equals by in described n the unit of the numerical value of the indicated variable of described " mark " order whereby and is set to described flag state; And
Described " mark " order equals by in described n the unit of the numerical value of the indicated variable of described " mark " order each not comprising, and described marker bit is set to described unmarked state.
38. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " clr " order, comprises each the described marker bit that equals by in described n the unit of the numerical value of the indicated variable of described " clr " order whereby and is set to described unmarked state.
39. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " clear first " order, and described n the unit with described marker bit of being arranged to described flag state of the described leftmost side is set to described unmarked state whereby.
40. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " trace " order, duplicates the described marker bit of all described n unit whereby in described content-addressed memory (CAM) to the left.
41. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " keepl " order, whereby, the described marker bit of all the described n unit the rightmost side of described n unit under being in described flag state is set to described unmarked state.
42. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " clrl " order, and the described marker bit that is in the rightmost side of described n unit under the described flag state whereby is set to described unmarked state.
43. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " left " order, whereby with all described marker bits of a described n unit to the unit that moves to left.
44. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " right " order, and a unit whereby moves right all described marker bits of a described n unit.
45. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " cright " order, all described marker bits that will be in described n unit under the described flag state whereby next unit, unit a to right side that moves right is unless next unit, described right side comprises the numerical value that equals the indicated variable of described " cright " order; And
When next unit, described right side comprised the numerical value that equals by the indicated variable of described " cright " order, described " cright " order replaced the described data field of next unit, described right side with predetermined value.
46. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " cleft " order, all described marker bits that will be in described n unit under the described flag state whereby are to next unit, unit to the left side that moves to left, unless next unit, described left side comprises the numerical value that equals by the indicated variable of described " cleft " order; And
When next unit, described left side comprised the numerical value that equals by the indicated variable of described " cleft " order, described " cleft " order replaced the described data field of next unit, described left side with predetermined value.
47. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " nop " order, does not carry out any operation whereby.
48. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " reset " order, and the described data field assignment of giving a described n unit whereby is to order indicated numerical value by described " reset ".
49. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " get " order, and output is stored in numerical value in the unit, the leftmost side that is in described n unit under the described flag state from described content-addressed memory (CAM) device whereby; And
The described marker bit that will be in the unit, the described leftmost side under the described flag state unit that moves right.
50. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " back " order, and output is stored in numerical value in the indexing unit of the leftmost side from described content-addressed memory (CAM) device whereby; And
With the described marker bit of the indexing unit of the described leftmost side to the unit that moves to left.
51. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " set " order, and whereby that described " set " order is indicated value storage is in the leftmost side that is in described n unit under the described flag state.
52. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " setall " order, in whereby that described " setall " order is indicated value storage all described n unit under being in described flag state.
53. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " ins " order, whereby on the insertion point before being positioned at the leftmost side that is in described n unit under the described flag state, the value storage that described " ins " order is indicated is in one of them of a described n unit; And
Each the content that described " ins " order will be arranged in described n the unit on right side, the described insertion point unit that moves right.
54. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " del " order, and deletion is in the data field of the leftmost side of described n unit under the described flag state whereby; And
Described " del " order will be arranged in each the content of described n unit on the right side of indexing unit of the described leftmost side to the unit that moves to left.
55. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " cpr " order, and the content that will be in all the described n unit under the described flag state whereby copies a unit to the right.
56. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " cpl " order, and the content that will be in all the described n unit under the described flag state whereby copies a unit left.
57. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " ccpr " order, and the content that will be in all the described n unit described flag state under whereby copies a unit to the right, comprises copying described flag state; And
Described " ccpr " order does not copy the described flag state of described n such unit: its described content equals by the indicated numerical value of described " ccpr " order.
58. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " ccpl " order, and the content that will be in all the described n unit described flag state under whereby copies a unit left, comprises copying described flag state; And
Described " ccpr " order does not copy the described flag state of described n such unit, and its described content equals the indicated numerical value of described " ccpl " order.
59. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " ld " order, whereby the indicated numerical value of described " ld " order is loaded in the described data field in all described n unit that are under the described flag state.
60. data handling system according to claim 24 further comprises:
The vector memory that comprises p vector; With
One in described many instructions of being sent by described controller is " st " order, and the content that will be in the described data field in all the described n unit described flag state under whereby copies described " st " to and orders on the central correspondence position of one of them vector of described p indicated vector.
61. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " add " order, whereby the indicated numerical value of described " add " order is increased to the central described data field in all described n unit that is in described flag state under.
62. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " fadd " order, whereby the indicated numerical value of described " fadd " order is increased in the central described data field in all described n unit of being in described flag state under; And
Wherein, in described content-addressed memory (CAM) device, be arranged in each the leftmost bit of described data field of unit on right side of described n unit being under the described flag state and serve as carry digit.
63. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " sub " order, deducts described " sub " whereby in the described data field all the described n unit from being in described flag state under and orders indicated numerical value.
64. data handling system according to claim 24, wherein:
One in many instructions of being sent by described controller is " fsub " order, deducts described " fsub " whereby in the described data field all the described n unit from being in described flag state under and orders indicated numerical value; And
Wherein, in described content-addressed memory (CAM) device, be arranged in each the leftmost bit of described data field of unit on right side of described n unit being under the described flag state and serve as carry digit.
65. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " half " order, will be in described data field in all the described n unit under the described flag state whereby divided by two.
66. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " fhalf " order, will be in described data field in all the described n unit under the described flag state whereby divided by two; And
Wherein, if in described content-addressed memory (CAM) device, be arranged in each the least significant data position of unit in left side, a described n unit and be in described flag state, then the position, the leftmost side with described data field adds one.
67. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " lt " order, and whereby that described " lt " order is indicated numerical value compares with described data field in all described n unit that are under the described flag state;
If described " lt " orders indicated described numerical value greater than described data field, the described marker bit that then described " lt " order just is in described n unit under the described flag state is set to described unmarked state; And
If described " lt " orders indicated described numerical value less than described data field, the position, the leftmost side that then described " lt " order just is in the described data field of described n unit under the described flag state is set to 1.
68. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " flt " order, and whereby that described " flt " order is indicated numerical value compares with described data field in all described n unit that are under the described flag state;
If described " flt " orders indicated described numerical value greater than described data field, and in described content-addressed memory (CAM) device, to be arranged in each the position, the leftmost side of described data field of unit in left side, described n unit being under the described flag state be zero, the described marker bit that then described " flt " order is in described n unit under the described flag state is set to described unmarked state;
If described " flt " orders indicated described numerical value less than described data field, the position, the leftmost side that then described " flt " order is in the described data field of described n unit under the described flag state is set to 1;
If in described content-addressed memory (CAM) device, to be arranged in each the position, the described leftmost side of unit in left side, described n unit being under the described flag state be 1, the position, the leftmost side of stating data field that then described " flt " order is in described n unit under the described flag state is set to 1; And
Described " flt " order in described content-addressed memory (CAM) device, be arranged in each the position, the described leftmost side of unit in left side, described n unit being under the described flag state and be set to 0.
69. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " gt " order, and the indicated numerical value of described whereby " gt " order compares with described data field in all described n unit that are under the described flag state;
If described " gt " orders indicated described numerical value less than described data field, the described marker bit that then described " gt " order just is in described n unit under the described flag state is set to described unmarked state; And
If described " gt " orders indicated described numerical value greater than described data field, the position, the leftmost side that then described " gt " order just is in the described data field of described n unit under the described flag state is set to 1.
70. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " fgt " order, and whereby that described " fgt " order is indicated numerical value compares with described data field in all described n unit that are under the described flag state;
If described " fgt " orders indicated described numerical value less than described data field, and in described content-addressed memory (CAM) device, to be arranged in each the position, the leftmost side of described data field of unit in left side, described n unit being under the described flag state be zero, the described marker bit that then described " fgt " order just is in described n unit under the described flag state is set to described unmarked state;
If described " fgt " orders indicated described numerical value greater than described data field, the position, the leftmost side that described " fgt " order just is in the described data field of described n unit under the described flag state is set to 1;
If in described content-addressed memory (CAM) device, to be arranged in each the described leftmost bit of unit in left side of described n unit being under the described flag state be 1, the position, the leftmost side that then described " fgt " order just is in the described data field of described n unit under the described flag state is set to 1; And
Described " fgt " order in described content-addressed memory (CAM) device, be arranged in each the position, the described leftmost side of unit in left side, described n unit being under the described flag state and be set to 0.
71. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " test " order, whereby for be under the described flag state, comprise all described n unit by the indicated numerical value of described " test " order, described " test " orders described marker bit to be set to described unmarked state; And
If all positions, the leftmost side of unit with left side, described n unit of described indicated value are 1, then described " test " order just has the described data field of described n unit of described indicated value with the predetermined value assignment to all; And
If position, the described leftmost side is 1, the position, the described leftmost side of the described unit in all left sides, described n unit with described indicated value is just removed in then described " test " order.
72. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " and " order, whereby for all described n unit that are under the described flag state, described " and " order finish by the indicated numerical value of described " and " order be in together the described data field in all described n unit under the described flag state step-by-step " with ".
73. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " or " order, whereby for all described n unit that are under the described flag state, described " or " order finish by described " or " indicated numerical value of order and be in the described data field in all described n unit under the described flag state step-by-step " or ".
74. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " xor " order, whereby for all described n unit that are under the described flag state, described " xor " order is finished by described " xor " indicated numerical value of order and is in the step-by-step distance of the described data field in all described n unit under the described flag state.
75. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " cond " order, whereby for all described n unit that are under the described flag state, if be 0 by described " cond " indicated numerical value of order and the result that is in the step-by-step AND-operation between the described data field of all the described n unit described flag state under, then described " cond " just orders the flag state with them to be converted to described unmarked state.
76. data handling system according to claim 24, wherein:
One in described many instructions of being sent by described controller is " ncond " order, whereby for all described n unit that are under the described flag state, if be not 0 by described " ncond " indicated numerical value of order and the result that is in the step-by-step AND-operation between the described data field of all the described n unit described flag state under, then described " ncond " just orders the flag state with them to be converted to described unmarked state.
77. according to the described data handling system of claim 71, wherein:
One in described many instructions of being sent by described controller is " index " order, whereby for all described n unit that are under the described flag state, described " index " order will represent in n the unit of described mark that each composes in n the unit of described mark each with respect to a numerical value of the position of the leftmost side of a described n unit.
78. data handling system according to claim 22, wherein:
Described sorter is judged each the global state in the described n unit; And
Described one in wherein said many instructions is by each the selected unit in the described content-addressed memory (CAM) device, carry out according to the described local state of a described n unit and described global state, the described execution of described instruction is simultaneous in each unit in a described clock period, in described selected each unit.
79. data handling system according to claim 22, wherein:
Described content-addressed memory (CAM) device allows to use the key field of variable-length.
80. according to the described data handling system of claim 78, wherein:
The key field of described variable-length comprises data field and key field, and each in the described n unit all has described data field and described key field; And
Wherein during in carrying out described many instructions, different time-interleavedly be stored in the described n unit each in data regard the part of described data field and described key field as.
81. the method for a deal with data said method comprising the steps of:
Form the content-addressed memory (CAM) device to comprise n unit;
Dispose in the described n unit each so that comprise treatment circuit;
Slave controller sends in many instructions one to described content-addressed memory (CAM) device;
Use clock apparatus, be used for the synchronizing clock signals that per second output was made up of the clock period of predetermined number, described clock apparatus is exported described synchronizing clock signals to described content-addressed memory (CAM) device and described controller; And
In a described clock period, transmit described many instructions one from described controller simultaneously to all described n unit globally.
82. a data handling system, described data handling system comprises:
The storage arrangement that comprises n unit, each in the described n unit all comprises treatment circuit;
Controller is used for sending of many instructions to described content-addressed memory (CAM) device;
Clock apparatus is used for the synchronizing clock signals that per second output was made up of the clock period of predetermined number, and described clock apparatus is exported described synchronizing clock signals to described content-addressed memory (CAM) device and described controller; With
Wherein said controller transmits in described many instructions one to all described n unit globally simultaneously in a described clock period.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US43115402P | 2002-12-05 | 2002-12-05 | |
| US60/431,154 | 2002-12-05 | ||
| US10/727,811 | 2003-12-04 |
Publications (2)
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|---|---|
| CN1720516A true CN1720516A (en) | 2006-01-11 |
| CN100440193C CN100440193C (en) | 2008-12-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003801050968A Expired - Fee Related CN100409221C (en) | 2002-12-05 | 2003-12-05 | Data processing system having a Cartesian controller |
| CNB2003801050953A Expired - Fee Related CN100440193C (en) | 2002-12-05 | 2003-12-05 | Cellular engine for a data processing system |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003801050968A Expired - Fee Related CN100409221C (en) | 2002-12-05 | 2003-12-05 | Data processing system having a Cartesian controller |
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| CN (2) | CN100409221C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101119192B (en) * | 2007-09-11 | 2010-09-29 | 杭州华三通信技术有限公司 | Clock synchronization method and system |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4907148A (en) * | 1985-11-13 | 1990-03-06 | Alcatel U.S.A. Corp. | Cellular array processor with individual cell-level data-dependent cell control and multiport input memory |
| US5418970A (en) * | 1986-12-17 | 1995-05-23 | Massachusetts Institute Of Technology | Parallel processing system with processor array with processing elements addressing associated memories using host supplied address value and base register content |
| US5081609A (en) * | 1989-01-10 | 1992-01-14 | Bull Hn Information Systems Inc. | Multiprocessor controller having time shared control store |
| US5867726A (en) * | 1995-05-02 | 1999-02-02 | Hitachi, Ltd. | Microcomputer |
| JP3759645B2 (en) * | 1995-12-25 | 2006-03-29 | 三菱電機株式会社 | Synchronous semiconductor memory device |
| US6317819B1 (en) * | 1996-01-11 | 2001-11-13 | Steven G. Morton | Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction |
| US6226738B1 (en) * | 1997-08-01 | 2001-05-01 | Micron Technology, Inc. | Split embedded DRAM processor |
| JP2000312293A (en) * | 1999-04-26 | 2000-11-07 | Ricoh Co Ltd | Printer |
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2003
- 2003-12-05 CN CNB2003801050968A patent/CN100409221C/en not_active Expired - Fee Related
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101119192B (en) * | 2007-09-11 | 2010-09-29 | 杭州华三通信技术有限公司 | Clock synchronization method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100409221C (en) | 2008-08-06 |
| CN100440193C (en) | 2008-12-03 |
| CN1720514A (en) | 2006-01-11 |
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