CN1584824A - Microprocessor frame based on CISC structure and instruction realizing style - Google Patents
Microprocessor frame based on CISC structure and instruction realizing style Download PDFInfo
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Abstract
A command realizing method of microprocessor based on CISC structure simplifies complicated instruction set of CISC microprocessor to beinstruction set with 151 commands which can support commands of data transmission and interchange, arithmetical logic operation, comparation, multiplication, division, displacement, circulation, nibble operation, position operation, skip, calling return, stack in and out, software interruption and idle operation.
Description
Technical field
The present invention relates to the microcontroller (MCU) of SIC (semiconductor integrated circuit) design field, especially relate to the microcontroller of carrying out sophisticated vocabulary based on the CISC structure.
Background technology
Microcontroller (MCU) is a core with a certain micro-processor kernel generally at present, the integrated ROM/EPROM/EEPROM/FlashROM of chip internal, RAM, bus, bus logic, Timer, WatchDog, I/O, serial port, width modulation output, A/D, D/A, LCD driving, UART, I
2Various necessary functions such as C and peripheral hardware.For adapting to different application demands, a Series chip has multiple derived product, and the processor cores of every kind of derived product all is the same, and different is the configuration and the encapsulation of storer and peripheral hardware.Single-chip microcomputer is complementary with application demand to greatest extent.The maximum characteristics of microcontroller are singualtion, and volume is little, thereby the power consumption of making and cost descend, and reliability improves.Microcontroller is the main flow of present embedded system industry.The peripheral hardware resource is generally abundanter on the sheet of microcontroller, is suitable for various application.
Kind and quantity that embedded microcontroller is present are maximum, and more representational universal serial comprises 8051, P51XA, MCS-251, MCS-96/196/296, C166/167, MC68HC05/11/12/16,68300 etc.Also have many half universal serial in addition as MCU 8XC930/931, the C540, the C541 that support USB interface; Support I
2C, CAN-Bus, LCD and numerous special-purpose MCU and compatible family.MCU accounts for the market share of embedded system about 70% at present.
Aspect the MCU exploitation,, can be divided into two big main flow: RISC and CISC with framework.It is fairly simple that risc instruction set is formed, and the relative instruction execution speed is very fast, may need many packings of orders to form but accomplish a task, and just needs to take the more compiler time at the work than complex combination and carry out, and its bus structure are Harvard's type.
The bus structure of CISC are Feng. Nuo Yiman types, and computing machine is in same storage space instruction fetch and data, data line and order line time-sharing multiplex.Aspect pipeline organization, to get finger and carry out employing single instruction stream line structure, its instruction set is abundant, and is powerful.
The CISC system is a kind of for the ease of programming with improve internal storage access efficient and the system that designs.Its principal character is to use the microcode operation and has abundant instruction set, is convenient to design new processor, can effectively shorten the microcode design time of new instruction.Its abundant instruction set is convenient to Application Engineer's programming use.Have dual-operand form, register to register, register to internal memory and internal memory to the instruction of register etc., addressing mode is flexible.
The single-chip microcomputer that belongs to the CISC structure mainly contains AT89 series, Taiwan Winbond (magnificent nation) the W78 series of M68HC series, the Atmel of the MCS-51 series of Intel, Motorola, PCF80C51 series of Dutch Pilips etc.; In general, the better simply small household appliances of control relation can adopt the risc type single-chip microcomputer; The occasion that control relation is complicated should adopt the CISC single-chip microcomputer as big household electrical appliances, communication product, industrial control system
In 8 CISC microcontroller chip fields, the standards system framework all is the execution of continuous type, traditional CISC has occupied the bigger market share, CISC has numerous and diverse instruction set mostly, operational efficiency is lower, the instruction extensibility is relatively poor, uses shortcomings such as complexity, is difficult to satisfy communication requirement more and more fast.
CISC single-chip microcomputer major defect is: 1. instruction set is numerous and jumbled, and the utilization factor of most instructions is not high.2. different instructions needs the different clock period to finish, and every instruction will just can be finished by carrying out one section explanatory microprogram, need take more CPU time, and it is not very high carrying out efficient.3. because instruction is huge, make the scope of program compiler select target instruction very big, compiling is optimized in inconvenience.4. emphasize Data Control, cause design complicated, the lead time is long.
Summary of the invention
The objective of the invention is to propose a kind of novel microprocessor framework and instruction implementation based on CISC, it improves on the basis of traditional C ISC, proposes a kind of efficient system framework, has improved instruction operation efficient.Support 151 elementary instructions, adopt four sections streamlines of single-stage, operational efficiency improves, and the packing of orders is convenient, can satisfy all kinds of Embedded Real-Time controls and the requirement of communicating by letter.
Microcontroller according to a first aspect of the invention based on the CISC structure, this microcontroller nuclear comprises program storage, the data random access memory, the special function register heap, data bus and address bus, the instruction pipeline structure, the data buffer, universal arithmetic logic unit, instruction is read and code translator and system control module, wherein, described data bus be divided into each self-separation 8 internal data buses and 8 program data bus, described system control module is used to produce system clock, system reset and various read-write control circuit, four sections instruction pipeline Processing Structure of described single-stage are divided into 4 parts, at first be that instruction is read and decoding scheme, promptly described instruction is read and code translator reads in instruction by above-mentioned 8 program data bus from program storage, and decomposition is deciphered in instruction; Read the content of register or storer then according to decode results by control circuit; Carry out computing by ALU again; Result to computing deposits register or data memory unit in afterwards; When execution such as calls, returns at instruction, can carry out pop down and go out stack operation program pointer, when carrying out instruction such as redirect, the pointer offset operation is arranged, when whenever reading next byte instruction, can have PC to add 1 operation simultaneously.
Microcontroller according to a second aspect of the invention based on the CISC structure, it is characterized in that described data-carrier store (RAM), program storage (ROM), special function register and data buffer area be the space independently, utilize the map addresses circuit with their map addresses on continuous space, and can expand.
Instruction implementation according to a third aspect of the invention we based on the microcontroller of CISC structure, the instruction set that it is characterized in that this microcontroller has 151 elementary instructions, this microcontroller is supported all kinds of common microprocessor instructions, comprise that data transmit exchange, arithmetic logical operation, comparison, multiplication and division, shift cycle, nibble operation, bit manipulation, redirect, call and return, push on and move back stack, soft interruption and the instruction of blank operation class, 1 work period that instruction execution cycle is the shortest, 10 the longest work periods, instruction can be expanded accordingly.
Instruction implementation according to a forth aspect of the invention based on the microcontroller of CISC structure, it is characterized in that described instruction set comprises 25 data movement instructions, every instruction has its unique operational code identification, instruction realizes the data of source address are sent in the destination address, because source address and destination address can be multiple addressing modes, make every instruction comprise the order number that 1-4 byte do not wait, produce class control signal control and finish: 1) the relevant register of control is sent to calculating (3) control that ALU (2) control ALU finishes the address with data and extracts data (4) control data from source address and write destination address.
Instruction implementation according to a fifth aspect of the invention based on the microcontroller of CISC structure, it is characterized in that described instruction set also comprises 10 comparison orders, every instruction has its unique operational code identification, instruction realizes the data of source address and the data of destination address are compared, every instruction comprises the order number that 1-4 byte do not wait, and produces class control signal control and finishes: the relevant register of (1) control is sent to calculating (3) control that ALU (2) control ALU finishes the address with address date and extracts data from source address and destination address and be sent to ALU (4) control ALU and carry out subtraction (5) control the result of subtraction is provided with flag register.
Instruction implementation according to a sixth aspect of the invention based on the microcontroller of CISC structure, it is characterized in that described instruction set also comprises 50 arithmetic logical operation instructions, every instruction has its unique operational code identification, instruction realizes the data of source address and the data of destination address are carried out arithmetic or logical operation, every instruction comprises the order number that 1-4 byte do not wait, and produces class control signal control and finishes: the relevant register of (1) control is sent to calculating (3) control that ALU (2) control ALU finishes the address with address date and extracts data from source address and destination address and be sent to arithmetical logic operation (5) control that ALU (4) control ALU execution command requires the result of computing is write destination register.
Instruction implementation according to a seventh aspect of the invention based on the microcontroller of CISC structure, it is characterized in that described instruction set also comprises 2 decimal adjust instructions, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, instruction realizes 16 system results in the register are carried out decimal system adjustment, produce binary-coded decimal, adjusted result still is written back to register p.
Instruction implementation according to an eighth aspect of the invention based on the microcontroller of CISC structure, it is characterized in that described instruction set also comprises 2 multiplication and division instructions, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, instruction realizes that the unsigned number among register w and the totalizer a multiplies each other and the write-back result, and the unsigned number among instruction realization register pair wa and the register c is divided by and write-back.
Instruction implementation according to a ninth aspect of the invention based on the microcontroller of CISC structure, it is characterized in that described instruction set also comprises 13 ring shifts and nibble operational order, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, instruction realizes the displacement or the nibble displacement of the data of register or register and internal memory.
Instruction implementation according to the tenth aspect of the invention based on the microcontroller of CISC structure, it is characterized in that described instruction set also comprises 24 bit manipulation instructions, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, instruction realizes the position of register or internal storage location data is provided with and computing.
Instruction implementation according to an eleventh aspect of the invention based on the microcontroller of CISC structure, it is characterized in that described instruction set also comprises 11 jump instructions, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, according to the redirect of side-play amount instruction realization program.
Instruction implementation according to a twelfth aspect of the invention based on the microcontroller of CISC structure, it is characterized in that described instruction set also comprise 8 call, link order, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, according to different addressing modes, instruction realizes calling and returning of subroutine.
Instruction implementation according to a thirteenth aspect of the invention based on the microcontroller of CISC structure, it is characterized in that described instruction set also comprises 4 pop instructions that push on, produce control signal, instruction realizes the pop down of program status word (PSW) and content of registers and pops.
The instruction implementation based on the microcontroller of CISC structure according to a fourteenth aspect of the invention is characterized in that described instruction set also comprises 1 soft interrupt instruction, produces control signal, and instruction realizes software interruption.
The instruction implementation based on the microcontroller of CISC structure according to a fifteenth aspect of the invention is characterized in that described instruction set also comprises 1 non-operation instruction, produces control signal, and instruction realizes blank operation.
Instruction implementation according to a sixteenth aspect of the invention based on the microcontroller of CISC structure, it is characterized in that the instruction of reading in is read by described instruction and code translator decomposes, decipher by the microinstruction code after decomposing, and carry out accordingly and operate, according to the addressing mode difference, after the decoding operand or operational code are stored in different operand registers, microinstruction code register, internal memory respectively.
The instruction implementation based on the microcontroller of CISC structure according to a seventeenth aspect of the invention is characterized in that described different addressing mode is respectively by addressing type to count totally 11 types of addressing, directly address, register addressing, register indirect addressing, implied addressing, relative addressing, indexed addressing, absolute addressing, vectorial addressing, Page addressing and memory bit addressing immediately.
Instruction implementation according to an eighteenth aspect of the invention based on the microcontroller of CISC structure, it is characterized in that instructing the order of carrying out be to read in order code and decoding mutually at first of clock, while handling interrupt etc., the data of the second phase rdma read unit or register and storage, third phase is carried out the ALU operation, finish the various computings of command request or the calculating of side-play amount, the 4th write memory as a result and the related register that ordering calculation is got carries out the setting of correlating markings position and the operation of instruction cycle storage computation mutually at each simultaneously.
Instruction implementation according to a nineteenth aspect of the invention based on the microcontroller of CISC structure, the mode that it is characterized in that Interrupt Process is for when the request of interruption takes place, set interrupt latch device, when first phase clock that instruction is carried out, detect the interrupt latch device, response is interrupted, and interrupting enabler flags and interrupt latch device clearly, PC carries out the automatic pop down in front and back and pops at interrupt routine; The kind of described interruption comprises that software interruption, external interrupt, timer interrupt, WDT interrupts, serial line interface interrupts, and interruption can be nested, except that software interruption and the may command interrupt source shielding of WDT interruption.
Description of drawings
Fig. 1 is the inner structure synoptic diagram of microprocessor core of the present invention.
Fig. 2 carries out the hardware configuration synoptic diagram for instruction.
Fig. 3 carries out the beat schematic flow sheet for instruction.
Fig. 4 is Memory Allocation and map addresses synoptic diagram.
Fig. 5 is the peripheral module resource distribution synoptic diagram of microcontroller nuclear of the present invention.
Fig. 6 is the reset circuit synoptic diagram.
Fig. 7 is an Interrupt Process process synoptic diagram.
Embodiment
Elaborate below in conjunction with the framework and the implementation of accompanying drawing to microprocessor of the present invention.
The structure of microprocessor core of the present invention as shown in Figure 1.Clock generator produces fundamental clock, and frequency division, and innernal CPU nuclear and the needed clock signal of outer peripheral device are provided.Program storage and data-carrier store have data bus separately.During execution, at first reading command sign indicating number, decoding then.Decoding is the definition according to microcode, and the difference of addressing mode, and operand or operational code are stored in operand register, microinstruction code register, internal memory or special function register (not comprising the SR zone) respectively.According to the type of the instruction that obtains after the decoding, ALU is sent in operand or calculative address carry out computing.Then, the result of storage computing writes register or internal storage location.And then read in the instruction of next byte, decipher, ALU computing, write-back storage data, by that analogy, up to order fulfillment.Because the instruction set of this microprocessor is elongated cisc instruction, every instruction length difference, instruction cycle from 1 machine cycle machine cycle to 10 is not waited.In the process that instruction is carried out, to every instruction performed to machine cycle and PC count, with the operation of steering order.
The hardware configuration of instruction process operating part at first finds the entry address of program as shown in Figure 2 according to reseting vector, PC points to the program entry unit of program storage, reads in instruction from program storage, deciphers by command decoder.If operational code deposits operation register in; If operand, still to send into ALU and carry out computing as number immediately according to the judgement of operational code being determined to write entry data memory.Behind the DSR, can carry out the ALU arithmetic operation.The result of computing deposits register or data memory unit in.When execution such as calls, returns at instruction, can carry out pop down and go out stack operation program pointer; During instructions such as execution redirect, the pointer offset operation is arranged; When whenever reading next byte instruction, can have PC to add 1 operation simultaneously.The source that these constitute PC also is one of normal key factor of carrying out of assurance program.
The basic sequential of instruction process as shown in Figure 3.(CLK1, CLK2, CLK3 and CLK4) controls by four phase clocks that obtain behind the major clock frequency division.Each machine cycle is divided into 4 beats according to 4 phase clocks, the corresponding phase clock of each beat.Each microcode of reading in is carried out following operation: CLK1 respectively at 4 phase clocks to be got and refers to that data, CLK3 that decoding (comprise zone bit and Interrupt Process are set), CLK2 read in the needed register carry out ALU computing, CLK4 storage operation result (comprise and adjust the PC pointer).Simultaneously, judge and the total periodicity of record present instruction, and when reading in the next byte of instruction, successively decrease according to microcode, adjust PC,, point to next bar instruction until last cycle of present instruction, the zone bit zero clearing, the open interruption begins to carry out next bar instruction.So cycling is up to EOP (end of program).
This microprocessor comprises basic interruptions commonly used such as software interruption, external interrupt, timer interrupt, WDT interrupts.May command interrupt source shielding, wherein software interruption and WDT interrupt not maskable with nested.When interrupt request, the interrupt request sign is set and is latched in the interrupt latch device simultaneously automatic PC pop down.After executing present instruction, response is interrupted, and is provided with to interrupt enabler flags and make in the current interrupt procedure of response and forbid maskable interrupts.After interruption executes or resets, open latching.The Interrupt Process process is seen shown in Figure 7.
The instruction set of microprocessor of the present invention is a sophisticated vocabulary, and data-bus width is 8, adopts single-stage pipeline processes and execution command, but the address space of addressing continuously 64K byte.This 64K space is divided into 4 address spaces, is respectively program memory ROM, data-carrier store RAM, special function register SR and data buffer register BR.Use the memory-mapped input/output, all I/O registers all are mapped in SR or BR address space.Chip internal has 16 groups of general-purpose registers, and 8 every group, totally 128 general-purpose registers are distributed in preceding 128 bytes in address ram space.Memory Allocation is seen shown in Figure 4.
For the safety and the power managed of system, system reset adopts multi-source to reset, as shown in Figure 6.Comprise that electrification reset, software reset, clock detection reset, address trap resets, WDT resets.Wherein electrification reset resets for the low level greater than 4 clock period; When PC points to RAM or specified register SR zone, produce the address trap reset signal, restarting systems; WDT is allowing under the duty, if CPU does not press the clear WDT of normal operating conditions, the WDT counting can produce reset signal when overflowing.
Processor cores of the present invention can be expanded all kinds of general peripheral hardwares and communication interface easily, comprises synchronous serial interface, high speed serialization output, I
2C bus, lcd driver, A/D converter, timer/counter or the like also can be expanded 151 instructions according to the microcode definition simultaneously.The application synoptic diagram of a microprocessor configuration peripheral hardware resource is seen shown in Figure 5.
A kind of typical implementation of microprocessor of the present invention as shown in Figure 5." 1 " is systematic clock generator, produces fundamental clock.Wherein comprise a timing sequencer, produce main system clock and operation of peripheral devices clock through frequency division.Exportable needed divided pulse and produces basic timing, WDT, serial ports, the release needed various clocks of system such as reset to outside port." 2 " are the CPU nuclear of this microprocessor, are cores of the present invention.With reference to figure 1, comprise command decoder, order register, ALU, internal stack, special register, interruption processing module and read-write control circuit.After the system power-on reset, finding the entry address of program according to reset instruction from program storage, is that unit reads in instruction and the storage that will carry out with the byte.Then instruction is deciphered.According to the definition of microcode, carry out operation accordingly during decoding.The coding of microcode is divided into two big classes, byte coding and double-byte encodings.Table 1 is the explanation to each byte microcode implication in every class coding.
Table 1 instruction microcode definition list
| The byte microcode | Instruction type | Addressing mode | The double byte microcode | Instruction | Addressing mode |
| ?0000 ?0000 | swi | ?0000 ?0001 | ?jmp | ||
| ?0000 ?0001 | jmp | ?0000 ?0011 | ?cal | ||
| ?0000 ?0010 | calp | ?0010 ?1*** | ?xorb | ||
| ?0000 ?0011 | cal | ?0011 ?0*** | ?movb | ||
| ?0010 ?0*** | mov b | ?0011 ?1*** | ?cplb | ||
| ?0010 ?1000 | jf | ?1011 ?0*** | ?clrb | ||
| ?0010 ?1001 | jt | ?1011 ?1*** | ?setb | ||
| ?0010 ?1100 | jnc | ?1110 ?0000 | ?rshrcf | ||
| ?0010 ?1101 | jc | ?1110 ?0001 | ?rshlcf | ||
| ?0010 ?1110 | jnz | ?1110 ?0010 | ?shrcf | ||
| ?0010 ?1111 | jz | ?1110 ?0011 | ?shlcf | ||
| ?0011 ?**** | calv | ?1111 ?0100 | ?dsa | ||
| ?010* ?**** | sjf | ?1111 ?0101 | ?daa |
| ?011* ?**** | ?sjt | ?1111 ?0110 | ?rshrm | ||
| ?1011 ?0*** | ?clrb | ?1111 ?0111 | ?rshlm | ||
| ?1011 ?1*** | ?setb | ?1111 ?1000 | ?push | ||
| ?1111 ?1000 | ?push | ?1111 ?1001 | ?pop | ||
| ?1111 ?1001 | ?pop | ?1111 ?1011 | ?retn | ||
| ?1111 ?1010 | ?ret | ?1111 ?1110 | ?swap | ||
| ?1111 ?1011 | ?reti | ?1010 ?0*** | ?mov | Target is register addressing | |
| ?1111 ?1100 | ?div | ?1110 ?10** | ?mov | Target is a register pair addressing | |
| ?1111 ?1101 | ?mul | ?1010 ?1*** | ?mov | The source is register addressing | |
| ?1111 ?1111 | ?nop | ?1110 ?11** | ?mov | The source is a register pair addressing | |
| ?1100 ?1*** | ?mov | Target for the register addressing source for counting immediately | ?1101 ?1001 | ?mov | Target is directly address |
| ?1111 ?0000 | ?mov | Target for the RBS source for counting immediately | ?1101 ?1000 | ?mov | Target is a register indirect addressing |
| ?1101 ?0011 | ?mov | Target is directly address | ?1101 ?0011 | ?mov | The source is for counting immediately |
| The source is for counting immediately | |||||
| ?1101 ?0010 | ?mov | Target for the register indirect addressing source for counting immediately | ?1000 ?0000 | ?cmp | Target is implied addressing A |
| ?0000 ?0101 | ?mov | Target is that stack pointer SP source is for counting immediately | ?1001 ?1000 | ?cmp | The source is a register indirect addressing |
| ?1000 ?0000 | ?cmp | Target is that implied addressing A source is directly address | ?1000 ?1000 | ?cmp | The source is for counting immediately |
| ?1000 ?0110 | ?add | Target is that implied addressing A source is directly address | ?1000 ?0110 | ?add | Target is implied addressing A |
| ?1000 ?0100 | ?sub | Target is that implied addressing A source is directly address | ?1001 ?1110 | ?add | The source is a register indirect addressing |
| ?1000 ?0011 | ?and | Target is that implied addressing A source is directly address | ?1000 ?1110 | ?add | The source is for counting immediately |
| ?1000 ?0001 | ?or | Target is that implied addressing A source is directly address | ?1000 ?0100 | ?sub | Target is implied addressing A |
| ?1000 ?0010 | ?xor | Target is implied addressing A | ?1001 ?1100 | ?sub | The source is that register is indirect |
| The source is directly address | Addressing | ||||
| ?1000 ?1100 | ?sub | The source is for counting immediately | |||
| ?1000 ?0011 | ?and | Target is implied addressing A | |||
| ?1001 ?1011 | ?and | The source is a register indirect addressing | |||
| ?1000 ?1011 | ?and | The source is for counting immediately | |||
| ?1000 ?0001 | ?or | Target is implied addressing A | |||
| ?1001 ?1001 | ?or | The source is a register indirect addressing | |||
| ?1000 ?1001 | ?or | The source is for counting immediately | |||
| ?1000 ?0010 | ?xor | Target is implied addressing A | |||
| ?1001 ?1010 | ?xor | The source is a register indirect addressing | |||
| ?1000 ?1010 | ?xor | The source is for counting immediately | |||
| ?0001 ?0*** | Register addressing | ||||
| ?0001 ?1000 | Before subtract 1 register |
| Indirect addressing | |||||
| ?0001 ?1001 | After add 1 register indirect addressing | ||||
| ?0001 ?1011 | Indexed addressing | ||||
| ?0001 ?1111 | Directly address |
The instruction length of microprocessor of the present invention is a 1-4 byte, and performance period 1-10 is not waited.According to decode results, be divided into immediately and count totally 11 types of addressing, directly address, register addressing, register indirect addressing, implied addressing, relative addressing, indexed addressing, absolute addressing, vectorial addressing, Page addressing, memory bit addressing.As shown in Figure 2, extract the first level address of several immediately or register information or RAM after the decoding, enter ALU by MUX and carry out computing, the result outputs to RAM or relevant register unit.Except that conventional PC adds 1, according to different instructions the PC pointer is adjusted, comprise the address of side-play amount addressing, internal stack, the address of jump instruction etc.After code translator carries out identification to the microcode that reads in, except to current operational code or immediately the number operate accordingly, also want total execution cycle number of decision instruction and record, whether be finished with this decision instruction as a token of, whether need to remove or be provided with corresponding flag register, carry out the correctness of sequential with the assurance system." 3 " are the reset circuit of system, comprise that clock detection resets, address trap resets, WDT resets, software reset and external reset circuit.Can be with reference to shown in Figure 6.Except that outside electrification reset, when system clock quits work, the perhaps non-ROM of PC pointed zone, perhaps CPU work is undesired and when not having clear WDT counter, can produce systematic reset signal and make system reset." 4 " are timer/counters, and native system comprises two 16 and two 8 multi-functional timer/counters." 5 " are input/output end ports.Be bidirectional port, and the port reusable." 6 " are the interface circuits of ADC and Digital Logic part." 7 " are the ADC modules, and native system is the successive approximation analog to digital C of 88 passages." 8 " are interruptable controllers.During when interruption request generation and to CPU application interrupt response, set interrupt latch device, when first phase clock that instruction is carried out, detect the interrupt latch device, discovery has interruption, response is interrupted, and interrupts enabler flags and interrupt latch device clearly, the automatic pop down of PC, entry address according to vector table address is read interrupt service routine writes PC.Carry out interrupt service routine then.After returning, PC pointer is originally popped automatically, continues to carry out master routine.Its sequential chart is seen shown in Figure 7." 9 " are program memory ROMs.EPROM and data-carrier store and specified register and the data buffer addressing continuously of the total 16K of this microprocessor are convenient to visit." 10 " are watchdog timer WDT.Work to produce when undesired at CPU and interrupt or internal reset signal, restart system and make it operate as normal, improved system reliability." 11 " are basic timers, provide regularly, can produce basic timer and interrupt." 12 " are the clock synchronization serial line interfaces, are used for the communication between the device, can transmit the data of 8 bytes continuously." 13 " are the static data memory RAM.With reference to figure 4, this microprocessor has the RAM of 8 of 512 bytes, and wherein preceding 128 bytes are the general-purpose register zone, comprises 16 groups of 8 general-purpose registers.Back 384 bytes are the metadata cache zone.Storehouse can be located at the arbitrary region beyond the general-purpose register among the RAM.When PC points to ram region, can produce address trap and reset.The general-purpose register here is what to separate with specified register SR, also has data buffer register BR and program memory ROM in addition.By the map addresses circuit can be continuous addressing 64K address space.
This microprocessor is the CISC structure, supports all kinds of common microprocessor instructions.Comprise 151 elementary instructions altogether, comprise that data transmit exchange, arithmetic logical operation, comparison, multiplication and division, displacement, circulation, nibble operation, bit manipulation, redirect, call and return, push on and move back stack, soft interruption and the instruction of blank operation class.According to the definition of microcode, instruction can be expanded according to microcode, uses flexibly.It below is basic instruction set of the present invention.
1, instruction: mov
(1) memonic symbol: mov p, q
Coding: 0001 0***1110 10**
Operation: p＜-q
Influence zone bit: JF=1, ZF=z
Describe: the value of register q is composed to register p.JF puts 1; ZF put 1 when the value that sends register p to was 0x00H, otherwise zero clearing.
(2) memonic symbol: mov p, (x)
Coding: 0,001 1,111 1010 0***
Operation: p＜-(x)
Influence zone bit: JF=1, ZF=z
Describe: with memory address is that the value at x place is composed to register p.JF puts 1; ZF put 1 when the value that sends register p to was 0x00H, otherwise zero clearing.
(3) memonic symbol: mov p, (HL+)
Coding: 0,001 1,001 1010 0***
Operation: p＜-(HL), HL＜-HL+ 1
Influence zone bit: JF=1, ZF=z
Describe: with memory address is that the value at registers group HL content place is composed to register p, and the content of HL adds 1 then.JF puts 1; ZF put 1 when the value that sends register p to was 0x00H, otherwise zero clearing.
(4) memonic symbol: mov p, (HL)
Coding: 0,001 1,000 1010 0***
Operation: HL＜-HL-1, p＜-(HL)
Influence zone bit: JF=1, ZF=z
Describe: the content with HL subtracts 1 earlier, is that the value at registers group HL content place is composed to register and put 1 again with memory address; ZF put 1 when the value that sends register p to was 0x00H, otherwise zero clearing.
(5) memonic symbol: mov p, (HL+d)
Coding: 0,001 1,011 1010 0***
Operation: p＜-(HL+d)
Influence zone bit: JF=1, ZF=z
Describe: with memory address is that the value that registers group HL content adds the d place is composed to register p.JF puts 1; ZF put 1 when the value that sends register p to was 0x00H, otherwise zero clearing.
(6) memonic symbol: mov pp, (x)
Coding: 0,001 1,111 0001 10**
Operation: pp＜-(x+1, x)
Influence zone bit: JF=1
Describe: with memory address is that the value at x and x+1 place is composed to registers group pp.JF puts 1.
(7) memonic symbol: mov pp, (HL+d)
Coding: 0,001 1,011 1110 10**
Operation: pp＜-(HL+d+1, HL+d)
Influence zone bit: JF=1
Describe: memory address is composed to registers group pp for the HL content adds the value that d+1 and HL content add the d place.JF puts 1.
(8) memonic symbol: mov (x), p
Coding: 0,000 1,111 1010 1***
Operation: (x)＜-p
Influence zone bit: JF=1
Describe: it is the internal storage location of x that the value of register p is composed to memory address.JF puts 1.
(9) memonic symbol: mov (HL+), p
Coding: 0,000 1,001 1010 1***
Operation: (HL)＜-p, HL＜-HL+ 1
Influence zone bit: JF=1
Describe: it is the internal storage location of HL value that the value of register p is composed to memory address, and the content of HL adds 1 then.JF puts 1.
(10) memonic symbol: mov (HL), p
Coding: 0,000 1,000 1010 1***
Operation: HL＜-HL-1, (HL)＜-p
Influence zone bit: JF=1
Describe: the content with HL subtracts 1 earlier, and then the value of register p being composed to memory address is the internal storage location of HL value.JF puts 1.
(11) memonic symbol: mov (HL+d), p
Coding: 0,000 1,011 1010 1***
Operation: (HL+d)＜-p
Influence zone bit: JF=1
Describe: it is the internal storage location of HL+d value that the value of register p is composed to memory address.JF puts 1.
(12) memonic symbol: mov (x), pp
Coding: 0,000 1,111 1110 11**
Operation: (x+1, x)＜-pp
Influence zone bit: JF=1
Describe: it is the internal storage location of x+1 and x that the value of register pp is composed to memory address.JF puts 1.
(13) memonic symbol: mov (HL+d), pp
Coding: 0,000 1,011 1110 11**
Operation: (HL+d+1, HL+d)＜-pp
Influence zone bit: JF=1
Describe: the value of register pp is composed to memory address added the internal storage location that d+1 and HL content add d for the HL content.JF puts 1.
(14) memonic symbol: mov (x), (y)
Coding: 1,101 1001
Operation: (x)＜-(y)
Influence zone bit: JF=1, ZF=z
Describe: be that the internal storage location value of y composes to memory address with memory address be the internal storage location of x.JF puts 1; If the data that transmit are 0x00H, then ZF puts 1, otherwise zero clearing.
(15) memonic symbol: mov (x), (HL+d)
Coding: 0,001 1,011 1,101 1001
Operation: (x)＜-(HL+d)
Influence zone bit: JF=1
Describe: it is the internal storage location of x that the internal storage location value that memory address is added d for the HL content is composed to memory address.JF puts 1.
(16) memonic symbol: mov (HL), (x)
Coding: 0,001 1,111 1,101 1000
Operation: (HL)＜-(x)
Influence zone bit: JF=1; ZF=z
Describe: with memory address be the internal storage location value of x compose to memory address add the internal storage location of d for the HL content.JF puts 1; If the data that transmit are 0x00H, then ZF puts 1, otherwise zero clearing.
(17) memonic symbol: mov (HL), (HL+d)
Coding: 0,001 1,011 1,101 1000
Operation: (HL)＜-(HL+d)
Influence zone bit: JF=1; ZF=z
Describe: with memory address be the internal storage location value of x compose to memory address add the internal storage location of d for the HL content.JF puts 1; If the data that transmit are 0x00H, then ZF puts 1, otherwise zero clearing.
(18) memonic symbol: mov p, n
Coding: 1100 1***
Operation: p＜-n
Influence zone bit: JF=1
Describe: will count n immediately and compose to register p.JF puts 1.
(19) memonic symbol: mov SP, mn
Coding: 0,000 0101
Operation: SP＜-mn
Influence zone bit: JF=1
Describe: will count mn immediately and compose to SP SP.JF puts 1.
(20) memonic symbol: mov RBS, n
Coding: 1,111 0,000 1111
Operation: RBS＜-n
Influence zone bit: JF=1
Describe: will count n immediately and compose to register RBS.JF puts 1.
(21) memonic symbol: mov (x), n
Coding: 1,101 0011
Operation: (x)＜-n
Influence zone bit: JF=1
Describe: will count immediately that n composes to memory address is the internal storage location of x.JF puts 1.
(22) memonic symbol: mov (HL), n
Coding: 1,101 0010
Operation: (HL)＜-n
Influence zone bit: JF=1
Describe: will count immediately that n composes to memory address is the internal storage location of HL value.JF puts 1.
(23) memonic symbol: mov (HL+), n
Coding: 0,000 1,001 1,101 0011
Operation: (HL)＜-n; HL＜-HL+ 1
Influence zone bit: JF=1
Describe: will count immediately that n composes to memory address is the internal storage location of HL value, and the content of HL adds 1 then.JF puts 1.
(24) memonic symbol: mov (HL), n
Coding: 0,000 1,001 1,101 0011
Operation: HL＜-HL-1; (HL)＜-n
Influence zone bit: JF=1
Describe: the content with HL subtracts 1 earlier, and will count immediately then that n composes to memory address is the internal storage location of HL value.JF puts 1.
(25) memonic symbol: mov (HL+d), n
Coding: 0,000 1,011 1,101 0011
Operation: (HL+d)＜-n
Influence zone bit: JF=1
Describe: will counting n immediately, to compose to memory address be the internal storage location that the HL value adds d.JF puts 1.
2, instruction: cmp
(1) memonic symbol: cmp A, (x)
Coding: 1,000 0000
Operation: A-(x)
Influence zone bit: JF=z; ZF=z; CF=c; HF=h
Describe: comparand register A and memory address are the value in the internal storage location of x.The same ZF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(2) memonic symbol: cmp A, (HL+)
Coding: 0,001 1,001 1,000 0000
Operation: A-(HL); HL＜-HL+ 1
Influence zone bit: JF=z; ZF=z; CF=c; HF=h
Describe: comparand register A and memory address are the value in the internal storage location of HL, and the HL content adds 1 then.The same ZF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(3) memonic symbol: cmp A, (HL)
Coding: 0,001 1,000 1,000 0000
Operation: HL＜-HL-1; A-(HL)
Influence zone bit: JF=z; ZF=z; CF=c; HF=h
Describe: earlier the HL content is subtracted 1, comparand register A and memory address are the value in the internal storage location of HL again.The same ZF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(4) memonic symbol: cmp A, (HL+d)
Coding: 0,001 1,011 1,000 0000
Operation: A-(HL+d)
Influence zone bit: JF=z; ZF=z; CF=c; HF=h
Describe: comparand register A and memory address are that HL adds the value in the internal storage location of d.The same ZF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(5) memonic symbol: cmp (x), (HL)
Coding: 0,001 1,111 1,001 1000
Operation: (x)-(HL)
Influence zone bit: JF=z; ZF=z; CF=c; HF=h
Describe: relatively memory address is that x and memory address are the value in the internal storage location of HL value.The same ZF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(6) memonic symbol: cmp (HL+d), (HL)
Coding: 00] 01 1,011 1,001 1000
Operation: (HL+d)-(HL)
Influence zone bit: JF=z; ZF=z; CF=c; HF=h
Describe: relatively memory address is that the HL value adds the value in the internal storage location that d and memory address are the HL value.The same ZF of JF result; As ZF puts 1 when doing subtraction result and being 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(7) memonic symbol: cmp (x), n
Coding: 0,001 1,111 1,000 1000
Operation: (x)-n
Influence zone bit: JF=z; ZF=z; CF=c; HF=h
Describe: relatively memory address is the value in the x internal storage location and counts n immediately.The same ZF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(8) memonic symbol: cmp (HL+), n
Coding: 0,001 1,001 1,000 1000
Operation: (HL+)-n; HL＜-HL+ 1
Influence zone bit: JF=z; ZF=z; CF=c; HF=h
Describe: relatively memory address is value and the several immediately n in the internal storage location of HL value, and the content of HL adds 1 then.The same ZF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(9) memonic symbol: cmp (HL), n
Coding: 0,001 1,000 1,000 1000
Operation: HL＜-HL-1; (HL)-n
Influence zone bit: JF=z; ZF=z; CF=c; HF=h
Describe: earlier the HL content is subtracted 1, compare the value in the internal storage location that memory address is the HL value again and count n immediately.The same ZF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 3rd borrow HF put 1.
(10) memonic symbol: cmp (HL+d), n
Coding: 0,001 1,011 1,000 1000
Operation: (HL+d)-n
Influence zone bit: JF=z; ZF=z; CF=c; HF=h
Describe: relatively memory address is that HL adds value and the several immediately n in the internal storage location of d value.The same ZF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
3, instruction: add
(1) memonic symbol: add A, (x)
Coding: 1,000 0110
Operation: A＜-A+ (x)
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: memory address is that the value in the internal storage location of x adds the value among the register A, and the result leaves among the register A.The same ZF of JF result; As addition, ZF put 1 when the result was 0x00H; Most significant digit exists carry CF to put 1; Existence HF when the 4th carry puts 1.
(2) memonic symbol: add A, (HL+)
Coding: 0,001 1,001 1,000 0000
Operation: A＜-A+ (HL); HL＜-HL+ 1
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: memory address is that the value in the HL internal storage location adds the value among the register A, and the result leaves among the register A, and the HL content adds 1 then.The same CF of JF result; As addition, ZF put 1 when the result was 0x00H; Most significant digit exists carry CF to put 1; Existence during from the 3rd carry HF put 1.
(3) memonic symbol: add A, (HL)
Coding: 0,001 1,000 1,000 0110
Operation: HL＜-HL-1; A＜-A+ (HL)
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: earlier the HL content being subtracted 1, is that value in the HL internal storage location adds the value among the register A again with memory address, and the result leaves among the register A.The same CF of JF result; As addition, ZF put 1 when the result was 0x00H; Most significant digit exists carry CF to put 1; Existence during from the 3rd carry HF put 1.
(4) memonic symbol: add A, (HL+d)
Coding: 0,001 1,011 1,000 0110
Operation: A＜-A+ (HL+d)
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: with memory address is that HL adds the value that value in the internal storage location of d adds register A, and the result leaves among the register A.The same CF of JF result; As addition, ZF put 1 when the result was 0x00H; Most significant digit exists carry CF to put 1; Existence during from the 3rd carry HF put 1.
(5) memonic symbol: add (x), (HL)
Coding: 0,001 1,111 1,001 1110
Operation: (x)＜-(x)+(HL)
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: with memory address is that x and memory address are the value addition in the HL internal storage location, and the result leaves in the internal storage location that memory address is x.The same CF of JF result; As addition, ZF put 1 when the result was 0x00H; Most significant digit exists carry CF to put 1; Existence during from the 3rd carry HF put 1.
(6) memonic symbol: add (HL+d), (HL)
Coding: 0,001 1,011 1,001 1110
Operation: (HL+d)＜-(HL+d)+(HL)
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: with memory address is that x and memory address are that HL adds the value addition in the internal storage location of d, and it is that HL adds in the internal storage location of d that the result leaves memory address in.The same CF of JF result; As ZF puts 1 when doing addition results and being 0x00H; Most significant digit exists carry CF to put 1; Existence during from the 3rd carry HF put 1.
(7) memonic symbol: add (x), n
Coding: 0,001 1,111 1,000 1110
Operation: (x)-n
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: with memory address is value and several immediately n addition in the x internal storage location, and it is in the x internal storage location that the result leaves memory address in.The same CF of JF result; As addition, ZF put 1 when the result was 0x00H; Most significant digit exists carry CF to put 1; Existence during from the 3rd carry HF put 1.
(8) memonic symbol: add (HL+), n
Coding: 0,001 1,001 1,000 1110
Operation: (HL)＜-(HL)+n; HL＜-HL+ 1
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: be value and the several immediately n addition in the internal storage location of HL value with memory address, the result leaves in the internal storage location that memory address is the HL value, and the content of HL adds 1 then.The same CF of JF result; As addition, ZF put 1 when the result was 0x00H; Most significant digit exists carry CF to put 1; Existence during from the 3rd carry HF put 1.
(9) memonic symbol: add (HL), n
Coding: 0,001 1,000 1,000 1000
Operation: HL＜-HL-1; (HL)＜-(HL)+n
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: earlier the HL content being subtracted 1, is value and several immediately n addition in the internal storage location of HL value then with memory address, and the result leaves in the internal storage location that memory address is the HL value.The same CF of JF result; As addition, ZF put 1 when the result was 0x00H; Most significant digit exists carry CF to put 1; Existence during from the 3rd carry HF put 1.
(10) memonic symbol: add (HL+d), n
Coding: 0,001 1,011 1,000 1000
Operation: (HL+d)＜-(HL)+n
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: with memory address is that HL adds value and the several immediately n addition in the internal storage location of d, and its result leaves in the internal storage location that memory address is the HL value.The same CF of JF result; As addition, ZF put 1 when the result was 0x00H; Most significant digit exists carry CF to put 1; Existence during from the 3rd carry HF put 1.
4, instruction: sub
(1) memonic symbol: sub A, (x)
Coding: 1,000 0100
Operation: A＜-A-(x)
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: the value among the register A deducts the value in the internal storage location that memory address is x, and the result leaves among the register A.The same ZF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence HF when the 4th borrow puts 1.
(2) memonic symbol: sub A, (HL+)
Coding: 0,001 1,001 1,000 0100
Operation: A＜-A-(HL); HL＜-HL+ 1
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: the value among the register A deducts the value in the internal storage location that memory address is HL, and the result leaves among the register A, and the HL content adds 1 then.The same CF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(3) memonic symbol: sub A, (HL)
Coding: 0,001 1,000 1,000 0100
Operation: HL＜-HL-1; A＜-A-(HL)
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: earlier the HL content is subtracted 1, then the value among the register A is deducted the value in the internal storage location that memory address is HL, the result leaves among the register A.The same CF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(4) memonic symbol: sub A, (HL+d)
Coding: 0,001 1,011 1,000 0100
Operation: A＜-A-(HL+d)
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: it is that HL adds the value in the internal storage location of d that the value of register A deducts memory address, and the result leaves among the register A.The same CF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(5) memonic symbol: sub (x), (HL)
Coding: 0,001 1,111 1,001 1100
Operation: (x)＜-(x)-(HL)
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: with memory address be the internal storage location value of x to deduct memory address be HL internal storage location intermediate value, the result leaves in the internal storage location that memory address is x.The same CF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(6) memonic symbol: sub (HL+d), (HL)
Coding: 0,001 1,011 1,001 1100
Operation: (HL+d)＜-(HL+d)-(HL)
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: with memory address be the internal storage location value of x to deduct memory address be that HL adds the value in the internal storage location of d, it is that HL adds in the internal storage location of d that the result leaves memory address in.The same CF of JF result; As ZF puts 1 when doing subtraction result and being 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(7) memonic symbol: sub (x), n
Coding: 0,001 1,111 1,000 1100
Operation: (x)＜-(x)-n
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: with memory address is that value in the x internal storage location deducts and counts n immediately, and it is in the x internal storage location that the result leaves memory address in.The same CF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(8) memonic symbol: sub (HL+), n
Coding: 0,001 1,001 1,000 1100
Operation: (HL)＜-(HL)-n; HL＜-HL+ 1
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: with memory address is that the internal storage location value of HL value deducts several immediately n, and the result leaves in the internal storage location that memory address is the HL value, and the content of HL adds 1 then.The same CF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(9) memonic symbol: sub (HL), n
Coding: 0,001 1,000 1,000 1100
Operation: HL＜-HL-1; (HL)＜-(HL)-n
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: earlier the HL content being subtracted 1, is that the internal storage location value of HL value deducts several immediately n then with memory address, and the result leaves in the internal storage location that memory address is the HL value.The same CF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
(10) memonic symbol: sub (HL+d), n
Coding: 0,001 1,011 1,000 1100
Operation: (HL+d)＜-(HL)-n
Influence zone bit: JF=c; ZF=z; CF=c; HF=h
Describe: memory address is that internal storage location value that HL adds d deducts and counts n immediately, and its result leaves in the internal storage location that memory address is the HL value.The same CF of JF result; As subtraction, ZF put 1 when the result was 0x00H; Most significant digit exists borrow CF to put 1; Existence during from the 4th borrow HF put 1.
5, instruction: and
(1) memonic symbol: and A, (x)
Coding: 1,000 0011
Operation: A＜-A﹠amp; (x)
Influence zone bit: JF=z; ZF=z;
Describe: the value among the register A and memory address be in the internal storage location of x value with, the result leaves among the register A.The same ZF of JF result; With result ZF when the 0x00H put 1, otherwise zero clearing.
(2) memonic symbol: and A, (HL+)
Coding: 0,001 1,001 1,000 0011
Operation: A＜-A﹠amp; (HL); HL＜-HL+ 1
Influence zone bit: JF=z; ZF=z;
Describe: the value among the register A and memory address be in the internal storage location of HL value with, the result leaves among the register A, the HL content adds 1 then.The same ZF of JF result; With result ZF when the 0x00H put 1, otherwise zero clearing.
(3) memonic symbol: and A, (HL)
Coding: 0,001 1,000 1,000 0011
Operation: HL＜-HL-1; A＜-A﹠amp; (HL)
Influence zone bit: JF=z; ZF=z;
Describe: earlier the HL content is subtracted 1, with value among the register A and memory address be then in the internal storage location of HL value with, the result leaves among the register A.The same ZF of JF result; With result ZF when the 0x00H put 1, otherwise zero clearing.
(4) memonic symbol: and A, (HL+d)
Coding: 0,001 1,011 1,000 0011
Operation: A＜-A﹠amp; (HL+d)
Influence zone bit: JF=z; ZF=z;
Describe: the value of register A and memory address be HL add in the d internal storage location value with, the result leaves among the register A.The same ZF of JF result; With result ZF when the 0x00H put 1, otherwise zero clearing.
(5) memonic symbol: and (x), (HL)
Coding: 0,001 1,111 1,001 1011
Operation: (x)＜-(x) ﹠amp; (HL)
Influence zone bit: JF=z; ZF=z;
Describe: internal storage location value and the memory address that with memory address is x be HL internal storage location intermediate value with, the result leaves in the internal storage location that memory address is x.The same ZF of JF result; With result ZF when the 0x00H put 1, otherwise zero clearing.
(6) memonic symbol: and (HL+d), (HL)
Coding: 0,001 1,011 1,001 1011
Operation: (HL+d)＜-(HL+d) ﹠amp; (HL)
Influence zone bit: JF=z; ZF=z;
Describe: internal storage location value and the memory address that with memory address is x be HL add in the internal storage location of d value with, it is that HL adds in the internal storage location of d that the result leaves memory address in.The same ZF of JF result; With result ZF when the 0x00H put 1, otherwise zero clearing.
(7) memonic symbol: and (x), n
Coding: 0,001 1,111 1,000 1011
Operation: (x)＜-(x) ﹠amp; n
Influence zone bit: JF=z; ZF=z;
Describe: with memory address be value in the x internal storage location and several immediately n with, it is in the x internal storage location that the result leaves memory address in.The same ZF of JF result; With result ZF when the 0x00H put 1, otherwise zero clearing.
(8) memonic symbol: and (HL+), n
Coding: 0,001 1,001 1,000 1011
Operation: (HL)＜-(HL) ﹠amp; N; HL＜-HL+ 1
Influence zone bit: JF=z; ZF=z;
Describe: with memory address be the internal storage location value of HL value with several n immediately with, the result leaves in the internal storage location that memory address is the HL value, the content of HL adds 1 then.The same ZF of JF result; With result ZF when the 0x00H put 1, otherwise zero clearing.
(9) memonic symbol: and (HL), n
Coding: 0,001 1,000 1,000 1011
Operation: HL＜-HL-1; (HL)＜-(HL) ﹠amp; n
Influence zone bit: JF=z; ZF=z;
Describe: earlier the HL content is subtracted 1, be the internal storage location value of HL value then with memory address with several n immediately with, its result leaves in the internal storage location that memory address is the HL value.The same ZF of JF result; With result ZF when the 0x00H put 1, otherwise zero clearing.
(10) memonic symbol: and (HL+d), n
Coding: 0,001 1,011 1,000 1011
Operation: (HL+d)＜-(HL) ﹠amp; n
Influence zone bit: JF=z; ZF=z;
Describe: with memory address be HL add the internal storage location value of d and several immediately n with, its result leaves in the internal storage location that memory address is the HL value.The same ZF of JF result; With result ZF when the 0x00H put 1, otherwise zero clearing.
6, instruction: or
(1) memonic symbol: or A, (x)
Coding: 1,000 0001
Operation: A＜-A| (x)
Influence zone bit: JF=z; ZF=z;
Describe: the value among the register A and memory address be in the internal storage location of x value mutually or, the result leaves among the register A.The same ZF of JF result; ZF put 1 when or result was for 0x00H mutually, otherwise zero clearing.
(2) memonic symbol: or A, (HL+)
Coding: 0,001 1,001 1,000 0001
Operation: A＜-A| (HL); HL＜-HL+ 1
Influence zone bit: JF=z; ZF=z;
Describe: the value among the register A and memory address be in the internal storage location of HL value mutually or, the result leaves among the register A, the HL content adds 1 then.The same ZF of JF result; ZF put 1 when or result was for 0x00H mutually, otherwise zero clearing.
(3) memonic symbol: or A, (HL)
Coding: 0,001 1,000 1,000 0001
Operation: HL＜-HL-1; A＜-A| (HL)
Influence zone bit: JF=z; ZF=z;
Describe: earlier the HL content is subtracted 1, with value among the register A and memory address be then in the internal storage location of HL value mutually or, the result leaves among the register A.The same ZF of JF result; ZF put 1 when or result was for 0x00H mutually, otherwise zero clearing.
(4) memonic symbol: or A, (HL+d)
Coding: 0,001 1,011 1,000 0001
Operation: A＜-A| (HL+d)
Influence zone bit: JF=z; ZF=z;
Describe: the value of register A and memory address be HL add in the d internal storage location value mutually or, the result leaves among the register A.The same ZF of JF result; ZF put 1 when or result was for 0x00H mutually, otherwise zero clearing.
(5) memonic symbol: or (x), (HL)
Coding: 0,001 1,111 1,001 1001
Operation: (x)＜-(x) | (HL)
Influence zone bit: JF=z; ZF=z;
Describe: internal storage location value and the memory address that with memory address is x be HL internal storage location intermediate value mutually or, the result leaves in the internal storage location that memory address is x.The same ZF of JF result; ZF put 1 when or result was for 0x00H mutually, otherwise zero clearing.
(6) memonic symbol: or (HL+d), (HL)
Coding: 0,001 1,011 1,001 1001
Operation: (HL+d)＜-(HL+d) | (HL)
Influence zone bit: JF=z; ZF=z;
Describe: internal storage location value and the memory address that with memory address is x be HL add in the internal storage location of d value mutually or, it is that HL adds in the internal storage location of d that the result leaves memory address in.The same ZF of JF result; ZF put 1 when or result was for 0x00H mutually, otherwise zero clearing.
(7) memonic symbol: or (x), n
Coding: 0,001 1,111 1,000 1001
Operation: (x)＜-(x) | n
Influence zone bit: JF=z; ZF=z;
Describe: with memory address be value in the x internal storage location and several immediately n mutually or, it is in the x internal storage location that the result leaves memory address in.The same ZF of JF result; ZF put 1 when or result was for 0x00H mutually, otherwise zero clearing.
(8) memonic symbol: or (HL+), n
Coding: 0,001 1,001 1,000 1001
Operation: (HL)＜-(HL) | n; HL＜-HL+ 1
Influence zone bit: JF=z; ZF=z;
Describe: with memory address be the internal storage location value of HL value with several n immediately mutually or, the result leaves in the internal storage location that memory address is the HL value, the content of HL adds 1 then.The same ZF of JF result; ZF put 1 when or result was for 0x00H mutually, otherwise zero clearing.
(9) memonic symbol: or (HL), n
Coding: 0,001 1,000 1,000 1001
Operation: HL＜-HL-1; (HL)＜-(HL) | n
Influence zone bit: JF=z; ZF=z;
Describe: earlier the HL content is subtracted 1, be the internal storage location value of HL value then with memory address with several n immediately mutually or, its result leaves in the internal storage location that memory address is the HL value.The same ZF of JF result; ZF put 1 when or result was for 0x00H mutually, otherwise zero clearing.
(10) memonic symbol: or (HL+d), n
Coding: 0,001 1,011 1,000 1001
Operation: (HL+d)＜-(HL) | n
Influence zone bit: JF=z; ZF=z;
Describe: with memory address be HL add the internal storage location value of d and several immediately n mutually or, its result leaves in the internal storage location that memory address is the HL value.The same ZF of JF result; ZF put 1 when or result was for 0x00H mutually, otherwise zero clearing.
7, instruction: xor
(1) memonic symbol: xor A, (x)
Coding: 1,000 0010
Operation: A＜-A xor (x)
Influence zone bit: JF=z; ZF=z;
Describe: the value among the register A and memory address are the value XOR mutually in the x internal storage location, and the result leaves among the register A.The same ZF of JF result; ZF put 1 when the result of phase XOR was 0x00H, otherwise zero clearing.
(2) memonic symbol: xor A, (HL+)
Coding: 0,001 1,001 1,000 0010
Operation: A＜-A xor (HL); HL＜-HL+ 1
Influence zone bit: JF=z; ZF=z;
Describe: the value among the register A and memory address are the value XOR mutually in the HL internal storage location, and the result leaves among the register A, and the HL content adds 1 then.The same ZF of JF result; ZF put 1 when the result of phase XOR was 0x00H, otherwise zero clearing.
(3) memonic symbol: xor A, (HL)
Coding: 0,001 1,000 1,000 0010
Operation: HL＜-HL-1; A＜-A xor (HL)
Influence zone bit: JF=z; ZF=z;
Describe: earlier the HL content being subtracted 1, is the value XOR mutually in the internal storage location of HL then with value among the register A and memory address, and the result leaves among the register A.The same ZF of JF result; ZF put 1 when the result of phase XOR was 0x00H, otherwise zero clearing.
(4) memonic symbol: xor A, (HL+d)
Coding: 0,001 1,011 1,000 0010
Operation: A＜-A xor (HL+d)
Influence zone bit: JF=z; ZF=z;
Describe: the value of register A and memory address are the value XOR mutually that HL adds the d internal storage location, and the result leaves among the register A.The same ZF of JF result; ZF put 1 when the result of phase XOR was 0x00H, otherwise zero clearing.
(5) memonic symbol: xor (x), (HL)
Coding: 0,001 1,111 1,001 1010
Operation: (x)＜-(x) xor (HL)
Influence zone bit: JF=z; ZF=z;
Describe: the internal storage location value that with memory address is x is a HL internal storage location intermediate value XOR mutually with memory address, and the result leaves in the internal storage location that memory address is x.The same ZF of JF result; ZF put 1 when the result of phase XOR was 0x00H, otherwise zero clearing.
(6) memonic symbol: xor (HL+d), (HL)
Coding: 0,001 1,011 1,001 1010
Operation: (HL+d)＜-(HL+d) xor (HL)
Influence zone bit: JF=z; ZF=z;
Describe: internal storage location value and the memory address that with memory address is x is that HL adds the value XOR mutually in the internal storage location of d, and it is that HL adds in the internal storage location of d that the result leaves memory address in.The same ZF of JF result; ZF put 1 when the result of phase XOR was 0x00H, otherwise zero clearing.
(7) memonic symbol: xor (x), n
Coding: 0,001 1,111 1,000 1010
Operation: (x)＜-(x) xor n
Influence zone bit: JF=z; ZF=z;
Describe: with memory address is value in the x internal storage location and several immediately n XOR mutually, and it is in the x internal storage location that the result leaves memory address in.The same ZF of JF result; ZF put 1 when the result of phase XOR was 0x00H, otherwise zero clearing.
(8) memonic symbol: xor (HL+), n
Coding: 0,001 1,001 1,000 1010
Operation: (HL)＜-(HL) xor n; HL＜-HL+ 1
Influence zone bit: JF=z; ZF=z;
Describe: with memory address is the internal storage location value of HL value and the XOR mutually of several n immediately, and the result leaves in the internal storage location that memory address is HL, and the HL content adds 1 then.The same ZF of JF result; ZF put 1 when the result of phase XOR was 0x00H, otherwise zero clearing.
(9) memonic symbol: xor (HL), n
Coding: 0,001 1,000 1,000 1010
Operation: HL＜-HL-1; (HL)＜-(HL) xor n
Influence zone bit: JF=z; ZF=z;
Describe: earlier the HL content being subtracted 1, is the internal storage location value of HL value with memory address and the XOR mutually of several n immediately then, and its result leaves in the internal storage location that memory address is the HL value.The same ZF of JF result; ZF put 1 when the result of phase XOR was 0x00H, otherwise zero clearing.
(10) memonic symbol: xor (HL+d), n
Coding: 0,001 1,011 1,000 1010
Operation: (HL+d)＜-(HL) xor n
Influence zone bit: JF=z; ZF=z;
Describe: with memory address is that HL adds the internal storage location value of d and counts n XOR mutually immediately, and the result leaves in the internal storage location that memory address is the HL value.The same ZF of JF result; ZF put 1 when the result of phase XOR was 0x00H, otherwise zero clearing.
8, instruction: daa
(1) memonic symbol: daa p
Coding: 0001 0*** 1,111 0101
Operation: add instruction result's 16 systems-binary-coded decimal
Influence zone bit: JF=c, ZF=z, CF=c, HF=h
Describe: after executing add instruction, 16 system results among the register p are carried out decimal system adjustment, produce binary-coded decimal.Adjusted result still is written back to register p.
9, instruction: dsa
(1) memonic symbol: dsa p
Coding: 0001 0*** 1,111 0100
Operation: subtraction instruction result's 16 systems-binary-coded decimal
Influence zone bit: JF=c, ZF=z, CF=c, HF=h
Describe: after executing subtraction instruction, 16 system results among the register p are carried out decimal system adjustment, produce binary-coded decimal.Adjusted result still is written back to register p.
10, instruction: mul
(1) memonic symbol: mul w, a
Coding: 1,111 1101
Operation: w*a-〉wa
Influence zone bit: JF=z, ZF=z
Describe: the unsigned number among register w and the totalizer a multiplies each other, and result's high byte is written back to w, and low byte is written back to a.When high byte was 0, sign JF and ZF put 1; Otherwise clear 0.
11, instruction: div
(1) memonic symbol: div wa, c
Coding: 1,111 1100
Operation: wa ÷ c (merchant)-a, remainder-w
Influence zone bit: JF=z, ZF=z, CF=c
Describe: the unsigned number among register pair wa and the register c is divided by, and the merchant writes a, and remainder is write w.Remainder is 0 o'clock, and sign JF and ZF put 1; Otherwise clear 0.If the data of removing among the number register c are 0, the back merchant of perhaps being divided by is greater than 100H, and sign CF puts 1; Otherwise clear 0.
12, instruction: shlcf
(1) memonic symbol: shlcf p
Coding: 0001 0*** 1,110 0011
Operation: referring to following description
Influence zone bit: JF=p[7], ZF=z, CF=p[7]
Describe: the data among the register p move to left one, former most significant digit p[7] to write among the zone bit CF, lowest order mends 0.Concrete operations are referring to accompanying drawing M-1.Sign JF and CF equal the most significant digit of the former data of register.If the data in the displacement late register are 0, indicate that then ZF puts 1, otherwise clear 0.
13, instruction: shrcf
(1) memonic symbol: shrcf p
Coding: 0001 0*** 1,110 0010
Operation: referring to following description
Influence zone bit: JF=p[0], ZF=z, CF=p[0]
Describe: one of the data shift right among the register p, former lowest order p[0] to write among the zone bit CF, most significant digit mends 0.Concrete operations are referring to accompanying drawing M-2.Sign JF and CF equal the lowest order of the former data of register.If the data in the displacement late register are 0, indicate that then ZF puts 1, otherwise clear 0.
14, instruction: rshlcf
(1) memonic symbol: rshlcf p
Coding: 0001 0*** 1,110 0001
Operation: referring to following description
Influence zone bit: JF=p[7], ZF=z, CF=p[7]
Describe: one of data among the register p and zone bit CF ring shift left, the former most significant digit p[7 of register] write among the zone bit CF, former zone bit CF writes register lowest order p[0].Concrete operations are referring to accompanying drawing M-3.Sign JF and CF equal the most significant digit of the former data of register.If the data in the displacement late register are 0, indicate that then ZF puts 1, otherwise clear 0.
15, instruction: rshrcf
(1) memonic symbol: rshrcf p
Coding: 0001 0*** 1,110 0000
Operation: referring to following description
Influence zone bit: JF=p[0], ZF=z, CF=p[0]
Describe: one of data among the register p and zone bit CF ring shift right, the former lowest order p[0 of register] write among the zone bit CF, former zone bit CF writes register most significant digit p[7].Concrete operations are referring to accompanying drawing M-4.Sign JF and CF equal the lowest order of the former data of register.If the data in the displacement late register are 0, indicate that then ZF puts 1, otherwise clear 0.
16, instruction: swap
(1) memonic symbol: swap p
Coding: 0001 0*** 1,111 1110
Operation:
Influence zone bit: JF=1
Describe: the high and low nibble switch among the register p.Sign JF puts 1.
17, instruction: rshlm
(1) memonic symbol: rshlm a, (x)
Coding: 0,001 1,111 1,111 0111
Operation: referring to following description
Influence zone bit: JF=1
Describe: the high and low nibble ring shift left of the low nibble of totalizer a and directly address cell data, concrete operations are referring to accompanying drawing M-5.Sign JF puts 1.
(2) memonic symbol: rshlm a, (HL+)
Coding: 0,001 1,001 1,111 0111
Operation: referring to following description
Influence zone bit: JF=1
Describe: the low nibble of totalizer a and by the high and low nibble ring shift left of HL indirect addressing cell data, concrete operations are referring to accompanying drawing M-6.After shifting function was finished, the content of HL added up 1.Sign JF puts 1.
(3) memonic symbol: rshlm a, (HL)
Coding: 0,001 1,000 1,111 0111
Operation: referring to following description
Influence zone bit: JF=1
Describe: the content of HL successively decreases 1.The low nibble of totalizer a and by the successively decrease high and low nibble ring shift left of back indirect addressing cell data of HL, concrete operations are referring to accompanying drawing M-7.Sign JF puts 1.
(4) memonic symbol: rshlm a, (HL+d)
Coding: 0,001 1,011 1,111 0111
Operation: referring to following description
Influence zone bit: JF=1
Describe: the low nibble of totalizer a and by the high and low nibble ring shift left of HL band side-play amount indirect addressing cell data, concrete operations are referring to accompanying drawing M-8.Sign JF puts 1.
18, instruction: rshrm
(1) memonic symbol: rshrm a, (x)
Coding: 0,001 1,111 1,111 0110
Operation: referring to following description
Influence zone bit: JF=1
Describe: the high and low nibble ring shift right of the low nibble of totalizer a and directly address cell data, concrete operations are referring to accompanying drawing M-9.Sign JF puts 1.
(2) memonic symbol: rshrm a, (HL+)
Coding: 0,001 1,001 1,111 0110
Operation: referring to following description
Influence zone bit: JF=1
Describe: the low nibble of totalizer a and by the high and low nibble ring shift right of HL indirect addressing cell data, concrete operations are referring to accompanying drawing M-10.After shifting function was finished, the content of HL added up 1.Sign JF puts 1.
(3) memonic symbol: rshrm a, (HL)
Coding: 0,001 1,000 1,111 0110
Operation: referring to following description
Influence zone bit: JF=1
Describe: the content of HL successively decreases 1.The low nibble of totalizer a and by the successively decrease high and low nibble ring shift right of back indirect addressing cell data of HL, concrete operations are referring to accompanying drawing M-11.Sign JF puts 1.
(4) memonic symbol: rshrm a, (HL+d)
Coding: 0,001 1,011 1,111 0110
Operation: referring to following description
Influence zone bit: JF=1
Describe: the low nibble of totalizer a and by the high and low nibble ring shift right of HL band side-play amount indirect addressing cell data, concrete operations are referring to accompanying drawing M-12.Sign JF puts 1.
19, instruction clrb
(1) memonic symbol: clrb (x) .b
Coding: 1011 0***
Operation: (x) .b-〉ZF, 0-〉(x) .b
Influence zone bit: JF=z, ZF=(x) .b
Describe: write sign ZF after the b position negate with the directly address unit, afterwards should position clear 0.The same ZF of sign JF.
(2) memonic symbol: clrb (HL+) .b
Coding: 0,001 1,001 1011 0***
Operation: (HL) .b-〉ZF, 0-〉(HL) .b, HL+1-〉HL
Influence zone bit: JF=z, ZF=(HL) .b
Describe: write sign ZF after the b position negate with register pair HL indirect addressing unit, afterwards should be clear 0, at last the data accumulation among the register pair HL 1.The same ZF of sign JF.
(3) memonic symbol: clrb (HL) .b
Coding: 0,001 1,000 1011 0***
Operation: HL-1-〉HL, (HL) .b-〉ZF, 0-〉(HL) .b
Influence zone bit: JF=z, ZF=(HL-1) .b
Describe: earlier the data among the register pair HL are successively decreased 1, write sign ZF again after the b position negate with register pair HL indirect addressing unit, afterwards should position clear 0.The same ZF of sign JF.
(4) memonic symbol: clrb (HL+d) .b
Coding: 0,001 1,011 1011 0***
Operation: (HL+d) .b-〉ZF, 0-〉(HL+d) .b
Influence zone bit: JF=z, ZF=(HL+d) .b
Describe: write sign ZF after the b position negate with register pair HL band side-play amount indirect addressing unit, afterwards should position clear 0.The same ZF of sign JF.
20, instruction setb
(1) memonic symbol: setb (x) .b
Coding: 1011 1***
Operation: (x) .b-〉ZF, 1-〉(x) .b
Influence zone bit: JF=z, ZF=(x) .b
Describe: write sign ZF after the b position negate with the directly address unit, afterwards with this position 1.The same ZF of sign JF.
(2) memonic symbol: setb (HL+) .b
Coding: 0,001 1,001 1011 1***
Operation: (HL) .b-〉ZF, 1-〉(HL) .b, HL+1-〉HL
Influence zone bit: JF=z, ZF=(HL) .b
Describe: write sign ZF after the b position negate with register pair HL indirect addressing unit, afterwards with this position 1, at last the data accumulation among the register pair HL 1.The same ZF of sign JF.
(3) memonic symbol: setb (HL) .b
Coding: 0,001 1,000 1011 1***
Operation: HL-1-〉HL, (HL) .b-〉ZF, 1-〉(HL) .b
Influence zone bit: JF=z, ZF=(HL-1) .b
Describe: earlier the data among the register pair HL are successively decreased 1, write sign ZF again after the b position negate with register pair HL indirect addressing unit, afterwards with this position 1.The same ZF of sign JF.
(4) memonic symbol: setb (HL+d) .b
Coding: 0,001 1,011 1011 1***
Operation: (HL+d) .b-〉ZF, 1-〉(HL+d) .b
Influence zone bit: JF=z, ZF=(HL+d) .b
Describe: write sign ZF after the b position negate with register pair HL band side-play amount indirect addressing unit, afterwards with this position 1.The same ZF of sign JF.
21, instruction cplb
(1) memonic symbol: cplb (x) .b
Coding: 0,001 1,111 0011 1***
Operation: (x) .b-〉ZF, (x) .b-〉(x) .b
Influence zone bit: JF=z, ZF=(x) .b
Describe: write sign ZF after the b position negate with the directly address unit, and with write-back after this negate.The same ZF of sign JF.
(2) memonic symbol: cplb (HL+) .b
Coding: 0,001 1,001 0011 1***
Operation: (HL) .b-〉ZF, (HL) .b-〉(HL) .b, HL+1-〉HL
Influence zone bit: JF=z, ZF=(HL) .b
Describe: write sign ZF after the b position negate with register pair HL indirect addressing unit, and with write-back after this negate, at last the data accumulation among the register pair HL 1.The same ZF of sign JF.
(3) memonic symbol: cplb (HL) .b
Coding: 0,001 1,000 0011 1***
Operation: HL-1-〉HL, (HL) .b-〉ZF, (HL) .b-〉(HL) .b
Influence zone bit: JF=z, ZF=(HL-1) .b
Describe: earlier the data among the register pair HL are successively decreased 1, write sign ZF again after the b position negate with register pair HL indirect addressing unit, and with write-back after this negate.The same ZF of sign JF.
(4) memonic symbol: cplb (HL+d) .b
Coding: 0,001 1,011 0011 1***
Operation: (HL+d) .b-〉ZF, (HL+d) .b-〉(HL+d) .b
Influence zone bit: JF=z, ZF=(HL+d) .b
Describe: write sign ZF after the b position negate with register pair HL band side-play amount indirect addressing unit, and with write-back after this negate.The same ZF of sign JF.
22, instruction movb
(1) memonic symbol: movb cf, (x) .b
Coding: 0010 0***
Operation: (x) .b-〉CF
Influence zone bit: JF=c, CF=(x) .b
Describe: sign CF is write in the b position of directly address unit.JF is opposite with CF for sign.
(2) memonic symbol: movb cf, (HL+) .b
Coding: 0,001 1,001 0010 0***
Operation: (HL) .b-〉CF, HL+1-〉HL
Influence zone bit: JF=c, CF=(HL) .b
Describe: sign CF is write in the b position of register pair HL indirect addressing unit, and the data accumulation among the register pair HL 1.JF is opposite with CF for sign.
(3) memonic symbol: movb cf, (HL) .b
Coding: 0,001 1,000 0010 0***
Operation: HL-1-〉HL, (HL) .b-〉CF
Influence zone bit: JF=c, CF=(HL-1) .b
Describe: earlier the data among the register pair HL are successively decreased 1, the b position of register pair HL indirect addressing unit is write sign CF again, JF is opposite with CF for sign.
(4) memonic symbol: movb cf, (HL+d) .b
Coding: 0,001 1,011 0010 0***
Operation: (HL+d) .b-〉CF
Influence zone bit: JF=c, CF=(HL+d) .b
Describe: sign CF is write in the b position of register pair HL band side-play amount indirect addressing unit.JF is opposite with CF for sign.
(5) memonic symbol: movb (x) .b, cf
Coding: 0,001 1,111 0011 0***
Operation: CF-〉(x) .b
Influence zone bit: JF=1
Describe: will indicate that CF writes the b position of directly address unit.Sign JF puts 1.
(6) memonic symbol: movb (HL+) .b, cf
Coding: 0,001 1,001 0011 0***
Operation: CF-〉(HL) .b, HL+1-〉HL
Influence zone bit: JF=1
Describe: will indicate that CF writes the b position of register pair HL indirect addressing unit, and the data accumulation among the register pair HL 1.Sign JF puts 1.
(7) memonic symbol: movb (HL) .b, cf
Coding: 0,001 1,000 0011 0***
Operation: HL-1-〉HL, CF-〉(HL) .b
Influence zone bit: JF=1
Describe: earlier the data among the register pair HL are successively decreased 1, will indicate that again CF writes the b position of register pair HL indirect addressing unit, sign JF puts 1.
(8) memonic symbol: movb (HL+d) .b, cf
Coding: 0,001 1,011 0011 0***
Operation: CF-〉(HL+d) .b
Influence zone bit: JF=1
Describe: will indicate that CF writes the b position of register HL band side-play amount indirect addressing unit, sign JF puts 1.
23, instruction xorb
(1) memonic symbol: xorb cf, (x) .b
Coding: 0,001 1,111 0010 1***
Operation: CF XOR (x) .b-〉CF
Influence zone bit: JF=c, CF=CF XOR (x) .b
Describe: the b position that will indicate CF and directly address unit is XOR mutually, and the result is written back to and indicates CF.JF is opposite with CF for sign.
(2) memonic symbol: xorb cf, (HL+) .b
Coding: 0,001 1,001 0010 1***
Operation: CF XOR (HL) .b-〉CF, HL+1-〉HL
Influence zone bit: JF=c, CF=CF XOR (HL) .b
Describe: the b position that will indicate CF and register pair HL indirect addressing unit is XOR mutually, and the result is written back to and indicates CF, and the data accumulation among the register pair HL 1.JF is opposite with CF for sign.
(3) memonic symbol: xorb cf, (HL) .b
Coding: 0,001 1,000 0010 1***
Operation: HL-1-〉HL, CF XOR (HL) .b-〉CF
Influence zone bit: JF=c, CF=CF XOR (HL-1) .b
Describe: earlier the data among the register pair HL are successively decreased 1, the b position that will indicate CF and register pair HL indirect addressing unit again is XOR mutually, and the result is written back to and indicates CF, indicates that JF is opposite with CF.
(4) memonic symbol: xorb cf, (HL+d) .b
Coding: 0,001 1,011 0010 1***
Operation: CF XOR (HL+d) .b-〉CF
Influence zone bit: JF=c, CF=CF XOR (HL+d) .b
Describe: will indicate b position that CF and register pair HL be with side-play amount indirect addressing unit XOR mutually, the result is written back to and indicates CF.JF is opposite with CF for sign.
24, instruction sjt
(1) memonic symbol: sjt d
Coding: 011* * * * *
Operation: referring to following description
Influence zone bit: JF=1
Describe: this instruction jump range is 15 bytes or return 16 bytes forward.If sign JF is 1, then program jumps to the d+2 side-play amount place of present instruction first address, and promptly programmable counter PC increases d; Otherwise program does not have redirect.Sign JF puts 1.
25, instruction sjf
(1) memonic symbol: sjf d
Coding: 010* * * * *
Operation: referring to following description
Influence zone bit: JF=1
Describe: this instruction jump range is 15 bytes or return 16 bytes forward.If sign JF is 0, then program jumps to the d+2 side-play amount place of present instruction first address, and promptly programmable counter PC increases d; Otherwise program does not have redirect.Sign JF puts 1.
26, instruction jt
(1) memonic symbol: jt d
Coding: 0,010 1001
Operation: referring to following description
Influence zone bit: JF=1
Describe: this instruction jump range is 127 bytes or return 128 bytes forward.As indicate that JF is 1, and then program jumps to the d+2 side-play amount place of present instruction first address, and promptly programmable counter PC increases d; Otherwise program does not have redirect.Sign JF puts 1.
27, instruction jf
(1) memonic symbol: jf d
Coding: 0,010 1000
Operation: referring to following description
Influence zone bit: JF=1
Describe: this instruction jump range is 127 bytes or return 128 bytes forward.As indicate that JF is 0, and then program jumps to the d+2 side-play amount place of present instruction first address, and promptly programmable counter PC increases d; Otherwise program does not have redirect.Sign JF puts 1.
28, instruction jz
(1) memonic symbol: jz d
Coding: 0,010 1111
Operation: referring to following description
Influence zone bit: JF=1
Describe: this instruction jump range is 127 bytes or return 128 bytes forward.As indicate that ZF is 1, and then program jumps to the d+2 side-play amount place of present instruction first address, and promptly programmable counter PC increases d; Otherwise program does not have redirect.Sign JF puts 1.
29, instruction jnz
(1) memonic symbol: jnz d
Coding: 0,010 1110
Operation: referring to following description
Influence zone bit: JF=1
Describe: this instruction jump range is 127 bytes or return 128 bytes forward.As indicate that ZF is 0, and then program jumps to the d+2 side-play amount place of present instruction first address, and promptly programmable counter PC increases d; Otherwise program does not have redirect.Sign JF puts 1.
30, instruction jc
(1) memonic symbol: jc d
Coding: 0,010 1101
Operation: referring to following description
Influence zone bit: JF=1
Describe: this instruction jump range is 127 bytes or return 128 bytes forward.As indicate that CF is 1, and then program jumps to the d+2 side-play amount place of present instruction first address, and promptly programmable counter PC increases d; Otherwise program does not have redirect.Sign JF puts 1.
31, instruction jnc
(1) memonic symbol: jnc d
Coding: 0,010 1100
Operation: referring to following description
Influence zone bit: JF=1
Describe: this instruction jump range is 127 bytes or return 128 bytes forward.As indicate that CF is 0, and then program jumps to the d+2 side-play amount place of present instruction first address, and promptly programmable counter PC increases d; Otherwise program does not have redirect.Sign JF puts 1.
32, instruction jmp
(1) memonic symbol: jmp xy
Coding: 0,000 0001
Operation: xy-〉PC
Influence zone bit: JF=1
Describe: it is 16 instruction memory cells of counting xy immediately that program jumps to the address.Be about to count the xy assignment immediately and give programmable counter PC.Sign JF puts 1.
(2) memonic symbol: jmp (x)
Coding: 0,001 1,111 0,000 0001
Operation: (x+1, x)-PC
Influence zone bit: JF=1
Describe: it is internal storage location (x+1, x) the instruction memory cell of content that program jumps to the address.(x+1, x) the data assignment in is given programmable counter PC to be about to internal storage location.Sign JF puts 1.
(3) memonic symbol: jmp (hl+d)
Coding: 0,001 1,011 0,000 0001
Operation: (hl+d+1, hl+d)-PC
Influence zone bit: JF=1
Describe: it is memory cell (hl+d+1, hl+d) the instruction memory cell of content that program jumps to the address.(hl+d+1, hl+d) the data assignment in is given programmable counter PC to be about to memory cell.Sign JF puts 1.
33, instruction calv
(1) memonic symbol: calv d
Coding: 0011 * * * *
Operation: PC-1-〉(SP, SP-1), SP-2-〉SP,
(FFC1+d*2，FFC0+d*2)->PC
Influence zone bit: do not have and describe: this instruction is vector call instruction, addressable 16 different subroutines.At first the currency with programmable counter PC subtracts 1 back pop down, simultaneously top-of-stack pointer is subtracted 2, then with the vector table unit to (d*2+FFC1, d*2+FFC0) 16 bit data in are composed to PC, program jumps to the address that this moment, PC pointed to, the i.e. first address of institute's call subroutine.
34, instruction calp
(1) memonic symbol: calp d
Coding: 0,000 0010
Operation: PC-〉(SP, SP-1), SP-2-〉SP, FF00+d-〉PC
Influence zone bit: do not have
Describe: this instruction is the page invocation instruction.At first with the currency pop down of programmable counter PC, top-of-stack pointer subtracts 2 simultaneously, then page first address FF00 is added that side-play amount d composes to PC, and program jumps to the address that this moment, PC pointed to, the i.e. first address of institute's call subroutine.
35, instruction cal
(1) memonic symbol: cal xy
Coding: 0,000 0011
Operation: PC+1-〉(SP, SP-1), SP-2-〉SP, xy-〉PC
Influence zone bit: do not have
Describe: at first the currency with programmable counter PC adds 1 back pop down, and top-of-stack pointer subtracts 2 simultaneously, then 16 bit data xy is composed to PC, and program jumps to the address that this moment, PC pointed to, the i.e. first address of institute's call subroutine.
(2) memonic symbol: cal (x)
Coding: 0,001 1,111 0,000 0011
Operation: PC+1-〉(SP, SP-1), SP-2-〉SP, (x+1, x)-PC
Influence zone bit: do not have
Describe: at first the currency with programmable counter PC adds 1 back pop down, and top-of-stack pointer subtracts 2 simultaneously, then with internal storage location (x+1, x) 16 bit data in are composed to PC, program jumps to the address that this moment, PC pointed to, the i.e. first address of institute's call subroutine.
(3) memonic symbol: cal (hl+d)
Coding: 0,001 1,011 0,000 0011
Operation: PC+1-〉(SP, SP-1), SP-2-〉SP, (hl+d+1, hl+d)-PC
Influence zone bit: do not have
Describe: at first the currency with programmable counter PC adds 1 back pop down, and top-of-stack pointer subtracts 2 simultaneously, then with memory cell (hl+d+1, hl+d) 16 bit data in are composed to PC, program jumps to the address that this moment, PC pointed to, the i.e. first address of institute's call subroutine.
36, instruction ret
(1) memonic symbol: ret
Coding: 1,111 1010
Operation: SP+2-〉SP, (SP, SP-1)-PC
Influence zone bit: do not have
Describe: this instruction is the subroutine call link order.At first top-of-stack pointer is added 2, then with stack cell (SP, SP-1) data in are composed to PC, program jumps to the address that this moment, PC pointed to, and promptly carries out next bar instruction of call subroutine instruction.
37, instruction reti
(1) memonic symbol: reti
Coding: 1,111 1011
Operation: SP+3-〉SP, (SP-1, SP-2)-PC, (SP)-PSW
Influence zone bit: referring to following description
Describe: this instruction is maskable interrupts service routine link order.At first top-of-stack pointer is added 3, then with stack cell (SP-1, SP-2) data in are composed to PC, simultaneously the data in the stack cell (SP) are composed to program status word (PSW) PSW, program jumps to the address that this moment, PC pointed to, and promptly carries out next the bar instruction that will carry out when interrupting taking place.(CF HF) reverts to interrupt service routine and carries out preceding numerical value each state flag bit for JF, ZF at this moment.
38, instruction retn
(1) memonic symbol: retn
Coding: 0,001 0,111 1,111 1011
Operation: SP+3-〉SP, (SP-1, SP-2)-PC, (SP)-PSW
Influence zone bit: referring to following description
Describe: this instruction is maskable interrupt service routine link order not.At first top-of-stack pointer is added 3, then with stack cell (SP-1, SP-2) data in are composed to PC, simultaneously the data in the stack cell (SP) are composed to program status word (PSW) PSW, program jumps to the address that this moment, PC pointed to, and promptly carries out next the bar instruction that will carry out when interrupting taking place.(CF HF) reverts to interrupt service routine and carries out preceding numerical value each state flag bit for JF, ZF at this moment.
39, instruction push
(1) memonic symbol: push PSW
Coding: 1,111 1000
Operation: (PSW)-(SP), SP-1-〉SP
Influence zone bit: do not have
Describe:, simultaneously top-of-stack pointer is subtracted 1 program status word (PSW) PSW pop down.
(2) memonic symbol: push pp
Coding: 0001 01** 1,111 1000
Operation: pp-〉(SP, SP-1), SP-2-〉SP
Influence zone bit: do not have
Describe: the data pop down with among the register pair pp subtracts 2 with top-of-stack pointer simultaneously.
40, instruction pop
(1) memonic symbol: pop PSW
Coding: 1,111 1001
Operation: SP+1-〉SP, (SP)-PSW
Influence zone bit: referring to following description
Describe: top-of-stack pointer is added 1, then the data in the stack cell (SP) are composed to program status word (PSW) PSW.(CF HF) reverts to nearest pop down instruction and carries out preceding numerical value each state flag bit for JF, ZF at this moment.
(2) memonic symbol: pop pp
Coding: 0001 01** 1,111 1001
Operation: SP+2-〉SP, (SP, SP-1)-pp
Influence zone bit: do not have
Describe: top-of-stack pointer is added 2, and (SP, SP-1) data in are composed to register pair pp with stack cell then.
41, instruction swi
(1) memonic symbol: swi
Coding: 0,000 0000
Operation: PSW-〉(SP), PC-1-〉(SP-1, SP-2), SP-3-〉SP,
0->IEN，(FFFD，FFFC)->PC
Influence zone bit: do not have
Describe: this instruction is software interrupt instruction.To stack cell (SP), (SP-1, SP-2), top-of-stack pointer subtracts 3 to the back pop down that again programmable counter successively decreased simultaneously, and interruption is enabled always to indicate IEN clear 0 to stack cell with program status word (PSW) PSW pop down in elder generation.Forbid response to all maskable interrupts.To interrupt at last the entry address memory cell (FFFD, FFFC) data in are composed to programmable counter PC, thereby the executive software interrupt service routine.
42, instruction nop
(1) memonic symbol: nop
Coding: 1,111 1111
Operation: do not have
Influence zone bit: do not have
Describe: this instruction is non-operation instruction.
Claims (19)
1. micro controller frame based on the CISC structure, this microcontroller nuclear comprises program storage, the data random access memory, the special function register heap, data bus and address bus, the instruction pipeline structure, the data buffer, universal arithmetic logic unit, instruction is read and code translator and system control module, wherein, described data bus is divided into 8 internal data buses and 8 program data bus of each self-separation, described system control module is used to produce system clock, system reset and various read-write control circuit, described instruction pipeline structure is four sections instruction pipeline structures of single-stage, and four sections instruction pipeline Processing Structure of this single-stage are divided into 4 parts, at first is that instruction is read and decoding scheme, this instruction is read and code translator reads in instruction by above-mentioned 8 program data bus from program storage, and decomposition is deciphered in instruction; Read the content of register or storer then according to decode results by control circuit; Carry out computing by ALU again; Result to computing deposits register or data memory unit in afterwards; When execution such as calls, returns at instruction, can carry out pop down and go out stack operation program pointer, when carrying out instruction such as redirect, the pointer offset operation is arranged, when whenever reading next byte instruction, can have PC to add 1 operation simultaneously.
2. the micro controller frame based on the CISC structure according to claim 1, it is characterized in that described data-carrier store (RAM), program storage (ROM), special function register and data buffer area be the space independently, utilize the map addresses circuit with their map addresses on continuous space, and can expand.
3. instruction implementation based on the microcontroller of CISC structure, the instruction set that it is characterized in that this microcontroller has 151 elementary instructions, this microcontroller is supported all kinds of common microprocessor instructions, comprise that data transmit exchange, arithmetic logical operation, comparison, multiplication and division, shift cycle, nibble operation, bit manipulation, redirect, call and return, push on and move back stack, soft interruption and the instruction of blank operation class, 1 work period that instruction execution cycle is the shortest, 10 the longest work periods, instruction can be expanded accordingly.
4. the instruction implementation of microcontroller as claimed in claim 3, it is characterized in that described instruction set comprises 25 data movement instructions, every instruction has its unique operational code identification, instruction realizes the data of source address are sent in the destination address, because source address and destination address can be multiple addressing modes, make every instruction comprise the order number that 1-4 byte do not wait, produce class control signal control and finish: 1) the relevant register of control is sent to universal arithmetic logic unit (2) control universal arithmetic logic unit with data and finishes calculating (3) control of address and extract data (4) control data from source address and write destination address.
5. the instruction implementation of microcontroller as claimed in claim 3, it is characterized in that described instruction set also comprises 10 comparison orders, every instruction has its unique operational code identification, instruction realizes the data of source address and the data of destination address are compared, every instruction comprises the order number that 1-4 byte do not wait, and produces class control signal control and finishes: the relevant register of (1) control is sent to calculating (3) control that universal arithmetic logic unit (2) control universal arithmetic logic unit finishes the address with address date and extracts data from source address and destination address and be sent to universal arithmetic logic unit (4) control universal arithmetic logic unit and carry out subtraction (5) control the result of subtraction is provided with flag register.
6. the instruction implementation of microcontroller as claimed in claim 3, it is characterized in that described instruction set also comprises 50 arithmetic logical operation instructions, every instruction has its unique operational code identification, instruction realizes the data of source address and the data of destination address are carried out arithmetic or logical operation, every instruction comprises the order number that 1-4 byte do not wait, and produces class control signal control and finishes: the relevant register of (1) control is sent to calculating (3) control that universal arithmetic logic unit (2) control universal arithmetic logic unit finishes the address with address date and extracts data from source address and destination address and be sent to arithmetical logic operation (5) control that universal arithmetic logic unit (4) control universal arithmetic logic unit execution command requires the result of computing is write destination register.
7. the instruction implementation of microcontroller as claimed in claim 3, it is characterized in that described instruction set also comprises 2 decimal adjust instructions, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, instruction realizes 16 system results in the register are carried out decimal system adjustment, produces binary-coded decimal, and adjusted result still is written back to register p.
8. the instruction implementation of microcontroller as claimed in claim 3, it is characterized in that described instruction set also comprises 2 multiplication and division instructions, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, instruction realizes that the unsigned number among register w and the totalizer a multiplies each other and the write-back result, and the unsigned number among instruction realization register pair wa and the register c is divided by and write-back.
9. the instruction implementation of microcontroller as claimed in claim 3, it is characterized in that described instruction set also comprises 13 ring shifts and nibble operational order, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, instruction realizes the displacement or the nibble displacement of the data of register or register and internal memory.
10. the instruction implementation of microcontroller as claimed in claim 3, it is characterized in that described instruction set also comprises 24 bit manipulation instructions, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, instruction realizes the position of register or internal storage location data is provided with and computing.
11. the instruction implementation of microcontroller as claimed in claim 3, it is characterized in that described instruction set also comprises 11 jump instructions, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, according to the redirect of side-play amount instruction realization program.
12. the instruction implementation of microcontroller as claimed in claim 3, it is characterized in that described instruction set also comprise 8 call, link order, every instruction has its unique operational code identification, according to different addressing modes, produce control signal, according to different addressing modes, instruction realizes calling and returning of subroutine.
13. the instruction implementation of microcontroller as claimed in claim 3 is characterized in that described instruction set also comprises 4 pop instructions that push on, and produces control signal, instruction realizes the pop down of program status word (PSW) and content of registers and pops.
14. microcontroller as claimed in claim 3 is characterized in that described instruction set also comprises 1 soft interrupt instruction, produces control signal, instruction realizes software interruption.
15. the instruction implementation of microcontroller as claimed in claim 3 is characterized in that described instruction set also comprises 1 non-operation instruction, produces control signal, instruction realizes blank operation.
16. instruction implementation as each described microcontroller of claim 3 to 15, it is characterized in that the instruction of reading in is read by described instruction and code translator decomposes, decipher by the microinstruction code after decomposing, and carry out accordingly and operate, according to the addressing mode difference, after the decoding operand or operational code are stored in different operand registers, microinstruction code register, internal memory or special register respectively.
17. the instruction implementation of microcontroller as claimed in claim 16 is characterized in that described different addressing mode is respectively immediately by addressing type to count totally 11 types of addressing, directly address, register addressing, register indirect addressing, implied addressing, relative addressing, indexed addressing, absolute addressing, vectorial addressing, Page addressing and memory bit addressing.
18. instruction implementation as each described microcontroller of claim 3 to 15, it is characterized in that instructing the order of carrying out be to read in order code and decoding mutually at first of clock, while handling interrupt etc., the data of the second phase rdma read unit or register and storage, third phase is carried out the universal arithmetic logic unit operation, finish the various computings of command request or the calculating of side-play amount, the 4th write memory as a result and the related register that ordering calculation is got carries out the setting of correlating markings position and the operation of instruction cycle storage computation mutually at each simultaneously.
19. the instruction implementation of microcontroller as claimed in claim 3, the mode that it is characterized in that Interrupt Process is for when the request of interruption takes place, set interrupt latch device, when first phase clock that instruction is carried out, detect the interrupt latch device, response is interrupted, and interrupting enabler flags and interrupt latch device clearly, PC carries out the automatic pop down in front and back and pops at interrupt routine; The kind of described interruption comprises that software interruption, external interrupt, timer interrupt, WDT interrupts, serial line interface interrupts, and interruption can be nested, except that software interruption and the may command interrupt source shielding of WDT interruption.
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| CN2007101872125A CN101299185B (en) | 2003-08-18 | 2003-08-18 | Microprocessor structure based on CISC structure |
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| CN100545804C (en) | 2009-09-30 |
| CN101299185B (en) | 2010-10-06 |
| CN101299185A (en) | 2008-11-05 |
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