CN101044450A - Processor - Google Patents
Processor Download PDFInfo
- Publication number
- CN101044450A CN101044450A CNA2005800358326A CN200580035832A CN101044450A CN 101044450 A CN101044450 A CN 101044450A CN A2005800358326 A CNA2005800358326 A CN A2005800358326A CN 200580035832 A CN200580035832 A CN 200580035832A CN 101044450 A CN101044450 A CN 101044450A
- Authority
- CN
- China
- Prior art keywords
- data
- register
- processor
- storer
- mark value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Devices For Executing Special Programs (AREA)
Abstract
There is provided a processor capable of performing operation with a high operation frequency by reducing the delay generated between a memory and a register file. The processor (100) includes a register file (110) having a plurality of registers and a tag value generation circuit (102) for generating a tag value indicating the data attribute. Each of the registers has a data filed (112) for holding data and a tag field (111) for holding a tag value. When executing a load instruction for loading data into the register of the register file (110) from the memory (14), the tag generation circuit (102) generates a tag value according to the load instruction and stores it in the tag field (111).
Description
Technical field
The present invention relates to a kind of processor that can under high operating frequency, move, especially relate to the processor that can improve operating frequency.
Background technology
Has a kind of processor now, when carrying out load instructions, according to attribute by this load instructions established data, after to the data conversion of having carried out configuration change, code expansion, zero expansion etc. from the data of storer output, it is stored in (for example with reference to patent documentation 1) in the register file.
Fig. 1 is the figure that the existing processor of expression constitutes.
As shown in the figure, processor 10 possesses that instruction decoding circuit 11, storer are read control circuit 12, storer writes control circuit 13, storer 14, arithmetical unit 15, data converting circuit 20 and register file 30.And register file 30 possesses a plurality of registers that only are made of data field 31.In addition, use register serial number (the management data field 31 of Reg# 0～Reg#N).
So-called " load instructions " is meant from the instruction of memory load data.
So-called " storage instruction " is to point to the instruction of memory stores data.
So-called " operational order " is meant the instruction of carrying out calculation process.
In the load instructions decoded signal, comprise the required address of reference-to storage 14 and sense data, size of data, and information such as data type.
In the operational order decoded signal, comprise the information of determining the calculation process content.
In the storage instruction decoded signal, comprise reference-to storage 14 and write the required address of data, size of data, and information such as data type.
Storer is read control circuit 12 according to the load instructions decoded signal from instruction decoding circuit 11 outputs, will (read control signal hereinafter referred to as storer by the signal that this load instructions decoded signal has been added feature.) output to storer 14.
Storer writes control circuit 13 according to the storage instruction decoded signal from instruction decoding circuit 11 outputs, will (write control signal hereinafter referred to as storer by the signal that this storage instruction decoded signal has been added feature.) output to storer 14.
In addition, from the data that storer 14 is read, in data converting circuit 20, be performed the data conversion of configuration change, code expansion, zero expansion etc. after, be stored in the register file 30.
Fig. 2 is the figure of the formation of expression data conversion circuit.
As shown in the figure, here, as an example, data conversion circuit 20 possesses ordering portion 21, zero extension 22, code extension 23, selector switch 24 etc.
21 pairs of data from storer 14 outputs of ordering portion are implemented ordering and are handled, and the data after will handling output to zero extension 22 and code extension 23.
So-called " ordering is handled " is meant that (M is a natural number to make M.) position of the part bit string of bit data and lowest order as one man arranges and export.For example, when the part bit string of input the 8th to the 15th of 32 bit data, output is from the bit string of 7 of the 0th arrangements to the.
The 22 pairs of data from 21 outputs of ordering portion in zero extension are implemented zero extension process, and the data after will handling output to selector switch 24.
So-called " zero extension process " be meant, in that (M is a natural number with M.) data of position expand to N (N is the natural number bigger than M.) position data the time, make from the M-1 position to most significant digit the position for " 0 " and output.
The 23 pairs of data from 21 outputs of ordering portion in code extension are implemented the code extension process, and the data after will handling output to selector switch 24.
So-called " code extension process " be meant, in that (M is a natural number with M.) data of position expand to N (N is the natural number bigger than M.) position data the time, make from the M-1 position to most significant digit the position for " value of the code bit of M bit data " and output.
Selector switch 24 bases are selected one of the data from storer 14 outputs, the data of exporting from zero extension 22, data of 23 outputs from the code extension, and are outputed to register file 30 from the load instructions decoded signal of instruction decoding circuit 11 outputs.
Patent documentation 1: the spy opens flat 9-269895 communique
But, in described existing technology, there are the following problems: when when storer 14 outputs to register file 30 with data, because of needs pass through data converting circuit 20, so the delay that produces between storer 14 and register file 30 increases, in the exploitation of the processor that carries out moving with high operating frequency, this delay becomes disadvantage.
Summary of the invention
Therefore, the present invention carries out in view of the above problems, and its purpose is to provide a kind of processor, cuts down the delay that produces between storer and register file, can high operating frequency action.
In order to realize described purpose, processor of the present invention possesses: the register file that (a) has a plurality of registers; (b) generation unit of the mark value of generation expression data attribute, (c) described each register has data field that keeps data and the tag field that keeps described mark value, (d) described generation unit is when the load instructions of carrying out from the memory load to the register, generate described mark value according to described load instructions, and be stored in the described tag field.
Thus, be stored in the data in the data field, carry out the instruction of calculation process in execution, from register file with data storage during to the storage instruction of storer, can carry out data-switching according to the mark value of expression data attribute, needn't between storer and register file, carry out the data-switching of configuration change, code expansion, zero expansion etc.
In addition, the present invention just is not implemented as processor, and the method (hereinafter referred to as control method) that also can be used as processor controls waits and realizes.In addition, also can be used as and assembled the function that provides by processor (hereinafter referred to as functional processor.) LSI, in programmable logic device (PLD) such as FPGA, CPLD, form the IP kernel heart program of functional processor (hereinafter referred to as the processor core program.) and write down the processor core program recording medium and waited and realize.
The invention effect
As mentioned above, the treatment in accordance with the present invention device can provide a kind of processor, when storer outputs to register file with data, because of not needing,, can high operating frequency move so cut down the delay that between storer and register file, produces by data converting circuit.
In addition, also provide a kind of processor, owing to can handle big or small big data easily than the register of distributing to a register serial number, so can improve data-handling capacity.
Description of drawings
Fig. 1 is the figure of the formation of the existing processor of expression.
Fig. 2 is the figure of the formation of expression data converting circuit.
Fig. 3 is the figure of formation of the processor of expression embodiment 1.
Fig. 4 is the figure of expression as the formation of the register file of an example, embodiment 1.
Fig. 5 is the figure of expression as the data structure of the register of an example, embodiment 1.
Fig. 6 A is the 1st figure that is illustrated in the example of data-switching in the data converting circuit of embodiment 1.
Fig. 6 B is the 2nd figure that is illustrated in the example of data-switching in the data converting circuit of embodiment 1.
Fig. 6 C is the 3rd figure that is illustrated in the example of data-switching in the data converting circuit of embodiment 1.
Fig. 7 is the 1st figure of the processor action of expression embodiment 1.
Fig. 8 A is the 2nd figure of the processor action of expression embodiment 1.
Fig. 8 B is the 3rd figure of the processor action of expression embodiment 1.
Fig. 8 C is the 4th figure of the processor action of expression embodiment 1.
Fig. 9 is the figure of formation of the processor of expression embodiment 2.
Figure 10 is the figure of expression as the formation of the register file of an example, embodiment 2.
Figure 11 is the 1st figure of the processor action of expression embodiment 2.
Figure 12 A is the 2nd figure of the processor action of expression embodiment 2.
Figure 12 B is the 3rd figure of the processor action of expression embodiment 2.
Figure 13 is the figure of formation of the processor of expression embodiment 3.
Figure 14 is the figure of expression as the formation of the arithmetical unit of an example, embodiment 3.
Figure 15 A is the figure of action of the processor of expression embodiment 3.
Figure 15 B is the figure of action of the processor of expression embodiment 3.
Figure 16 is the figure of formation of the processor of expression embodiment 4.
Figure 17 is the figure of expression as the formation of the arithmetical unit of an example, embodiment 4.
Figure 18 is the 1st figure of the processor action of expression embodiment 4.
Figure 19 is the 2nd figure of the processor action of expression embodiment 4.
Figure 20 is the figure of formation of the processor of expression embodiment 5.
Figure 21 is the figure of expression as the formation of the arithmetical unit of an example, embodiment 5.
Figure 22 is the figure of expression as the data structure of the register of an example, embodiment 5.
Figure 23 is the 1st figure of the processor action of expression embodiment 5.
Figure 24 is the 2nd figure of the processor action of expression embodiment 5.
Figure 25 is the 3rd figure of the processor action of expression embodiment 5.
Figure 26 is the figure of formation of the processor of expression embodiment 6.
Figure 27 is the figure of expression as the formation of the arithmetical unit of an example, embodiment 6.
Figure 28 is the 1st figure of the processor action of expression embodiment 6.
Figure 29 is the 2nd figure of the processor action of expression embodiment 6.
Symbol description
10 processors
11 instruction decoding circuits
12 storeies are read control circuit
13 storeies write control circuit
14 storeies
15 arithmetical unit
20 data converting circuits
21 ordering portions
22 0 extensions
23 code extensions
24 selector switchs
30 register files
31 data fields
100,200 processors
101 instruction decoding circuits
102 mark value generative circuits
110,210 register files
111,211 tag fields
112,212 data fields
113,213 data attribute decision circuitry
114,214 data converting circuits
121,221 ordering portions
122,222 zero extensions
123,223 code extensions
124,224 selector switchs
300,400 processors
310,410 register files
311,411 tag fields
312,412 data fields
320,420 arithmetical unit
321,421 data attribute decision circuitry
322,422 arithmetic processing circuits
330 storeies write control circuit
331 data attribute decision circuitry
332 data converting circuits
341,441 ordering portions
342,442 zero extensions
343,443 code extensions
344,444 selector switchs
345,445 totalizers
401 instruction decoding circuits
402 mark value generative circuits
500,600 processors
510,610 register files
520,620 arithmetical unit
530 storeies write control circuit
531 data attribute decision circuitry
532 data converting circuits
541,641 selector switchs
542,642 totalizers
543,643 selector switchs
Embodiment
(embodiment 1)
Below, with reference to description of drawings embodiments of the present invention 1.
The processor of embodiment 1 is characterised in that, carries out the data-switching of configuration change, code expansion, zero expansion etc. before from register file data being outputed to arithmetical unit, replaces carrying out between storer and register file.
According to above viewpoint, the processor of embodiment of the present invention 1 is described.
Fig. 3 is the figure of formation of the processor of expression embodiment 1.
As shown in the figure, processor 100 possesses that storer is read control circuit 12, storer writes control circuit 13, storer 14, arithmetical unit 15.And, possess instruction decoding circuit 101, mark value generative circuit 102, register file 110.
So-called " load instructions " is meant from the instruction of memory load data.
So-called " storage instruction " is to point to the instruction of memory stores data.
So-called " operational order " is meant the instruction of carrying out calculation process.
In the load instructions decoded signal, comprise the required address of reference-to storage 14 and sense data, size of data, and the information of data type etc.
The information that in the operational order decoded signal, comprises the content of determining calculation process.
In the storage instruction decoded signal, comprise reference-to storage 14 and write the required address of data, size of data, and the information of data type etc.
Mark value generative circuit 102 is according to the load instructions decoded signal from instruction decoding circuit 101 outputs, generate the mark value of representing to be stored in the attribute of the data in the register file 110, and mark value and this data that generate are stored in the register file 110 accordingly by this load instructions decoded signal.In addition, according to operational order decoded signal from instruction decoding circuit 101 outputs, generate the mark value of representing to be stored in the attribute of the data in the register file 110, and mark value and this data that generate are stored in the register file 110 accordingly by this operational order decoded signal.
In addition, mark value shows the attribute of the data corresponding with this mark value.In addition, the every effective or invalid information that in attribute, comprises size of data, data type, composition data.
Storage mark value in tag field 111, the storage data corresponding in data field 112 with this mark value.
In addition, data field 112 and tag field 111 have 1 pair 1 corresponding relation, and by register serial number (Reg# 0～Reg#N) management.
Data attribute decision circuitry 113 is read the mark value corresponding with these data from tag field 111 from data field 112 sense datas the time, and judges the attribute of these data according to the mark value of reading.Then, judged result is judged that as data attribute signal outputs to data converting circuit 114.
Storer is read control circuit 12 according to the load instructions decoded signal from instruction decoding circuit 101 outputs, will (read control signal hereinafter referred to as storer by the signal that this load instructions decoded signal has been added feature.) output to storer 14.
Storer writes control circuit 13 according to the storage instruction decoded signal from instruction decoding circuit 101 outputs, will (write control signal hereinafter referred to as storer by the signal that this storage instruction decoded signal has been added feature.) output to storer 14.
In addition, from the data that storer 14 is read, do not carry out the expansion of configuration change, code, zero expansion etc. data-switching store register file 110 into.
Below, as an example, the formation of the register file of embodiment 1 is described.
Here, be that example describes with following situation: the data of reading from register (Reg#0) are carried out calculation process, and will carry out data that calculation process obtains, be that operation result stores register (Reg#1) into.
Fig. 4 is the figure of expression as the formation of the register file of an example, embodiment 1.
As shown in the figure, data attribute decision circuitry 113 is from the tag field 111 mark-sense values of register (Reg#0), and according to the mark value of reading, judges the data attribute of reading from the data field 112 of register (Reg# 0).Then, judged result is judged that as data attribute signal outputs to selector switch 124 etc.
Relative therewith, 121 pairs of data from data field 112 outputs of register (Reg#0) of ordering portion are implemented ordering and are handled, and the data after will handling output to zero extension 122 and code extension 123.
So-called " ordering is handled " is meant that (M is a natural number to make M.) the section data bit string of position and a processing of as one man arranging and exporting of lowest order.For example, when the part bit string of input the 8th to the 15th of 32 bit data, output is from the bit string of 7 of the 0th arrangements to the.
The 122 pairs of data from 121 outputs of ordering portion in zero extension are implemented zero extension process, and the data after will handling output to selector switch 124.
So-called " zero extension process " be meant, in that (M is a natural number with M.) data of position expand to N (N is the natural number bigger than M.) position data the time, make from the M-1 position to most significant digit the position for " 0 " and output processing.
The 123 pairs of data from 121 outputs of ordering portion in code extension are implemented the code extension process, and the data after will handling output to selector switch 124.
So-called " code extension process " be meant, in that (M is a natural number with M.) data of position expand to N (N is the natural number bigger than M.) position data the time, make from the M-1 position to most significant digit the position for " value of the code bit of M bit data " and output processing.
Then, 15 pairs of arithmetical unit are carried out calculation process from the data of selector switch 124 outputs, and will carry out data that calculation process obtains, be the data field 112 that operation result stores register (Reg#1) into.
Below, as an example, the data structure of the register of embodiment 1 is described.
Fig. 5 is the figure of expression as the data structure of the register of an example, embodiment 1.
As shown in the figure, register is made of 8 tag field 151 and 32 data field.
The 0th to the 3rd low level 4 bit representation significance bits of tag field 151, promptly where begin to store data from data field 152.For example, (a) when being " 1000 ", expression is stored since the 3rd bit string (the 31st).(b) when being " 0100 ", expression is stored since the 2nd bit string (the 23rd).(c) when being " 0010 ", expression is stored since the 1st bit string (the 15th).(d) when being " 0001 ", expression is stored since the 0th bit string (the 7th).
The 4th to the 5th 2 bit representations of tag field 151 are stored in the size of the data in the data field 152.For example, (a) for " 00 " time, represent 32, (b) for " 01 " time, represent 16, (c) for " 10 " time, represent 8.In addition, " 11 " are empty.
Whether the data that the 6th bit representation of tag field 151 is stored in the data field 152 are data that code is arranged.For example, (a) when being " 0 ", expression is codeless data, and (b) when being " 1 ", expression is the data that code is arranged.
Whether the data that the 7th bit representation of tag field 151 is stored in the data field 152 are data of having carried out the data-switching of configuration change, code expansion, zero expansion etc.For example, (a) when being " 0 ", expression is EOC, promptly is data after the conversion, (b) when be " 1 ", expression be do not change finish, promptly be the preceding data of conversion.
Below, the example of data-switching in the data converting circuit of embodiment 1 is described.
Fig. 6 A～Fig. 6 C is the figure that is illustrated in the example of data-switching in the data converting circuit of embodiment 1.
As shown in the figure, data converting circuit 114 is according to the situation difference of following (1)～(3), the content difference of data-switching.
(1) (mov Reg, Mem) and when storer 162b has read 32 data, data converting circuit 114 is not changed at execution command 161a.That is, among the register 163b with 32 data storage to 32.(with reference to Fig. 6 A.)。
(2) at execution command 161b (movb Reg, Mem) and when having read in 32 since effective 8 bit data of the 1st bit string from storer 162b, data converting circuit 114 is converted into as one man to be arranged with the position of lowest order and has carried out zero expanded data.Then, with the conversion after data storage in 32 register 163b.(with reference to Fig. 6 B.)。
(3) at execution command 161c (movbex Reg, Mem) and when having read in 32 since effective 8 bit data of the 1st bit string from storer 162b, data converting circuit 114 converts thereof into as one man to be arranged with the position of lowest order and has carried out the code expanded data.Then, with the conversion after data storage in 32 register 163c.(with reference to Fig. 6 C.)。
Below, the action of the processor of embodiment 1 is described.
Fig. 7, Fig. 8 A～Fig. 8 C is the figure of action of the processor of expression embodiment 1.
As shown in Figure 7, instruction decoding circuit 101 is carried out one of following (1)～(3) (step S101) according to the instruction of decoding.
(1) instruction decoding circuit 101 outputs to storer with the load instructions decoded signal and reads control circuit 12 and mark value generative circuit 102 (step S111) when the instruction of decoding is load instructions.
Corresponding with it, storer is read control circuit 12 and storer is read control signal is outputed to storer 14 (step S112).Storer 14 will be read the control signal established data by storer and store register file 110 (step S113) into.On the other hand, mark value generative circuit 102 will represent to be stored in by the load instructions decoded signal mark value of the attribute of the data in the register file 110, store register file 110 (step S114) accordingly into these data.
At this moment, as shown in Figure 8, register file 110 will store data field 112 (step S121) into by load instructions decoded signal established data, and store the mark value corresponding with these data into tag field 111 (step S122).
(2) instruction decoding circuit 101 outputs to arithmetical unit 15 and mark value generative circuit 102 (step S131) with the operational order decoded signal when the instruction of decoding is operational order.
Corresponding with it, arithmetical unit 15 is read by operational order decoded signal established data (step S132) from register file 110, and the data of reading are carried out the calculation process of being determined by the operational order decoded signal (step S133).Then, the data storage that the execution calculation process is obtained is to register file 110 (step S134).On the other hand, mark value generative circuit 102 will represent to be stored in by the operational order decoded signal mark value of the attribute of the data in the register file 110, and the data that obtain with the execution calculation process store register file 110 (step S135) accordingly into.
At this moment, shown in Fig. 8 B, register file 110 is in data attribute decision circuitry 113, according to by the corresponding mark value of operational order decoded signal established data, judge the attribute (step S141) of these data, and judged result is judged that as data attribute signal outputs to data converting circuit 114 (step S142).Then, in data converting circuit 114, judge that according to data attribute signal judges whether to change these data (step S143).When the result who judges is conversion (step S143: be), judge these data of conversion of signals (step S144) according to data attribute, and the data after will changing output to arithmetical unit 15 (step S145).
In addition, at (step S143: not), do not change by operational order decoded signal established data ground and directly output to arithmetical unit 15 when not changing.
(3) instruction decoding circuit 101 outputs to storer with the storage instruction decoded signal and writes control circuit 13 (step S151) when the instruction of decoding is storage instruction.
Corresponding with it, storer writes control circuit 13 and storer is write control signal outputs to storer 14 (step S152).Storer 14 is read by storer from register file 110 and is write control signal established data (step S153).
At this moment, shown in Fig. 8 C, register file 110 is in data attribute decision circuitry 113, according to by the corresponding mark value of storage instruction decoded signal established data, judge the attribute (step S161) of these data, and judged result is judged that as data attribute signal outputs to data conversion circuit 114 (step S162).Then, in data converting circuit 114, judge that according to data attribute signal judges whether to change these data (step S163).When the result who judges is conversion (step S163: be), judge these data of conversion of signals (step S164) according to data attribute, and the data after will changing output to storer 14 (step S165).
In addition, at (step S163: not), do not change by storer and output to storer 14 with writing the control signal established data when not changing.
According to the processor 100 of aforesaid embodiment 1, in register file 110, possess tag field 111, data field 112, data attribute decision circuitry 113 and data converting circuit 114.
Thus, can be before data be outputed to arithmetical unit 15 from register file 110, be configured the data conversion of change, code expansion, zero expansion etc., replace between storer 14 and register file 110, carrying out, and can cut down the delay that between storer 14 and register file 110, produces.And, because arithmetical unit 15 can general existing arithmetical unit, so design is also easy.
(embodiment 2)
Below, with reference to description of drawings embodiments of the present invention 2.
The processor of embodiment 2 is characterised in that, before data are outputed to arithmetical unit from register file, be configured the data-switching of change, code expansion, zero expansion etc. in the inside of register file, replace between storer and register file, carrying out.
According to above viewpoint, the processor of embodiment 2 is described.
In addition, to the additional same-sign of the inscape identical, and omit explanation with embodiment 1.
Fig. 9 is the figure of formation of the processor of expression embodiment 2.
As shown in the figure, processor 200 is compared with the processor 100 of embodiment 1, and difference is: possess register file 210 and replace register file 110 (with reference to Fig. 3.)。
Data attribute decision circuitry 213 when again data storage being arrived data field 212, is read from tag field 211 and the corresponding mark value of these data, and is judged the attribute of these data according to the mark value of reading.Then, judged result is judged that as data attribute signal outputs to data converting circuit 214.And, judge whether to change this mark value according to this judged result.During for conversion, change this mark value in the result who judges, and the mark value after will change stores register file 210 into, will change the mark value after preceding mark value is replaced into conversion according to this judged result.
Below, as an example, the formation of the register file of embodiment 2 is described.
Here, so that the data of reading from storer (Reg#0) are carried out data-switching, and the data storage after will changing is that example describes to the situation of register (Reg#0).
Figure 10 is the figure of expression as the formation of the register file of an example, embodiment 2.
As shown in the figure, data attribute decision circuitry 213 is from the tag field 211 mark-sense values of register (Reg#0), and judges the attribute of the data of reading from the data field 212 of register (Reg#0) according to the mark value of reading.Then, judged result is judged that as data attribute signal outputs to selector switch 224.
Relative therewith, 221 pairs of data from data field 212 outputs of register (Reg#0) of ordering portion are implemented ordering and are handled, and the data after will handling output to zero extension 222 and code extension 223.
In addition, because zero extension 222 is identical with code extension 123 formations with the zero extension 122 of embodiment 1 with code extension 223, so omit explanation.
And, the mark value that 213 conversions of data attribute decision circuitry are read, and the mark value after will changing stores the tag field 212 of register (Reg#0) into.
Then, 15 pairs of the arithmetical unit data after the conversion of data field 212 outputs of register (Reg#0) are carried out calculation process, and will carry out data that calculation process obtains, be the data field 212 that operation result stores register (Reg#1) etc. into.
The following describes the action of the processor 200 of embodiment 2.
Figure 11, Figure 12 A, Figure 12 B are the figure of action of the processor of expression embodiment 2.
Shown in Figure 11, Figure 12 A, Figure 12 B, processor 200 is compared with the processor 100 of embodiment 1, has the difference of following (1)～(3).
(1) about the action when load instructions is carried out, (step S111～S114, S121～S122) compare exist following difference (with reference to Fig. 8 A, Figure 11 with the action of embodiment 1.)。
As the action of the register file 110 that replaces embodiment 1 (step S121～S122), register file 210 is carried out load instructions, when storing data into data field 212 again (step S221), in data attribute decision circuitry 213, judge the attribute (step S222) of these data according to the mark value corresponding, and judged result is outputed to data converting circuit 213 (step S223) as the data attribute signal with these data.And, judge whether to change this mark value (step S224) according to this judged result.When the result who judges is conversion (step S224: be), change this mark value (step S225) according to this judged result, and the mark value after will changing stores tag field 211 into, is replaced into mark value (step S226) after the conversion with the mark value before will changing.Then, in data converting circuit 213, judge that according to data attribute signal judges whether to change these data (step S227).During for conversion (step S227: be), judge conversion of signals this data (step S228) according to data attribute in the result who judges, and the data storage after will change being to data field 212, serves as data (step S229) after changing will change preceding data replacement.
Action when (2) carrying out about operational order, (step S131～S135, S141～S144) compare exist following difference (with reference to Fig. 8 B, Figure 12 A with the action of embodiment 1.)。
When the action of the register file 110 of register file 210 alternate embodiments 1 (step S141～when S144) carrying out operational order, sense data from data field 212 (step S241).
Action when (3) carrying out about storage instruction, (step S151～S153, S161～S164) compare exist following difference (with reference to Fig. 8 C, Figure 12 B with the action of embodiment 1.)。
Action (step S161～S164), when register file 210 is carried out storage instructions, the data that are stored in the data field 212 are outputed to storer 14 (step S261) when the register file 110 of alternate embodiments 1.
According to the processor 200 of aforesaid embodiment 2, in register file 210, possess tag field 211, data field 212, data attribute decision circuitry 213 and data converting circuit 214.
Thus, can be before data be outputed to arithmetical unit 15 from register file 210, be configured the data-switching of change, code expansion, zero expansion etc. in the inside of register file 210, replacement is carried out between storer 14 and register file 210, and can cut down the delay that produces between storer 14 and register file 210.In addition because carry out data-switching in the inside of register file 210, so between register file 210 and the arithmetical unit 15, do not produce between register file 210 and the storer 14 and postpone the influence that increases.And, so owing to arithmetical unit 15 can design easily by general existing arithmetical unit.
(embodiment 3)
Below, with reference to description of drawings embodiments of the present invention 3.
The processor of embodiment 3 is characterised in that, is configured the data-switching of change, code expansion, zero expansion etc. in the inside separately that arithmetical unit and storer write control circuit, replaces carrying out between storer and register file.
According to above viewpoint, the processor of embodiment 3 is described.
In addition, to the additional same-sign of the inscape identical, and omit explanation with embodiment 1.
Figure 13 is the figure of formation of the processor of expression embodiment 3.
As shown in the figure, processor 300 is compared with the processor 100 of embodiment 1, and the difference that has following (1)～(3) is (with reference to Fig. 3.)。
(1) possesses register file 310, come alternative registers file 110.
(2) possess arithmetical unit 320 and substitute arithmetical unit 15.
Data attribute decision circuitry 321 from register file 310 read with by the corresponding mark value of operational order decoded signal established data, and judge the attribute of these data according to the mark value of reading.Then, judged result is judged that as data attribute signal outputs to arithmetic processing circuit 322.
In addition, when not changing, do not change the data ground of reading and directly carry out calculation process.
(3) possess storer and write control circuit 330, substitute storer and write control circuit 13.
Storer writes control circuit 330 and writes control circuit 13 with storer and compare, and difference is: newly possess data attribute decision circuitry 331 and data converting circuit 332.
Data attribute decision circuitry 331 from register file 310 read with by the corresponding mark value of storage instruction decoded signal established data, and judge the attribute of these data according to the mark value of reading.Then, judged result is judged that as data attribute signal outputs to data converting circuit 332.And the storer that generates according to storage instruction decoded signal and mark value writes control signal, and outputs to storer 14.
In addition, when not changing, do not change the data ground of reading and directly output to storer 14.
Below, as an example, the formation of the arithmetical unit of embodiment 3 is described.
Here, so that the data of reading from register (Reg#0) are carried out addition process, and will carry out data that addition process obtains, be that the situation that the result of addition stores register (Reg#1) into is that example describes.
Figure 14 is the figure of expression as the formation of the arithmetical unit of an example, embodiment 3.
As shown in the figure, data attribute decision circuitry 321 is from the tag field 311 mark-sense values of register (Reg#0), and judges the attribute of the data of reading from the data field 312 of register (Reg#0) according to the mark value of reading.Then, judged result is judged that as data attribute signal outputs to selector switch 344.
Relative therewith, 341 pairs of data from data field 312 outputs of register (Reg#0) of ordering portion are implemented ordering and are handled, and the data after will handling output to zero extension 342 and code extension 343.
The 342 pairs of data from 341 outputs of ordering portion in zero extension are implemented zero extension process, and the data after will handling output to selector switch 344.
The 343 pairs of data from 341 outputs of ordering portion in code extension are implemented the code extension process, and the data after will handling output to selector switch 344.
345 pairs of totalizers are carried out addition process from the data of selector switch 344 outputs, and will carry out data that addition process obtains, be that operation result is stored in the data field 312 of register (Reg#1).
The action of the processor 300 of embodiment 3 then, is described.
Figure 15 A, Figure 15 B are the figure of action of the processor of expression embodiment 3.
As shown in the figure, processor 300 is compared with the processor 100 of embodiment, has following difference.
Action when (1) carrying out about load instructions is because of (step S111～S114, S121～S122) be identical to omit explanation with the action of embodiment 1.
Action when (2) carrying out about operational order, (there are following difference (with reference to Fig. 8 B, Figure 15 A) in step S131～S135, S141～S145) compare with the action of embodiment 1.
As the action of the register file 110 that replaces embodiment 1 (step S141～S144), when arithmetical unit 320 is carried out operational order, in data attribute decision circuitry 321 according to by the corresponding mark value of operational order decoded signal established data, judge the attribute (step S341) of these data, and judged result is judged that as data attribute signal outputs to arithmetic processing circuit 322 (step S342).And, in arithmetic processing circuit 322, judge signal according to data attribute, judge whether to change these data (step S343).When the result who judges is conversion (step S343: be), judges these data of conversion of signals (step S344) according to data attribute, and the data after the conversion are carried out calculation process (step S345).To carry out data storage that this calculation process obtains in the data field 312 of register file 310 (step S346).
In addition, at (step S343: not), do not change by operational order decoded signal established data ground and directly carry out calculation process when not changing.
Action when (3) carrying out about storage instruction, (there are following difference (with reference to Fig. 8 C, Figure 15 B) in step S151～S153, S161～S165) compare with the action of embodiment 1.
As the action of the register file 110 that replaces embodiment 1 (step S161～S164), when storer writes control circuit 330 execution storage instructions, in data attribute decision circuitry 331 according to write the corresponding mark value of control signal established data by storer, judge the attribute (step S361) of these data, and judged result is judged that as data attribute signal outputs to data converting circuit 332 (step S362).And, in data converting circuit 332, judge that according to data attribute signal judges whether to change these data (step S363).When the result who judges is conversion (step S363: be), judge these data of conversion of signals (step S364) according to data attribute, and the data after will changing output to storer (step S365).
In addition, at (step S363: not), do not change writing control signal established data ground by storer and directly output to storer 14 when not changing.
Processor 300 according to aforesaid embodiment 3, in register file 310, possess tag field 311 and data field 312, in arithmetical unit 320, possess data attribute decision circuitry 321 and arithmetic processing circuit 322, write at storer and possess data attribute decision circuitry 331 and data converting circuit 332 in the control part 330.
Thus, can write control circuit 330 inside separately at arithmetical unit 320 and storer and be configured data-switching such as change, code expansion, zero expansion, replace between storer 14 and register file 310, carrying out, and can cut down the delay that between storer 14 and register file 310, produces.
(embodiment 4)
Below, with reference to description of drawings embodiments of the present invention 4.
The processor of embodiment 4 is characterised in that, writes control circuit inside separately at arithmetical unit and storer and is configured data-switching such as change, code expansion, zero expansion, replaces carrying out between storer and register storage.
According to above-mentioned aspect, the processor of embodiment 4 is described.
In addition, to the inscape additional phase identical with embodiment 3 with symbol, and omit explanation.
Figure 16 is the figure of structure of the processor of expression embodiment 4.
As shown in the figure, processor 400 is compared with the processor 300 of embodiment 3, and the difference that has following (1)～(3) is (with reference to Fig. 5.)。
(1) possesses instruction decoding circuit 401, replace instruction decoding circuit 101.
(2) possess mark value generative circuit 402, replace mark value generative circuit 102.
Mark value generative circuit 402 is compared with mark value generative circuit 102, and difference is: do not generate the mark value that the attribute of the data that obtained by the definite calculation process of operational order decoded signal is carried out in expression.
(3) possess arithmetical unit 420, come substitution operation device 320.
Data attribute decision circuitry 421 from register file 410 read with by the corresponding mark value of operational order decoded signal established data, and judge the attribute of these data according to the mark value of reading.And, judged result is judged that as data attribute signal outputs to arithmetic processing circuit 422.And, generate the mark value that the attribute of the data that the calculation process determined by the operational order decoded signal obtains is carried out in expression, and with the mark value that generates with carry out the data that calculation process obtains and store register file 410 accordingly into.
In addition, when not changing, do not change the data ground of reading and directly carry out calculation process.
Then, as an example, the formation of the arithmetical unit of embodiment 4 is described.
Here, so that the data of reading from register (Reg#0) are carried out calculation process, and will carry out data that calculation process obtains, be that the situation that the result of computing is stored in the register (Reg#1) is that example describes.
Figure 17 is the figure of expression as the formation of the arithmetical unit of an example, embodiment 4.
As shown in the figure, data attribute decision circuitry 421 is from the tag field 411 mark-sense values of register (Reg#0), and judges the attribute of the data of reading from the data field 412 of register (Reg#0) according to the mark value of reading.And, judged result is outputed to selector switch 444 etc. as the determined property signal.
Relative therewith, 441 pairs of data from data field 412 outputs of register (Reg#0) of ordering portion are implemented ordering and are handled, and the data after will handling output to zero extension 442 and code extension 443.
445 pairs of totalizers are carried out addition process from the data of selector switch 444 outputs, and will carry out data that addition process obtains, be that operation result is stored in the data field 412 of register (Reg#1).
And data attribute decision circuitry 421 generates about carrying out data that addition process obtains in totalizer 445, be the mark value of operation result, and the mark value that generates is stored in the tag field 411 of register (Reg#1).
In addition, the formation of zero extension 442 and code extension 443 is identical with code extension 343 with the zero extension 342 of embodiment 3, omits explanation.
The action of embodiment 4 then, is described.
Figure 18, Figure 19 are the figure of action of the processor of expression embodiment 4.
As Figure 18, shown in Figure 19, processor 400 is compared with the processor 300 of embodiment 3, has the difference of following (2).
Action when (1) carrying out about load instructions, (therefore step S111～S114, S121～S122) identical omit explanation with the action of embodiment 3.
Action when (2) carrying out about operational order is compared with the action of embodiment 3, has following difference (with reference to Fig. 7, Figure 15 A, Figure 18, Figure 19).
Replace the action (step S131) of the instruction decoding circuit 101 of embodiment 3, instruction decoding circuit 401 when the instruction of decoding is operational order, outputs to arithmetical unit 420 (step S431) with the operational order decoded signal.
In addition, replace the action (step S135) of the mark value generative circuit 102 of embodiment 3, arithmetical unit 420 is in data attribute decision circuitry 421, expression is stored in the mark value of the attribute of the data in the register file 410 by the operational order decoded signal, is stored in accordingly in the tag field 411 of register file 410 (step S441) with these data.
Action when (3) carrying out about storage instruction, (therefore step S151～S153, S361～S365) identical omit explanation with the action of embodiment 3.
Thus, can write data-switching such as control circuit 330 inside execution configuration change, code separately expanded, zero expansion at arithmetical unit 420 and storer, replace between storer 14 and register file 410, carrying out, can cut down the delay that between storer 14 and register file 410, produces.In addition,, the mark value that will represent the attribute of these data carries out on the data that calculation process obtains, so needn't can realize the reduction of instruction number, the simplification of instruction decoding circuit 401 attribute of the instruction specific data of execution calculation process because being attached to.
(embodiment 5)
Below, with reference to description of drawings embodiments of the present invention 5.
The processor of embodiment 5 is characterised in that, strides a plurality of register-stored sizes data bigger than data field.And, from striding the reduction of data data of a plurality of register-stored, and the data after the reduction are carried out calculation process.
According to above-mentioned aspect, the processor of embodiment 5 is described.
In addition, to the additional same-sign of the inscape identical, and omit explanation with embodiment 3.
Figure 20 is the figure of the formation of the processor in the expression embodiment 5.
As shown in the figure, processor 500 is identical with processor 300 in the embodiment 3, and the difference that has following (1)～(3) is (with reference to Fig. 5.)。
(1) possesses register file 510, replace register file 310.
(2) possess arithmetical unit 520, come substitution operation device 320.
Data attribute decision circuitry 521 from register file 510 read with by the corresponding mark value of operational order decoded signal established data, and judge the attribute of these data according to the mark value of reading.And, judged result is judged that as data attribute signal outputs to arithmetic processing circuit 522.And, generate the mark value that the attribute of the data that the calculation process determined by the operational order decoded signal obtains is carried out in expression, and with the mark value that generates with carry out the data that calculation process obtains and be stored in the register file accordingly.
In addition, when not changing, do not change the data ground of reading and directly carry out calculation process.
In addition, arithmetic processing circuit 522 is striden a plurality of register-stored in register the time in data, according to the reduction of data data of reading from these registers, and the data after the reduction is carried out the calculation process of being determined by the operational order decoded signal.And, the data that the execution calculation process obtains are striden a plurality of register-stored in register file 510.
(3) possess storer and write control circuit 530, replace storer to write control circuit 330.
Storer writes control circuit 530 and writes control circuit 330 with storer and compare, and difference is: possess data attribute decision circuitry 531 and data converting circuit 532, come surrogate data method determined property circuit 331 and data converting circuit 332.
Data attribute decision circuitry 531 from register file 510 read with by the corresponding mark value of storage instruction decoded signal established data, and judge the attribute of these data according to the mark value of reading.And, judged result is judged that as data attribute signal outputs to data converting circuit 530.And, will write control signal according to the storer of storage instruction decoded signal and mark value and output to storer.
In addition, when not changing, do not change the data ground of reading and directly output to storer 14.
In addition, data converting circuit 532 is striden a plurality of register-stored in register file 510 time in data, and according to the reduction of data data of reading from these registers, and the data after will reducing output to storer 14.
Then, as an example, the formation of the arithmetical unit in the embodiment 5 is described.
Here, so that the data of striding the storage of register (Reg#0) and register (Reg#1) are carried out addition process, and will carry out data that addition process obtains, be that the situation that the branch as a result of addition cedes territory to be stored in register (Reg#2) and the register (Reg#3) is that example illustrates.
Figure 21 is the figure of expression as the formation of the arithmetical unit of an example, embodiment 5.
As shown in the figure, data attribute decision circuitry 521 is from the tag field 511 mark-sense values of register (Reg#0), and, judge with the corresponding data of mark value of reading it whether is to stride the data that register (Reg#0) and register (Reg#1) are stored according to the mark value of reading.And, be that the data attribute of striding this situation of data of register (Reg#0) and register (Reg#1) storage is judged signal with expression, output to selector switch 541, totalizer 542, selector switch 543.
Relative therewith, selector switch 541 is from the data of data field 512 output of register (Reg#0) with from the data of data field 512 outputs of register (Reg#1), selects from the data of data field 512 outputs of register (Reg#1) and outputs to totalizer 542.
And, it is high-order portion that totalizer 542 makes from the data of data field 512 outputs of register (Reg#0), make from the data of selector switch 541 output, promptly the data from data field 512 outputs of register (Reg#1) are low portion, and in conjunction with high-order portion and low portion, restoring data.And, the data after the reduction are carried out addition process, will carry out data that addition process obtains, be that the result of addition is divided into high-order portion and low portion, and output to selector switch 543 respectively.In addition, low portion is stored in the data field of register (Reg#3).
And selector switch 543 is from the high-order portion and low portion of totalizer 542 outputs, and the selection high-order portion also is stored in the data field 512 of register (Reg#2).
Then, as an example, the data structure of the register of embodiment 5 is described.
Figure 22 is the figure of expression as the data structure of the register of an example, embodiment 5.
As shown in the figure, the register of the register of embodiment 5 and embodiment 1 is at the difference of following (2).
(1) the 0th of tag field 551 the to the 3rd low level is 4, and is identical with the 0th to the 3rd 4 of low levels of tag field 151, therefore omits explanation.
(2) 2 of the 4th of tag field 551 the to the 5th, compare with the 4th to the 5th of tag field 151 2, (d) when being " 11 ", be different on 64 this point.At this moment, the size of data field keeps 32, distributes the data field 553 of a plurality of registers.
(3) 2 of the 6th of tag field 551 the to the 7th, identical with the 6th to the 7th of tag field 151 2, therefore omit explanation.
The action of the processor in the embodiment 5 then, is described.
Figure 23～Figure 25 is the figure of action of the processor of expression embodiment 5.
As Figure 23～shown in Figure 25, processor 500 is compared with the processor 300 of embodiment 3, has the difference of following (1)～(3).
Action when (1) carrying out about load instructions, (step S111～S114, S121～S122) compare exist following difference (with reference to Fig. 8 A, Figure 23 with the action of embodiment 3.)。
Action when (2) carrying out about operational order, (step S131～S135, S341～S346) compare exist following difference (with reference to Figure 15 A, Figure 24 with action in the embodiment 3.)。
Action when (3) carrying out about storage instruction, and the action in the embodiment 3 (step S151～S153, S361～S365) compare, there is following difference (with reference to Figure 15 A, Figure 25).
Storer writes control circuit 530, striding a plurality of register-stored (step 561: not) when writing the control signal established data by storer, according to the reduction of data data (step S562) of reading from these registers, and the data after will reducing output to storer 14 (step S365).
Processor according to aforesaid embodiment 5, in register file 510, possess tag field 511 and data field 512, in arithmetical unit 520, possess data attribute decision circuitry 521 and arithmetic processing circuit 522, write at storer and possess data attribute decision circuitry 531 and data converting circuit 532 in the control part 530.
Thus, can easily handle the size data bigger than data field 512.
(embodiment 6)
Below, with reference to description of drawings embodiments of the present invention 6.
The processor of embodiment 6 is characterised in that, strides a plurality of register-stored sizes data bigger than data field.And, according to the reduction of data data of striding a plurality of register-stored, and to the execution of the data after reduction calculation process.
According to above-mentioned aspect, the processor in the embodiment 6 is described.
In addition, to the additional same-sign of the inscape identical, and omit explanation with embodiment 5.
Figure 26 is the figure of formation of the processor of expression embodiment 6.
As shown in the figure, processor 600 is compared with the processor 500 in the embodiment 5, and the difference that has following (1)～(3) is (with reference to Fig. 7.)。
(1) possesses instruction decoding circuit 601, replace instruction decoding circuit 101.
(2) possess mark value generative circuit 602, replace mark value generative circuit 102.
Mark value generative circuit 602 is compared with mark value generative circuit 102, and difference is: do not generate the mark value that the data attribute that is obtained by the definite calculation process of operational order decoded signal is carried out in expression.
(3) possess arithmetical unit 620, come substitution operation device 520.
Data attribute decision circuitry 621 from register file 610 read with by the corresponding mark value of operational order decoded signal established data, and judge the attribute of these data according to the mark value of reading.And, judged result is judged that as data attribute signal outputs to arithmetic processing circuit 622.And, generate the mark value that the attribute of the data that the calculation process determined by the operational order decoded signal obtains is carried out in expression, and with the mark value that generates with carry out the data that calculation process obtains and store register file 610 accordingly into.
In addition, when not changing, do not change the data ground of reading and directly carry out calculation process.
In addition, arithmetic processing circuit 622 is striden a plurality of register-stored in register file 610 time in data, according to the reduction of data data of reading from these registers, and the data after the reduction is carried out the calculation process of being determined by the operational order decoded signal.And, the data that the execution calculation process obtains are striden a plurality of register-stored in register file 610.
Then, as an example, the formation of the arithmetical unit in the embodiment 6 is described.
Here, so that the data of striding the storage of register (Reg#0) and register (Reg#1) are carried out addition process, and to carrying out data that addition process obtains, be that the result of addition is cut apart, and situation about being stored in register (Reg#2) and the register (Reg#3) is that example describes.
Figure 27 is the figure of expression as the formation of the arithmetical unit in an example, the embodiment 6.
As shown in the figure, data attribute decision circuitry 621 is from the tag field 611 mark-sense values of register (Reg#0), and judges with the corresponding data of mark value of reading it whether is to stride the data that register (Reg#0) and register (Reg#1) are stored according to the mark value of reading.And, be that the data attribute of striding this situation of data of register (Reg#0) and register (Reg#1) storage is judged signal with expression, output to selector switch 641, totalizer 642, selector switch 643 etc.
Relative therewith, selector switch 641 is in the data of exporting from the data field 612 of register (Reg#0) with from the data that the data field 612 of register (Reg#1) is exported, the data that selection is exported from the data field 612 of register (Reg#1), and output to totalizer 642.
And, it is high-order portion that totalizer 642 makes from the data of data field 612 outputs of register (Reg#0), make from the data of selector switch 641 output, promptly the data from data field 612 outputs of register (Reg#1) are low portion, and in conjunction with high-order portion and low portion, restoring data.And, the data after the reduction are carried out addition process, will carry out data that addition process obtains, be that the result of addition is divided into high-order portion and low portion, and output to selector switch 643 respectively.In addition, low portion is stored in the data field of register (Reg#3).
And selector switch 643 is from the high-order portion and low portion of totalizer 642 outputs, and the selection high-order portion also is stored in the data field 612 of register (Reg#2).
And, it is the mark value of striding this situation of data of register (Reg#2) and register (Reg#3) storage that data attribute decision circuitry 621 generates about the mark value of the result of addition in totalizer 642, i.e. expression, and the mark value that generates is stored in the tag field 611 of register (Reg#2).
The action of the processor 600 in the embodiment 6 then, is described.
Figure 28, Figure 29 are the figure of action of the processor of expression embodiment 6.
As Figure 28, shown in Figure 29, processor 600 is compared with the processor in the embodiment 5, has the difference of following (2).
Action when (1) carrying out about load instructions is with action (step S111～S114, S121～S122, S521～S522) identical, the therefore omission explanation of embodiment 5.
Action when (2) carrying out about operational order, (step S131～S135, S341～S346, S541～S544) compare exist following difference (with reference to Fig. 7, Figure 24, Figure 28, Figure 29 with the action of embodiment 5.)。
Replace the action (step S131) of the instruction decoding circuit 101 of embodiment 5, instruction decoding circuit 601 when the instruction of decoding is operational order, outputs to arithmetical unit 620 (step S631) with the operational order decoded signal.
In addition, replace the action (step S135) of the mark value generative circuit 102 of embodiment 5, arithmetical unit 620, in data attribute decision circuitry 621, expression carried out the mark value of the attribute of the data that calculation process obtains, be stored in accordingly in the tag field 611 of register file 610 (step S641) with these data.
Action when (3) carrying out about storage instruction is with action (step S151～S153, S361～S365, S561～S562) identical, the therefore omission explanation of embodiment 5.
Thus, can easily handle the size data bigger than data field.In addition, because in the mark value of carrying out the attribute of these data of additional representation on the data that calculation process obtains, so needn't can realize the reduction of instruction number, the simplification of instruction decoding circuit to the attribute of the instruction specific data of carrying out calculation process.
(other)
In addition, the mark value generative circuit, when striding a plurality of register-stored from data that storer is read, also can generate the register that comprises storage that these data are crossed over quantity, be cutting apart of data of several mark value, and be stored in the tag field.
In addition, processor also can be realized by full customization (full custom) LSI (Large Scale Integration).In addition, also can realize by semi-custom (semi-custom) LSI as ASIC (Application Specific Integrated Circuit) etc.In addition, also can realize by programmable logic device (PLD) as FPGA (Fild Programmable GateArray), CPLD (Complex Programmable Logic Device) etc.In addition, also can be embodied as the dynamic restructuring device that circuit structure is dynamically rewritten.
And, in these LSI, form to constitute 1 design data of processor to the function more than 2, also by as the hardware of VHDL (Very high speed integrated circuit Hardware DesciptionLanguage), Verilog-HDL, SystemC etc. record and narrate the program (below be called the HDL program) of language record.In addition, also can be the net table (netlist) of the gate leve (gate level) that the synthetic HDL program of logic obtains.In addition, also can be macroelement (macrocell) information of in the net table of gate leve, having added configuration information, treatment conditions etc.In addition, also can be mask (mask) data of having stipulated size, timing etc.
And design data also can be recorded in optical record medium (for example, CD-ROM etc. in advance.), magnetic recording medium (for example, hard disk etc.), magneto-optic recording medium (for example, MO etc.), semiconductor memory (for example, RAM etc.) wait in the recording medium of such embodied on computer readable, so that can read by hardware systems such as computer system, built-in systems.And the design data through recording medium is read by other hardware systems also can download to programmable logic device (PLD) through download cable.
Perhaps, design data also can remain in the hardware system on the transfer path, so that can obtain via transfer paths such as networks and by other hardware systems in advance.And the design data from hardware system is obtained by other hardware systems through transfer path also can download to programmable logic device (PLD) through download cable.
Perhaps, logic design data synthetic, that dispose, connect up also can be recorded among the serial ROM in advance, so that can be sent to FPGA when energising.And the design data that is recorded among the serial ROM also can be directly downloaded to FPGA when energising.
Utilizability on the industry
The present invention can be utilized as the processor of deal with data etc., especially carries out and need to carry out high speed, huge The processor processed of the medium such as the sound processed of computing, image processing.
Claims (14)
1, a kind of processor is characterized in that, possesses:
Register file with a plurality of registers; With
Generate the generation unit of the mark value of expression data attribute,
Described each register has data field that keeps data and the tag field that keeps described mark value,
When the load instructions of carrying out from the memory load to the register, described generation unit generates described mark value according to described load instructions, and stores described tag field into.
2, processor according to claim 1 is characterized in that:
By carrying out the load instructions of data from described memory load to described register, described data field former state keeps from the data of described storer output.
3, processor according to claim 2 is characterized in that:
Described generation unit generates described mark value according to address, size of data and data type by described load instructions appointment,
The data that described data types to express should transmit are data or the codeless data that have code.
4, processor according to claim 3 is characterized in that:
Described processor also possesses converting unit, and conversion remains on the data in the data field of described register according to described mark value.
5, processor according to claim 4 is characterized in that:
Described converting unit is carried out zero expansion or code expansion according to described mark value to the data in the data field that remains on described register.
6, processor according to claim 5 is characterized in that:
When carrying out the instruction of readout register, described converting unit is carried out described conversion.
7, processor according to claim 5 is characterized in that:
Described converting unit is not carried out described conversion in the idling cycle of reading and writing according to the register of instruction takes place, and according to transformation result update mark field and data field.
8, processor according to claim 4 is characterized in that:
During the storage instruction of the data storage in carrying out the data field will remain on described register in storer, described converting unit is carried out conversion.
9, processor according to claim 8 is characterized in that:
Described processor also has the handling part of writing, by the processing that writes corresponding to described mark value, and will be by described converting unit data converted write store.
10, processor according to claim 2 is characterized in that:
Described processor cut apart the data of reading from storer, and the data storage that will cut apart is in 2 above data fields carrying out when storer is read the load instructions of the size data bigger than described data field.
11, processor according to claim 10 is characterized in that:
Described generation unit will comprise cutting apart of the described data of cutting apart several mark value and be stored in the tag field.
12, processor according to claim 11 is characterized in that:
Described preparation implement received shipment is calculated handling part, read data in the data field that is stored in described register, and carry out when carrying out the operational order of calculation process in execution, according to the described number of cutting apart, in conjunction with being stored in 2 data in the above data field, restoring data, and to the execution of the data after reduction calculation process.
13, processor according to claim 12 is characterized in that:
Described arithmetic processing section, when calculation process result's size is bigger than data field, stride 2 above data fields and store the calculation process result, and expression is striden the mark value of 2 described operation results of above data field stores, corresponding with described calculation process result, be stored in the described tag field.
14, processor according to claim 11 is characterized in that:
Described processor is when carrying out the storage instruction of the writing data into memory that size is bigger than described data field, and the data of 2 above data field stores are striden in reduction, and the writing data into memory after will reducing.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004304400 | 2004-10-19 | ||
| JP304400/2004 | 2004-10-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101044450A true CN101044450A (en) | 2007-09-26 |
Family
ID=36202771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005800358326A Pending CN101044450A (en) | 2004-10-19 | 2005-03-01 | Processor |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20070255928A1 (en) |
| JP (1) | JPWO2006043345A1 (en) |
| CN (1) | CN101044450A (en) |
| TW (1) | TW200614074A (en) |
| WO (1) | WO2006043345A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102622206A (en) * | 2011-01-28 | 2012-08-01 | 中兴通讯股份有限公司 | Processor and data processing method thereof |
| CN105453030A (en) * | 2013-06-28 | 2016-03-30 | 英特尔公司 | Mode dependent partial width load to wider register processors, methods, and systems |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006134693A1 (en) * | 2005-06-15 | 2006-12-21 | Matsushita Electric Industrial Co., Ltd. | Processor |
| WO2007074583A1 (en) * | 2005-12-27 | 2007-07-05 | Matsushita Electric Industrial Co., Ltd. | Processor having a reconstitutable functional unit |
| CN101361039A (en) * | 2006-01-20 | 2009-02-04 | 松下电器产业株式会社 | Processor |
| US20080270658A1 (en) * | 2007-04-27 | 2008-10-30 | Matsushita Electric Industrial Co., Ltd. | Processor system, bus controlling method, and semiconductor device |
| US20090157334A1 (en) * | 2007-12-14 | 2009-06-18 | Kenneth Joseph Goodnow | Measurement of power consumption within an integrated circuit |
| US7715995B2 (en) * | 2007-12-14 | 2010-05-11 | International Business Machines Corporation | Design structure for measurement of power consumption within an integrated circuit |
| JP5263497B2 (en) * | 2008-07-09 | 2013-08-14 | セイコーエプソン株式会社 | Signal processor and semiconductor device |
| JP5263498B2 (en) * | 2008-07-09 | 2013-08-14 | セイコーエプソン株式会社 | Signal processor and semiconductor device |
| CN102609378B (en) * | 2012-01-18 | 2016-03-30 | 中国科学院计算技术研究所 | A kind of message type internal storage access device and access method thereof |
| WO2015089314A1 (en) * | 2013-12-11 | 2015-06-18 | Mill Computing, Inc. | Computer processor employing operand data with associated meta-data |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60134937A (en) * | 1983-12-23 | 1985-07-18 | Hitachi Ltd | Address extension device |
| JPS63216129A (en) * | 1987-03-04 | 1988-09-08 | Mitsubishi Electric Corp | Register constitution system |
| JPH0628034B2 (en) * | 1988-10-24 | 1994-04-13 | 工業技術院長 | Calculator with tag |
| JP3546980B2 (en) * | 1996-03-29 | 2004-07-28 | 松下電器産業株式会社 | Data processing device |
| US5978901A (en) * | 1997-08-21 | 1999-11-02 | Advanced Micro Devices, Inc. | Floating point and multimedia unit with data type reclassification capability |
| JP3123047B2 (en) * | 1998-10-02 | 2001-01-09 | 日本電気株式会社 | Microprocessor |
| JP3805578B2 (en) * | 1999-09-14 | 2006-08-02 | 松下電器産業株式会社 | Processor |
| JP4158496B2 (en) * | 2002-11-18 | 2008-10-01 | 松下電器産業株式会社 | Image processing device |
| JP2004280924A (en) * | 2003-03-14 | 2004-10-07 | Oki Electric Ind Co Ltd | Memory test circuit |
| EP1460519B1 (en) * | 2003-03-18 | 2014-05-07 | Panasonic Corporation | Processor, driving method thereof, and information processing device |
-
2005
- 2005-03-01 CN CNA2005800358326A patent/CN101044450A/en active Pending
- 2005-03-01 WO PCT/JP2005/003356 patent/WO2006043345A1/en active Application Filing
- 2005-03-01 US US11/575,756 patent/US20070255928A1/en not_active Abandoned
- 2005-03-01 JP JP2006542233A patent/JPWO2006043345A1/en active Pending
- 2005-03-07 TW TW094106774A patent/TW200614074A/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102622206A (en) * | 2011-01-28 | 2012-08-01 | 中兴通讯股份有限公司 | Processor and data processing method thereof |
| CN105453030A (en) * | 2013-06-28 | 2016-03-30 | 英特尔公司 | Mode dependent partial width load to wider register processors, methods, and systems |
| CN105453030B (en) * | 2013-06-28 | 2019-02-15 | 英特尔公司 | Processor, the method and system loaded dependent on the partial width of mode is carried out to wider register |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200614074A (en) | 2006-05-01 |
| US20070255928A1 (en) | 2007-11-01 |
| JPWO2006043345A1 (en) | 2008-05-22 |
| WO2006043345A1 (en) | 2006-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101044450A (en) | Processor | |
| CN1296833C (en) | Device and method for storage management | |
| CN1875345A (en) | Extensible type system for representing and checking consistency of program components during the process of compilation | |
| CN1469241A (en) | Processor, program transformation apparatus and transformation method and computer program | |
| CN1677570A (en) | Nonvolatile semiconductor memory device for writing multivalued data | |
| CN1498367A (en) | Information processing device, momery management device, memory management method and information processing method | |
| CN1860441A (en) | Efficient high performance data operation element for use in a reconfigurable logic environment | |
| CN1763743A (en) | System and method for automatic label placement on charts | |
| CN101040306A (en) | Pseudo random number generation device | |
| CN1749958A (en) | Common charting using shapes | |
| CN1453687A (en) | Communication apparatus and system, insert module control method and recording media | |
| CN1744036A (en) | Systems and methods for supporting custom graphical representations in reporting software | |
| CN1977531A (en) | Program creation device, program test device, program execution device, information processing system | |
| CN1813252A (en) | Information processing method, information processing program, information processing device, and remote controller | |
| CN1991798A (en) | Semiconductor storage apparatus | |
| CN1776621A (en) | Program converting method | |
| CN1160704C (en) | Musical interval changing device | |
| CN1106941A (en) | Method, system, equipment and multiplier for automatic design of logic circuit | |
| CN101078994A (en) | Compiler apparatus, compiler method, and compiler program | |
| CN1148744C (en) | Modulation device and method and distribution medium | |
| CN1624698A (en) | High level synthesis method and high level synthesis apparatus | |
| CN1296825C (en) | Simulator and simulation method | |
| CN1950803A (en) | Nonvolatile storage device and data write method | |
| CN1577266A (en) | Program converting method, program and storage medium | |
| CN1145878C (en) | Processor with reduced hardware quantity and command converter with reduced command class |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |