CN1716596B - 微电子模块中产生静电放电保护的方法及相应微电子模块 - Google Patents
微电子模块中产生静电放电保护的方法及相应微电子模块 Download PDFInfo
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Abstract
一种在一微电子模块中产生一静电放电(electrostaticdischarge,ESD)保护的方法,该微电子模块包含一半导体电路,其包含至少二独立电压供应域,其分别具有至少一电压供应连结衬垫,其与一对应的微电子模块一起揭露。在本案中,在二独立电压供应域的二电压供应连结衬垫间存有一电连结,其在该半导体电路外排定路线,且,举例来说,是藉由一连结线或是一焊接点而实现。
Description
技术领域
本发明是关于一种用以产生ESD保护的方法(抗静电放电保护,protection against electrostatic discharge),以及关于一种藉由此方法所实现的微电子模块。
背景技术
在本案中,微电子模块包含一微电子电路或是一半导体电路,以及一套件,其尤其包含该微电子模块与外界的一接口。
一种适当的集成电路或是微电子组件的ESD保护需要低阻抗电流放电路径。如果该微电子模块包含复数个独立的电压供应域,则根据先前计数,必须要在这些独立的电压供应域间建立一个低阻抗的电连结,至少建立在个别独立电压供应域的接地供应或参考电位供应之间。此低阻抗电连结,其亦称为接地供应耦合,具有会导致从一独立电压供应域注入另一邻近电压供应域干扰的缺点。
根据先前技术,下述所存在的方法,是经由一共享接地网络以防止注入干扰,该共享接地网络由低阻抗电连结所构成。
第一种以共享接地网络实施的方法是经由二极管耦合独立电压供应域,此会导致以此实现的微电子模块的ESD电阻,会比经由一共享接地网络耦合的独立电压供应域还要小。
第二种方法是在两个独立的电压供应域间耦合,藉由置于个别独立电压供应域的两衬垫间的去耦合bow提供耦合。依照此方法,个别独立电压供应域必须增加一衬垫,导致微电子模块衬垫数量增加的问题。
第三种以共享接地网络实施的方法是经由二极管及非常复杂的额外保护方法提供耦合效应,此方法的缺点在于增加该微电子模块区域的需求。
本发明的目的因此基于在独立电压供应域之间提供一低阻抗电连结,使得邻近独立电压供应域的干扰不会因此注入,且前述方法所描述的缺点也不会发生。
根据本发明,此目的是藉由根据本发明的方法及根据根据本发明的微电子模块所达成,用以产生微电子模块中的ESD保护。本发明较佳且具有优点的实施例也得以具体说明。
发明内容
本发明的保护范围提供一种在一微电子模块中产生ESD保护的方法,该模块包含一半导体电路,其包含一第一及第二独立电压供应域,其依序分别具有至少一电压供应结合衬垫,尤其是用以终止一外部接地供应电压或是参考电位。在本案中,该第一独立电压供应域的该电压供应结合衬垫,与该第二独立电压供应域的该电压供应结合衬垫之间建立有一电连结,其在该半导体电路外部排定线路,且举例来说,藉由一结合线或是一焊接点或是一焊接球所实现。
根据本发明的方法,其具有下列优点。因为该电连结是在该半导体电路外部排定线路,因此该电连结并不会影响该微电子模块的该半导体电路,但还是在该微电子模块的套件中实现,根据本发明的方法因此便不具有区域需求或是半导体电路的衬垫数量反效果。除此之外,与在该半导体电路中实现电连结的方法相比,本方法非常易于中断介于该第一和第二独立电压供应域的电连结以供测试用途。对比之下,如果该电连结置于半导体电路中,则几乎不可能在不毁坏该半导体电路下中断此类连结。
根据本发明,该电连结可提供的电感,会比经由一连结线所排定线路的电连结更高,该连结线还必须越短越好,且举例来说,置于该第一独立电压供应域的该电压供应连结衬垫,及该第二独立电压供应域的该电压供应连结衬垫之间。
增加电感尤其在高频率干扰的去耦合方面表现较佳,因此举例来说,可以更有效率地防范由该第一独立电压供应域,经由该电连结所注入该第二独立电压供应域的干扰。在此必须指出在其它方面的参数相等下,电感会随着电连结的长度增加,亦即较长的电连结具有较高的电感。
该电连结尤其可经由该微电子模块的套件内的内部终端排定路线。为此,该第一和第二独立电压供应域的电压供应结合衬垫可分别经由一连结线或是仅由一焊接点,连接至一第一和第二内部终端,此两内部终端亦互相电连结。根据本发明,两内部终端之间的电连结方式有数种可能,一方面两内部终端可藉由一金属层组成的互连套件连接,且在该套件内排定路线,另一方面两内部终端的电连结可经由该套件的另一终端排定路线,其依序电连结。在本例中,该电连结可于两内部终端之一及另一终端之一间产生效应,或是在另一终端间产生效应,其经由一连结线或是互连套件。根据本发明,在本例中,介于该两内部终端之间的电连结可包含一电感器,例如线圈。
根据本发明,一独立电压供应域的电压供应连结衬垫亦可经由其自身的电连结,来连结至该微电子模块套件的外部终端,亦即此电连结并未额外使用另一个独立电压供应域,该外部终端连结至一外部电压供应,尤其是一接地供应电压或是参考电位,例如线圈。
在此必须指出,所描述关于一独立电压供应域,其自身经由对应电压供应连结衬垫所建立至外部终端的电连结特征,是独立于先前所描述关于藉由一电连结来连结两独立电压供应域的特征。
由于一独立电压供应域经由其自身的电连结,连结至该外部电压供应,因此可减少由一邻近独立电压供应域注入此独立电压供应域的干扰,其与此电压供应域及该邻近独立电压供应域,经由一至少部分共享电连结来连结至外部电压供应相比。
在本例中,介于该独立电压供应域及该外部终端或是外部电压供应之间的实际电连结,能藉由一内部终端所达成。为此,举例来说,该独立电压供应域的电压供应连结衬垫能经由一连结线或是一焊接点连结至此内部终端,且该内部终端可经由一互连套件连接至该外部终端。根据本发明,同一个内部终端可作为该电压供应域及外部电压供应之间的电连结,亦可作为介于该独立电压供应域及一邻近独立电压供应域之间的电连结。
由于使用同一个内部终端作为两个电连结,因此内部终端使用数量亦可减少。
本发明的保护范围亦提供一种微电子模块,其包含一半导体电路,其包含一第一和第二独立电压供应域,其皆具有一个别电压供应连结衬垫。在本例中,此两电压供应连结衬垫之间,且因此两独立电压供应域之间存在有一电连结,其是在该半导体电路外排定线路。
其优点与先前所描述在微电子模块中产生ESD保护方法的优点相同,因此在此不再赘述。
附图说明
本发明是在下文中参照附图及较佳实施方式做更完整的解释。
图1所示为根据本发明具有ESD保护的微电子模块,其中插入一电感器用以去耦合独立电压供应域。
图2所示为另一根据本发明具有ESD保护的微电子模块,以及独立电压供应域之间去耦合。
具体实施方式
图1所示为一微电子模块1,其包含一半导体电路9,其具有两个独立电压供应域8,每一独立电压供应域8具有一电压供应连结衬垫4,其经由一连结线5连结至一内部终端3,(在另一实施方式中,介于该电压供应连结衬垫4及该内部终端3之间的连结,亦可仅由一焊接点取代该连结线5来实现),每一内部终端3经由一互连套件6,连结至该微电子模块1的一外部终端2,且经由一连结线5连结至另一内部终端3’。两个内部终端3’是藉由一电感器7互相连结,其可藉由例如线圈达成,藉此具有一高电感的一低组抗电连结,建立于两独立电压供应域8的电压供应连结衬垫4之间。
该微电子模块1的ESD保护现在将参照图1描述。如果一独立电压供应域8发生一静电放电时,举例来说,其放电可藉由人体接触所引起,大多数静电放电的消除是透过该电压供应连结衬垫4,经由该连结线5、该内部终端3及该互连套件6所形成的路径,最后到达该外部终端2。在本例中,该外部终端2处于可为一正或负供应电压的一供应电位,或是参考电位。
然而,所有的静电放电能量并无法经由前述路径消散,因此便有另一个传播路径经由两电压供应连结衬垫4的电连结,该路径藉由该电感器7排定路线。由于该静电放电所受影响独立电压供应域8的负载减少,因此部分并未经由该外部终端2所消散的静电放电能量,便平均地分布于两个独立电压供应域8中。
在两电压供应连结衬垫4的电连结中的电感器7,防止由正常操作所产生,通常为高频率的干扰,不会经由此电连结所传导,因为该电感器7的电阻抗会随着该干扰频率而增加。举例来说,若一独立电压供应域8为一数字电路,而其它独立电压供应域8为一模拟电路,便可因此防止由该数字电路产生的干扰传至该模拟电路中。
图2所示为一微电子模块1,其本质上与图1所示微电子模块非常类似,除了图2所示微电子模块包含一半导体电路9,其由四个独立电压供应域8所构成。每一独立电压供应域8具有一电压供应连结衬垫4,每一独立电压供应域由该微电子模块1的一外部终端2以参考电位供应。每一电压供应连结衬垫4经由一连结线5连结至微电子模块1中个别相关的内部终端3。总共四个内部终端3,其分别分派给电压供应连结衬垫4,每一内部终端3是皆着经由一互连套件6连结至该微电子模块1的一外部终端2,每该外部终端2是连结至参考电位(图上未示)。除此之外,每该内部终端3经由一连结线5,分别连结至两个分派给他额外内部终端3’。总共八个额外内部终端3’中的两个分别连结至一互连套件6。因此由该四个内部终端3及该八个额外内部终端3’,便以其相关连结形成一个环,在实施方式所示,其连结由一连结线5及互连套件6所构成。透过这个环,四个独立电压供应域8互相连结,形成一个非常有效的ESD保护结构,因为部分未经由外部终端2消散的静电放电能量,可藉由此环传导至四个独立电压供应域8,而使得每一独立电压供应域8仅接收此能量的一部分。
在此实施方式中,该连结线5在环中分别插在四个内部终端3其中之一及八个额外内部终端3’其中之一只间,其当然能单独或全部由一互连套件所取代。同样地,在环中分别插在八个额外内部终端3’其中之二之间的互连套件6,亦可由连结线或至少部分地由电感器所取代。
总结来说,图2所示为一微电子模块1,其因为前述所描述的环而具有非常好的ESD保护,而不需要扩充该半导体电路9。在本例中,每一独立电压供应域具有一单独分派的电连结,至该微电子模块1的一外部终端2。
Claims (20)
1.一种在一微电子模块中产生一静电放电(ESD)保护的方法,该微电子模块包含一半导体电路,其包含至少二独立电压供应域,其分别具有至少一电压供应连结衬垫,其中
在该独立电压供应域其一的该电压供应连结衬垫与另一该独立电压供应域的至少一额外电压供应连结衬垫之间,建立一ESD保护的电连结,该ESD保护的电连结在该半导体电路外排定路线并具有一连结线或一焊接点,
经由该连结线或是该焊接点而连结至该独立电压供应域其一的该电压供应连结衬垫其一的所有该微电子模块的内部终端,以一环的形式互相电连结。
2.如权利要求1所述的方法,其中
该电连结有一较高的电感,该较高的电感高于经由一假想连结线所排定路线的一假想电连结,其中该假想连结线越短越好,且该假想电连结是介于该独立电压供应域其一的该电压供应连结衬垫与另一该独立电压供应域的该至少一额外电压供应连结衬垫之间。
3.如权利要求1所述的方法,其中
该独立电压供应域其一的该电压供应连结衬垫及另一该独立电压供应域的该至少一额外电压供应连结衬垫分别经由该连结线或该焊接点而连结至该微电子模块的一内部终端,该微电子模块的该内部终端被分派给该独立电压供应域其一的该电压供应连结衬垫及另一该独立电压供应域的该至少一额外电压供应连结衬垫,其中至少二该微电子模块的内部终端互相电连结。
4.如权利要求3所述的方法,其中
介于该至少二内部终端之间的该电连结通过一互连套件及/或一连结线而实现,且/或介于该至少二内部终端之间的该电连结包含额外内部终端,其中介于该二内部终端其一与该额外内部终端其一之间的该电连结、或是在该额外内部终端之间的该电连结,通过一互连套件或是一连结线而实现。
5.如权利要求3所述的方法,其中
介于该至少二内部终端之间的该电连结通过至少一电感器而实现。
6.如权利要求1所述的方法,其中
该独立电压供应域其一的至少一电压供应连结衬垫是经由其自身的一电连结而连结至该微电子模块的一外部终端,其中该外部终端连结至一外部电压供应。
7.如权利要求6所述的方法,其中
该至少一电压供应连结衬垫利用一接地供应电压而供应对应的电压域,且该接地供应电压由该外部电压供应所提供。
8.如权利要求6所述的方法,其中
该至少一电压供应连结衬垫经由一连结线或是一焊接点,而连结至该微电子模块的一内部终端,其中该内部终端经由一互连套件连结至该外部终端。
9.如权利要求3所述的方法,其中
该独立电压供应域其一的至少一电压供应连结衬垫是经由其自身的一电连结而连结至该微电子模块的一外部终端,其中该外部终端连结至一外部电压供应,同一个内部终端作为介于该独立电压域其一的该至少一电压供应连结衬垫与该外部终端之间的一电连结,该至少一电压供应连结衬垫经由一连结线或是一焊接点而连结至该内部终端,且同一个内部终端作为介于该独立电压供应域其一的该至少一电压供应连结衬垫与另一该独立电压供应域的至少一额外电压供应连结衬垫之间的一电连结,该至少一电压供应连结衬垫及该至少一额外电压供应连结衬垫同样经由一连结线或是一焊接点而连结至另一个内部终端。
10.如权利要求1所述的方法,其中
该微电子模块的一外部终端,至多连结至该独立电压供应域其一的该电压供应连结衬垫其一。
11.一种微电子模块,其包含一半导体电路,该半导体电路包含至少二独立电压供应域,其分别具有至少一电压供应连结衬垫,其中
在该独立电压供应域其一的该电压供应连结衬垫与另一该独立电压供应域的至少一额外电压供应连结衬垫之间,存有一ESD保护的电连结,该ESD保护的电连结在该半导体电路外排定路线并具有一连结线或一焊接点,
经由该连结线或是该焊接点而连结至该独立电压供应域其一的该电压供应连结衬垫其一的所有该微电子模块的内部终端,以一环的形式互相电连结。
12.如权利要求11所述的微电子模块,其中
该电连结有一较高的电感,该较高的电感高于经由一假想连结线所排定路线的一假想电连结,其中该假想连结线越短越好,且该假想电连结是介于该独立电压供应域其一的该电压供应连结衬垫与另一该独立电压供应域的该至少一额外电压供应连结衬垫之间。
13.如权利要求11所述的微电子模块,其中
该独立电压供应域其一的该电压供应连结衬垫及另一该独立电压供应域的该至少一额外电压供应连结衬垫分别经由该连结线或该焊接点而连结至该微电子模块的一内部终端,该微电子模块的该内部终端被分派给该独立电压供应域其一的该电压供应连结衬垫及另一该独立电压供应域的该至少一额外电压供应连结衬垫,其中至少二该微电子模块的内部终端互相电连结。
14.如权利要求13所述的微电子模块,其中
介于该至少二内部终端之间的该电连结为一互连套件及/或一连结线,且/或介于该至少二内部终端之间的该电连结包含额外内部终端,其中介于该二内部终端其一与该额外内部终端其一之间的该电连结、或是在该额外内部终端之间的该电连结,为一互连套件或是一连结线。
15.如权利要求13所述的微电子模块,其中
介于该至少二内部终端之间的该电连结包含至少一电感器。
16.如权利要求11所述的微电子模块,其中
该独立电压供应域其一的至少一电压供应连结衬垫是经由其自身的一电连结而连结至该微电子模块的一外部终端,其中该外部终端连结至一外部电压供应。
17.如权利要求16所述的微电子模块,其中
该至少一电压供应连结衬垫利用一接地供应电压而供应对应的电压域,且该接地供应电压由该外部电压供应所提供。
18.如权利要求16所述的微电子模块,其中
该至少一电压供应连结衬垫经由一连结线或是一焊接点而连结至该微电子模块的一内部终端,其中该内部终端经由一互连套件连结至该外部终端。
19.如权利要求13所述的微电子模块,其中
该独立电压供应域其一的至少一电压供应连结衬垫是经由其自身的一电连结而连结至该微电子模块的一外部终端,其中该外部终端连结至一外部电压供应,同一个内部终端作为介于该独立电压供应域其一的该至少一电压供应连结衬垫与该外部终端之间的一电连结,该至少一电压供应连结衬垫经由一连结线或是一焊接点而连结至该内部终端,且同一个内部终端作为介于该独立电压供应域其一的该至少一电压供应连结衬垫与另一该独立电压供应域的至少一额外电压供应连结衬垫之间的一电连结,该至少一电压供应连结衬垫及该至少一额外电压供应连结衬垫同样经由一连结线或是一焊接点而连结至另一个内部终端。
20.如权利要求11所述的微电子模块,其中
该微电子模块的一外部终端,至多连结至该独立电压供应域其一的该电压供应连结衬垫其一。
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5991135A (en) * | 1998-05-11 | 1999-11-23 | Vlsi Technology, Inc. | System including ESD protection |
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US6597227B1 (en) * | 2000-01-21 | 2003-07-22 | Atheros Communications, Inc. | System for providing electrostatic discharge protection for high-speed integrated circuits |
DE10102354C1 (de) * | 2001-01-19 | 2002-08-08 | Infineon Technologies Ag | Halbleiter-Bauelement mit ESD-Schutz |
US20030235019A1 (en) * | 2002-06-19 | 2003-12-25 | Ming-Dou Ker | Electrostatic discharge protection scheme for flip-chip packaged integrated circuits |
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US5991135A (en) * | 1998-05-11 | 1999-11-23 | Vlsi Technology, Inc. | System including ESD protection |
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