CN1714509A - PLL circuit - Google Patents
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- CN1714509A CN1714509A CNA2003801037272A CN200380103727A CN1714509A CN 1714509 A CN1714509 A CN 1714509A CN A2003801037272 A CNA2003801037272 A CN A2003801037272A CN 200380103727 A CN200380103727 A CN 200380103727A CN 1714509 A CN1714509 A CN 1714509A
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- 238000010586 diagram Methods 0.000 description 14
- 230000001360 synchronised effect Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000010295 mobile communication Methods 0.000 description 5
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0997—Controlling the number of delay elements connected in series in the ring oscillator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
- H03L7/102—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator
- H03L7/103—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator the additional signal being a digital signal
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Abstract
A PLL circuit comprises a phase comparator for comparing phases between a reference signal and an internal signal and outputting a phase difference signal according to a phase difference therebetween, a voltage controlled oscillator group composed of a plurality of oscillators which have mutually different frequency variable ranges and whose oscillation frequencies are respectively controlled in accordance with a phase control signal, a selecting means for selecting one of the outputs from the plurality of oscillators based on the phase difference signal or the phase control signal, and a frequency divider for generating the internal signal by dividing an output of an oscillator selected by the selecting means, and when the oscillator selecting state is changed, an output phase of the frequency divider is approximated to the phase of the reference signal. Thereby, a required voltage controlled oscillator can be selected in a short time according to a desirable oscillation frequency.
Description
Technical field
The present invention relates to PLL (phase-locked loop circuit) circuit of built-in voltage control generator, particularly need the PLL circuit of wide vibrating frequency band.
Background technology
Variation along with in recent years mobile communication system, the signal transmitting and receiving of variety of way is carried out in requirement with a mobile communication terminal, but usually, because different mobile communication system has adopted different frequency bands, so require to have the transmitting-receiving number of the sending function of carrying out, promptly so-called multiband radio function with a plurality of frequency bands for this multimode terminal.
The frequency synthesizer that is used for the wireless machine of multiband need generate the local signal of the various frequency bands corresponding with multibandization.For example, the PCS (personal communication service) that the DCS (collective and distributive type control system) of the GSM (global system mobile communication) of employing 900MHz band, employing 1800MHz band, employing 1900MHz are with, the UMTS modes such as (universal mobile telecommunications system) that adopts 2GHz to be with are widely used in the world, and wish to develop the wireless machine of 4 frequency ranges that can use in whole these frequency bands.
When realizing the frequency synthesizer corresponding, need to prepare GSM and send to receive to send to receive to send and receive usefulness/UMTS with, PCS and send and use and each unit synthesizer of UMTS reception usefulness with, PCS with, DCS with, DCS with, GSM with the wireless machine of this 4 frequency ranges.The receive frequency of PCS is roughly consistent because of frequency band with the transmission frequency of UMTS, thus can be by 1 synthesizer dual-purpose, but because of this belongs to special circumstances, thereby to prepare basically and required a plurality of frequency bands unit synthesizer of corresponding number respectively.Therefore, when frequency band number increased, the unit synthesizer increases with it with being directly proportional, and was huge thereby the scale of hardware becomes.
As the method that addresses this is that, can consider to improve the modulation sensitivity of oscillator, and enlarge the method for the variable range of oscillator, but in this case, because the outside of chip and inner noise etc., have the problem that the frequency of local oscillator changes.
In addition, also have the small scale in circuitry of the computing circuit that constitutes by combination frequency divider on 2 unit synthesizers with by the frequency mixer that is used for multiplying to constitute, and generate the formation of quantity more than the signal of a plurality of frequency bands of unit synthesizer.Yet, can not be corresponding with whole compound communication modes, the result has the shortcoming that the quantity of synthesizer increases.
Therefore, proposed to adopt a plurality of voltage-controlled oscillators,, selected the method for voltage-controlled oscillator by external signal according to deserved desirable oscillation frequency with different control voltage-frequency of oscillation characteristics.
In the method, a plurality of voltage-controlled oscillators have different frequency ranges respectively, although therefore the changeable frequency scope of each voltage-controlled oscillator is narrower, generally speaking form wider frequency.Narrower because of the changeable frequency scope of each voltage-controlled oscillator, get final product so the modulation sensitivity of each voltage-controlled oscillator is little, thereby synthesizer is stably moved.
Figure 10 selects a plurality of voltage-controlled oscillators for expression according to external signal, thus the figure of a configuration example of 4 multiple circuits of generation clock signal.
This conventional example, as shown in figure 10, be 4 multiple circuits that constitute by the PLL circuit, this PLL circuit has: phase comparator 1, charge pump 2, loop filter 3, the voltage-controlled oscillator group 4 that constitutes by 4 voltage-controlled oscillators with different control voltage-frequency of oscillation characteristics, select circuit 6, frequency divider 5, N-channel MOS transistor NM5 and resistance R, when the output signal S14 that selects circuit 6 is high potential (H), the NM5 conducting of N-channel MOS transistor and resistance R and MOS transistor NM5 constitute series circuit, the electric current of the output signal S4 of loop filter 3 is left behind thus, thereby the current potential on the electric wire of signal S4 is set to the interior voltage (opening flat 9-214335 communique with reference to the spy) of scope between reference voltage V ref1 described later and the Vref2.
Below, describe for the action of 4 multiple circuits of aforesaid formation.
The output signal S3 of charge pump 2 is input to loop filter 3, in loop filter 3, remove radio-frequency component after, as the control voltage S4 of high voltage control generator group 4 and be input to voltage-controlled oscillator group 4.
In voltage-controlled oscillator group 4, imported signal S10～S13 by selecting circuit 6 to generate, be used for selecting 1 voltage-controlled oscillator from voltage-controlled oscillator group 44 interior voltage-controlled oscillators.The output signal CK3 of voltage-controlled oscillator group 4 by 4 frequency divisions, becomes internal signal CK2 by frequency divider 5.
In this conventional example, when moving with the frequency of the signal CK2 mode consistent, lock, thereby the frequency of the signal CK3 that obtains from voltage-controlled oscillator group 4 becomes 4 times of reference signal CK1 with phase place according to signal CK1.
Figure 11 is the formation block diagram of expression selection circuit 6 shown in Figure 10.
As the output signal S10 that selects circuit 6～when S13 changes, output signal S14 becomes high potential (H) within a certain period of time, thus, the current potential of signal S4 is by according in threshold voltage Vref1 and Vref2 (the form setting in the scope between the Vref1＞Vref2).
In selecting circuit 6, be provided with voltage comparator 418 with threshold voltage Vref1 and voltage comparator 419 with threshold voltage Vref2.In voltage comparator 418, when the voltage of the control signal S4 that imports is lower than threshold voltage Vref1, output signal S15 is configured to high potential (H), and when the voltage of control signal S4 was higher than threshold voltage Vref1, output signal S15 was set to electronegative potential (L).And, in voltage comparator 419, when the voltage of the control signal S4 that imports was lower than threshold voltage Vref2, output signal S16 was configured to high potential (H), and when the voltage of control signal S4 was higher than threshold voltage Vref2, output signal S16 was set to electronegative potential (L).
In addition, also be provided with: NOR door 420, it is set as signal S17 high potential (H) when signal S15, S16 are electronegative potential (L), and sets electronegative potential (L) in other cases for; AND door 421, it is set as signal S18 high potential (H) when signal S15, S16 are high potential (H), and sets electronegative potential (L) in other cases for; 2 counters 422,423 that add; Subtract and calculate device 424, its output count value S19 from counter 422 deducts the output count value S20 of counter 423; With decoder 425, it is according to calculating the count value S21 that device 424 is imported from subtracting, only with the some high potentials (H) that is set in output signal S10～S13.
By having the selection circuit 6 of this operating characteristics, can from 4 voltage-controlled oscillators, select 1 corresponding voltage-controlled oscillator of 4 overtones bands automatically with the frequency of reference signal CK1 with different control voltage-frequency of oscillation characteristics.
And then, when changing selection modes by selection circuit 6, signal S14 temporarily becomes high potential (H), and the current potential of signal S4 forcibly is set to the value that is higher than threshold voltage Vref1 shown in Figure 12 and is lower than threshold voltage Vref2, therefore the output of NOR door 420 and AND door 421 temporarily returns to electronegative potential (L), thus, can prevent to have the selection mode misoperation of the voltage-controlled oscillator group 4 of different control voltage-frequencies of oscillation.
Figure 12 is the voltage of expression and the control signal S4 of the voltage-controlled oscillator group 4 shown in Figure 10 performance plot to the frequency of oscillation characteristic.In addition, frequency f 1～f8 has following relation: f1＜f2＜f3＜f4＜f5＜f6＜f7＜f8.
At first, the frequency 4 overtones band fosc that promptly are input to the reference signal CK1 of phase comparator 1 for desirable oscillation frequency are that the situation of f1＜fosc＜f2 describes.
When only locking with characteristic D shown in Figure 12, promptly when the voltage of control signal S4 when the scope between threshold voltage Vref1 and threshold voltage Vref2 does not depart from, the output signal S17 of NOR door 420 and AND door 421, S18 do not become high potential (H), therefore, counter 422,423 is not counted action, selects the state of the output signal S10～S13 of circuit 6 can not change from initial condition.
In addition,, transfer to characteristic B when being transferred to characteristic C shown in Figure 12, and final when locked, carry out following action.
When control voltage S4 surpasses threshold voltage Vref2 in characteristic D, the output signal S17 of NOR door 420 becomes high potential (H), the output valve S19 of counter 422 and the output valve S21 that subtracts calculation device 424 add 1, thus, in decoder 425, only there is output signal S13 to switch to the state of electronegative potential (L) from the state of high potential (H), and only there is output signal S12 to switch the state of system high potential (H), thereby is transferred to characteristic C from the state of electronegative potential (L).
When carrying out this switching, signal S14 temporarily becomes high potential (H), and control signal S4 temporarily returns to the voltage of the scope between threshold voltage Vref1 and the threshold voltage Vref2, so the output signal S17 of NOR door 420 becomes electronegative potential (L) from high potential (H).
Even carry out PLL control according to characteristic C like this, also still be lower than the frequency of 4 times of reference signals, and control voltage S4 surpasses threshold voltage Vref2 once more because of the frequency of internal signal, select circuit 6 to carry out above-mentioned action repeatedly, be transferred to characteristic B.At this constantly, voltage-controlled oscillator group 4 is the state of the roughly the same frequency of output and reference signal CK1, but because of the phase place of frequency divider 5 does not change at short notice, so phase comparator 1 still moves according to the form of the frequency gets higher that makes internal signal, the result, control voltage S4 surpasses threshold voltage Vref2 once more, selects circuit 6 to carry out above-mentioned action repeatedly, is transferred to characteristic A.
Its result, the frequency of voltage-controlled oscillator group 4 becomes higher than reference signal, and the phase place of frequency divider 5 is more leading than reference signal, and thus, control voltage S4 falls to threshold voltage Vref1, is transferred to characteristic B once more by selecting circuit 6.
After this, 2 frequencies become equal, and finally lock with characteristic B.
Yet, as mentioned above, utilization has a plurality of voltage-controlled oscillators of different control voltage-frequency of oscillation characteristics, when selecting voltage-controlled oscillator according to desirable oscillation frequency, although can realize the PLL circuit in broadband, even but select suitable voltage-controlled oscillator, the phase place because of frequency divider does not change at short notice yet, so the output of phase comparator can not followed frequency change fully, the result has the problem that needed the very long time before choosing best oscillator.
Because phase place is the integration of frequency, even so select best oscillator, make the internal signal with frequency identical with reference signal be input to phase comparator, becoming lock-out state until the output of phase comparator also needs certain hour, can not become lock-out state at once.
Summary of the invention
The object of the present invention is to provide a kind of PLL circuit, it adopts a plurality of voltage-controlled oscillators with different control voltage-frequency of oscillation characteristics, can select required voltage-controlled oscillator at short notice according to desirable oscillation frequency.
For reaching above-mentioned purpose, PLL circuit of the present invention has: phase bit comparison mechanism, and its phase place to reference signal and internal signal compares, and the output phase signal corresponding with its phase difference; A plurality of oscillators, it has mutually different changeable frequency scope, and according to each phase control signal control frequency of oscillation; Selection mechanism, it is according to described phase signal or described phase control signal, selects 1 in the output of described a plurality of oscillators; With frequency division mechanism, it generates described internal signal by the output frequency division of the oscillator that will be selected by described selection mechanism; Also have the output phase that when the selection mode of described oscillator changes, makes described frequency divider and the approaching mechanism of phase place of described reference signal.
Have, the changeable frequency scope of described a plurality of oscillators is overlapped again.
Have, the action threshold voltage value of described a plurality of oscillators is different mutually again.
Have, described selection mechanism is switched the output of described a plurality of oscillators according to the resume of described phase signal or described phase control signal again.
Have, described oscillator is a voltage-controlled oscillator again, has the mechanism that described phase signal is converted to magnitude of voltage.
Have again, has following mechanism: set its value mutually different 2 threshold voltages in the variable reference voltage of described phase control voltage, when the selection mode of described voltage-controlled oscillator changes, the value of described phase control voltage temporarily is set in the scope of described 2 threshold voltage clampings.
Have, have following mechanism: the resume when changing according to the selection mode of described voltage-controlled oscillator change the value of the temporary transient described phase control voltage of setting.
Have again, when described phase control voltage outside the scope of described 2 threshold voltage clampings and when switching the selection mode of described voltage-controlled oscillator, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
Have again, described phase control voltage is outside the scope of described 2 threshold voltage clampings and when switching the selection mode of described voltage-controlled oscillator, continuous more than 2 times under the extraneous situation at described 2 threshold voltage clampings at described phase control voltage, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
Have again, when described phase control voltage is outside the scope of described 2 threshold voltage clampings,, control whether greater than described 2 threshold voltages or not less than described 2 threshold voltages according to this phase control voltage so that described phase control voltage is set for height or set for low with respect to the intermediate potential of described 2 threshold voltages.
Another PLL circuit of the present invention has: phase bit comparison mechanism, and its phase place to reference signal and internal signal compares, and the output phase signal corresponding with its phase difference; A plurality of resonant circuits, it has mutually different resonance frequency; Oscillator, it is according to described resonant circuit and phase control signal control frequency of oscillation; Selection mechanism, it selects 1 in described a plurality of resonant circuit according to described phase signal or described phase control signal; With frequency division mechanism, it generates described internal signal by the output frequency division to described oscillator; Also have the output phase that when the selection mode of described resonant circuit changes, makes described frequency divider and the approaching mechanism of phase place of described reference signal.
Have, described selection mechanism is switched described a plurality of resonant circuit according to the resume of described phase signal or described phase control signal again.
Have, described oscillator is a voltage-controlled oscillator again, has the mechanism that described phase signal is converted to magnitude of voltage.
Have again, has following mechanism: set its value mutually different 2 threshold voltages in the variable reference voltage of described phase control voltage, when the selection mode of described resonant circuit changes, the value of described phase control voltage temporarily is set in the scope of described 2 threshold voltage clampings.
Have, have following mechanism: the resume when changing according to the selection mode of described resonant circuit change the value of the temporary transient described phase control voltage of setting.
Have again, when described phase control voltage outside the scope of described 2 threshold voltage clampings and when switching the selection mode of described resonant circuit, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
Have again, when described phase control voltage outside the scope of described 2 threshold voltage clampings and when switching the selection mode of described resonant circuit, continuous more than 2 times under the extraneous situation at described 2 threshold voltage clampings at described phase control voltage, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
Have again, when described phase control voltage is outside the scope of described 2 threshold voltage clampings,, control whether greater than described 2 threshold voltages or not less than described 2 threshold voltages according to this phase control voltage so that described phase control voltage is set for height or set for low with respect to the intermediate potential of described 2 threshold voltages.
Another PLL circuit of the present invention has: phase bit comparison mechanism, and its phase place to reference signal and internal signal compares, and the output phase signal corresponding with its phase difference; Oscillator, it connects and composes by controlled a plurality of delay circuits of time of delay according to each phase control signal; Selection mechanism, it selects the number of connection of described delay circuit according to described phase signal or described phase control signal; With frequency division mechanism, the output frequency division that it passes through the oscillator of being selected by described selection mechanism generates described internal signal; Also have the output phase that when the selection mode of described oscillator changes, makes described frequency divider and the approaching mechanism of phase place of described reference signal.
Have, described selection mechanism is switched the number of connection of described delay circuit according to the resume of described phase signal or described phase control signal again.
Have, described oscillator is a voltage-controlled oscillator again, has the mechanism that described phase signal is converted to magnitude of voltage.
Have again, has following mechanism: set its value mutually different 2 threshold voltages in the variable reference voltage of described phase control voltage, when the selection mode of the number of connection of described delay circuit changes, the value of described phase control voltage temporarily is set in the scope of described 2 threshold voltage clampings.
Have, have following mechanism: the resume when changing according to the selection mode of the number of connection of described delay circuit change the value of the temporary transient described phase control voltage of setting.
Have again, when described phase control voltage outside the scope of described 2 threshold voltage clampings and when switching the selection mode of number of connection of described delay circuit, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
Have again, when described phase control voltage outside the scope of described 2 threshold voltage clampings and switch described delay circuit the selection mode of number of connection the time, continuous more than 2 times under the extraneous situation at described 2 threshold voltage clampings at described phase control voltage, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
Have again, when described phase control voltage is outside the scope of described 2 threshold voltage clampings,, control whether greater than described 2 threshold voltages or not less than described 2 threshold voltages according to this phase control voltage so that described phase control voltage is set for height or set for low with respect to the intermediate potential of described 2 threshold voltages.
Have again, make the output phase of described frequency division mechanism and the Phase synchronization of described reference signal.
In the present invention who constitutes as mentioned above, owing to have: phase bit comparison mechanism, its phase place to reference signal and internal signal compares, and the output phase signal corresponding with its phase difference; A plurality of oscillators, it has mutually different changeable frequency scope, and according to each phase control signal control frequency of oscillation; Selection mechanism, it is according to phase signal or phase control signal, selects 1 in the output of a plurality of oscillators; With frequency division mechanism, it generates internal signal by the output frequency division of the oscillator that will be selected by selection mechanism; And owing to the phase place of output phase that makes frequency divider when the selection mode of oscillator changes and reference signal is approaching, therefore, in the PLL circuit that has adopted a plurality of voltage-controlled oscillators with different control voltage-frequency of oscillation characteristics, select required voltage-controlled oscillator at short notice according to desirable oscillation frequency.
Therefore, in the present invention, when adopting a plurality of voltage-controlled oscillators to realize wide band PLL circuit with different control voltage-frequency of oscillation characteristics, because of can in the extremely short time, automatically selecting required voltage-controlled oscillator according to desirable frequency of oscillation, so can be in switching the system that uses a plurality of wireless modes, avoid the chronic phenomenon of frequency setting, thereby be suitable for very much this system.
Description of drawings
Fig. 1 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 1st execution mode of PLL circuit of the present invention for expression.
Fig. 2 is the performance plot of the frequency of oscillation characteristic of the control signal relative voltage of expression voltage-controlled oscillator group shown in Figure 1.
Fig. 3 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 2nd execution mode of PLL circuit of the present invention for expression.
Fig. 4 is the performance plot of the frequency of oscillation characteristic of the control signal relative voltage of expression voltage-controlled oscillator group shown in Figure 3.
Fig. 5 is the performance plot of the frequency of oscillation characteristic of the control signal relative voltage of expression voltage-controlled oscillator group shown in Figure 3.
Fig. 6 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 3rd execution mode of PLL circuit of the present invention for expression.
Fig. 7 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 4th execution mode of PLL circuit of the present invention for expression.
Fig. 8 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 5th execution mode of PLL circuit of the present invention for expression.
Fig. 9 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 6th execution mode of PLL circuit of the present invention for expression.
Figure 10 selects a plurality of voltage-controlled oscillators to generate the figure of a configuration example of 4 multiple circuits of clock signal for expression according to external signal.
Figure 11 is the block diagram of the formation of expression selection circuit shown in Figure 10.
Figure 12 is the performance plot of the frequency of oscillation characteristic of the control signal relative voltage of expression voltage-controlled oscillator group shown in Figure 10.
Embodiment
(the 1st execution mode)
Fig. 1 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 1st execution mode of PLL circuit of the present invention for expression.In addition, in Fig. 1, be marked with same numeral, detailed for the part identical with component part shown in Figure 10.
In the manner shown in Figure 1, also be provided with 2 input AND circuit 7, it the 1st is input as reference signal, and the 2nd is input as from the signal of selecting circuit 6, its output is input to the reseting terminal of frequency divider 5, and according to this signal, makes the Phase synchronization of frequency divider output and reference signal.
In addition, be provided with the voltage comparator 418 with threshold voltage Vref1 and have threshold voltage Vref2 (＞Vref1) voltage comparator 419 in the inside of selecting circuit 6.In a voltage comparator 418, when the voltage of the control signal S4 that is imported is lower than threshold voltage Vref1, output signal S15 is set at electronegative potential (L) within a certain period of time, and when the voltage of the control signal S4 that is imported was higher than threshold voltage Vref1, output signal S15 was set at electronegative potential (H) within a certain period of time.And, in another voltage comparator 419, when the voltage of the control signal S4 that is imported is lower than threshold voltage Vref2, output signal S16 is set at high potential (H) within a certain period of time, and when the voltage of the control signal S4 that is imported was higher than threshold voltage Vref2, output signal S16 was set at electronegative potential (L) within a certain period of time.
The output S15 and the S16 of voltage comparator 418,419 are input to forward-backward counter 426, and according to this output switching selection switch 436.By having the selection circuit 6 of this operating characteristics, can from 4 voltage-controlled oscillators, select 1 voltage-controlled oscillator corresponding automatically according to the magnitude of voltage of control signal S4 with frequency 4 overtones bands of reference signal CK1 with different control voltage-frequency of oscillation characteristics.
And then, when changing selection modes by selection circuit 6, signal S14 temporarily becomes high potential (H), the potential setting that makes the output signal S4 of loop filter 3 forcibly is the value that is higher than threshold voltage Vref1 shown in Figure 2 and is lower than threshold voltage Vref2, so the output of voltage comparator 418,419 temporarily reverts to high potential (H).Also by having imported 2 input AND circuit 7 of signal S14 and reference signal, frequency divider 5 resets in the variation certain hour constantly of the selection mode of voltage-controlled oscillator, and thus, the output phase of reference signal and frequency divider 5 is synchronous.Thus, the bigger variation of the frequency that causes because of the variation of the selection mode of voltage-controlled oscillator can be by detecting in the phase comparator 1 at short notice, thereby misoperation appears in the selection mode that can prevent to have the voltage-controlled oscillator group 4 of different control voltage-frequency of oscillation characteristics.
As mentioned above, in the semiconductor integrated circuit that comprises voltage-controlled oscillator group with different control voltage-frequency of oscillation characteristics, only the output signal S4 of the loop filter 3 of the misoperation when being used to prevent the switching of voltage-controlled oscillator forced control in the past, but in the manner, also synchronous with reference signal forcibly by the output phase that makes frequency divider 5, can in the extremely short time, select suitable voltage-controlled oscillator.
Fig. 2 is the performance plot of the frequency of oscillation characteristic of the control signal S4 relative voltage of expression voltage-controlled oscillator group 4 shown in Figure 1.In addition, A～D is the control voltage-frequency of oscillation characteristic of each 4 oscillators, and frequency f 1～f8 has following relation: f1＜f2＜f3＜f4＜f5＜f6＜f7＜f8.
At first, the frequency f osc that promptly is input to 4 times of the frequencies of reference signal CK1 for desirable oscillation frequency is that the situation of f1＜fosc＜f2 describes.
When only locking with characteristic D shown in Figure 2, promptly when the voltage of control signal S4 when the scope between threshold voltage Vref1 and threshold voltage Vref2 does not depart from, output signal S15, the S16 of voltage comparator 418,419 do not become electronegative potential (L), therefore, counter 426 is not counted action, selects the state of circuit 6 can not change from initial condition.
In addition,, transfer to characteristic B when characteristic D shown in Figure 2 is transferred to characteristic C, and final when locked, carry out following action.
When control voltage S4 surpassed threshold voltage Vref2 in characteristic D, the output signal S16 of voltage comparator 419 became electronegative potential (L) within a certain period of time, and thus, counter 426 adds 1 action.Output according to this counter 426, the selection mode of voltage-controlled oscillator is transferred to characteristic C from characteristic D, synchronous signal S14 temporarily becomes high potential (H), control signal S4 temporarily returns to the scope between threshold voltage Vrefl and the threshold voltage Vref2, prevents that therefore output signal S16 from becoming electronegative potential (L) after voltage-controlled oscillator switches.
And then, by having imported 2 input AND circuit 7 of signal S14 and reference signal, frequency divider 5 resets in the variation certain hour constantly of the selection mode of voltage-controlled oscillator, therefore, the output phase of reference signal and frequency divider 5 is synchronous, thus, the bigger variation of the frequency that causes because of the variation of the selection mode of voltage-controlled oscillator can be by detecting in the phase comparator 1 at short notice, thereby misoperation appears in the selection mode that can prevent to have the voltage-controlled oscillator group 4 of different control voltage-frequency of oscillation characteristics.
Even carry out PLL control like this, also still be lower than the frequency of 4 times of reference signals, and control voltage S4 surpasses threshold voltage Vref2 once more, selects circuit 6 to carry out above-mentioned action repeatedly, is transferred to characteristic B because of the frequency of internal signal according to characteristic C.At this constantly, voltage-controlled oscillator is the state of the roughly the same frequency of output and reference signal, but because of the phase place of frequency divider 5 also becomes the value corresponding with it, so back 2 frequencies become equal, and finally locks with characteristic B.
On the contrary, for example, should make desirable oscillation frequency fosc become the frequency of the reference signal CK1 of f1＜fosc＜f2, then for example switch to characteristic B → characteristic C → characteristic D, and finally lock onto characteristic D by switching under the state that is locked in present characteristic B.
(the 2nd execution mode)
Fig. 3 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 2nd execution mode of PLL circuit of the present invention for expression.In addition, in Fig. 3, be marked with same numeral, detailed for the part identical with component part shown in Figure 1.
In the manner shown in Figure 3, added following circuit in the part shown in the 1st execution mode: by the output of resume counter 427,428 storage voltage comparators 418,419, and, change the magnitude of voltage of the output potential of forcing setting loop filter 3 according to this record information.
In the present embodiment, when having changed selection mode according to selection circuit 6, when continuously when forward-backward counter 426 has been imported the signal that adds deduct, the output valve of loop filter 3 the signal consecutive hours that adds be set to be lower than threshold voltage Vref2 near, and subtract calculate the signal consecutive hours then force to be set to be higher than threshold voltage Vref1 near.
Resume counter 427,428 has for example each shift register of 2 formation, and its output is input to each 2 input AND circuit 429,430 and 2 input EXOR circuit 431,432.
When the signal that adds is continuous when importing more than 2 times, 2 of resume counter 427 of adding are output as the identical value of output, therefore the output of AND circuit 429 becomes high potential (H), thus, the output S4 of loop filter 3 be forced to be set to be lower than threshold voltage Vref2 near.
On the other hand, be output as the identical value of output when subtracting when calculating that signal is continuous to be imported more than 2 times, subtract 2 of calculating resume counter 428, so the output of AND circuit 430 becomes high potential (H), thus, the output S4 of loop filter 3 be forced to be set to be higher than threshold voltage Vref1 near.
In addition, calculating signal when the signal and subtracting of adding does not all have continuous when importing more than 2 times, the output of 2 EXOR circuit 431,432 becomes high potential (H), and OR circuit 433 is output as high potential (H) as a result, and the output of loop filter 3 is set to the centre of threshold voltage Vref1 and Vref2.
Thus, even for the covering wide frequency range designs a plurality of selectable oscillators, also can shorten transfer time from the minimum characteristic of frequency to the highest characteristic of frequency.
Also by having imported 2 input AND circuit 7 of signal S14 and reference signal, frequency divider 5 resets in during constantly certain of the variation of the selection mode of voltage-controlled oscillator, and thus, the output phase of reference signal and frequency divider 5 is synchronous.Thus, the bigger variation of the frequency that causes because of the variation of the selection mode of voltage-controlled oscillator can be by detecting in the phase comparator 1 at short notice, thereby misoperation appears in the selection mode that can prevent to have the voltage-controlled oscillator group 4 of different control voltage-frequency of oscillation characteristics.
As mentioned above, in the semiconductor integrated circuit that comprises 4 voltage-controlled oscillator groups with different control voltage-frequency of oscillation characteristics, misoperation when preventing the switching of voltage-controlled oscillator in the past only forces to be controlled to be 1 value with the output signal S4 of loop filter 3, but in the manner, added the circuit that changes the magnitude of voltage of the output potential of forcing setting loop filter 3 according to the switching record information of voltage-controlled oscillator, and also synchronous with reference signal forcibly by the output phase that makes frequency divider 5, can select suitable voltage-controlled oscillator in the short time at the utmost point.
Fig. 4 is the performance plot of the frequency of oscillation characteristic of the control signal S4 relative voltage of expression voltage-controlled oscillator group 4 shown in Figure 3.In addition, A～D is the control voltage-frequency of oscillation characteristic of each 4 oscillators, and frequency f 1～f8 has following relation: f1＜f2＜f3＜f4＜f5＜f6＜f7＜f8.
At first, the frequency 4 overtones band fosc that promptly are input to reference signal CK1 for desirable oscillation frequency are that the situation of f1＜fosc＜f2 describes.
When only locking with characteristic D shown in Figure 4, promptly when the voltage of control signal S4 when the scope between threshold voltage Vref1 and threshold voltage Vref2 does not depart from, output signal S15, the S16 of voltage comparator 418,419 do not become electronegative potential (L), therefore, counter 426 is not counted action, selects the state of circuit 6 can not change from initial condition.
In addition,, transfer to characteristic B, and when finally being locked into characteristic A, carry out following action when characteristic D shown in Figure 4 is transferred to characteristic C.
When control voltage S4 surpassed threshold voltage Vref2 in characteristic D, the output signal S16 of voltage comparator 419 became electronegative potential (L) within a certain period of time, and thus, counter 426 adds 1 counting action.Output according to this counter, the selection mode of voltage-controlled oscillator is transferred to characteristic C from characteristic D, synchronous signal S14 temporarily becomes high potential (H), control signal S4 temporarily returns to the scope between threshold voltage Vrefl and the threshold voltage Vref2, therefore prevents that output signal S16 from becoming electronegative potential (L) after the switching of voltage-controlled oscillator.
And then, by having imported 2 input AND circuit 7 of signal S14 and reference signal, frequency divider 5 resets in during constantly certain of the variation of the selection mode of voltage-controlled oscillator, therefore, the output phase of reference signal and frequency divider 5 is synchronous, thus, the bigger variation of the frequency that causes because of the variation of the selection mode of voltage-controlled oscillator can be by detecting in the phase comparator 1 at short notice, thereby misoperation appears in the selection mode that can prevent to have the voltage-controlled oscillator group 4 of different control voltage-frequency of oscillation characteristics.
Even carry out PLL control according to characteristic C like this, also still be lower than 4 overtones bands of reference signal, and control voltage S4 surpasses threshold voltage Vref2 once more because of the frequency of internal signal.At this moment, 2 outputs of resume counter 427 of adding become high potential (H) simultaneously, therefore the output of AND circuit 429 becomes high potential (H), thus, the output S4 of loop filter 3 be forced to be set to be lower than threshold value Vref2 near, and simultaneously, frequency divider 5 also carries out above-mentioned action repeatedly, is transferred to characteristic B.
Even carry out PLL control according to characteristic B like this, also still be lower than 4 overtones bands of reference signal, and control voltage S4 surpasses threshold voltage Vref2 once more because of the frequency of internal signal, select circuit 6 to carry out above-mentioned action repeatedly, be transferred to characteristic A.
At this constantly, voltage-controlled oscillator is the state of the roughly the same frequency of output and reference signal, but because of the phase place of frequency divider 5 also becomes the value corresponding with it, so back 2 frequencies become equal, and finally locks with characteristic A.
On the contrary, for example, switch for the frequency that should make desirable oscillation frequency fosc become the reference signal CK1 of f1＜fosc＜f2 by the state that is locked in present characteristic A, then as shown in Figure 5, for example switch to characteristic A → characteristic B → characteristic C → characteristic D, and finally lock onto characteristic D.
Fig. 5 is the performance plot of the frequency of oscillation characteristic of the control signal S4 relative voltage of expression voltage-controlled oscillator group 4 shown in Figure 3.
In the aforesaid the manner, though be output valve S4 with loop filter 3 be set to threshold voltage Vref1 or threshold voltage Vref2 near, this is very effective for the situation that needs significantly change frequency.During use in identical frequency band etc., carry out inching in 2 amounts of voltage-controlled oscillator with interior frequency range usually and be advisable, but when different frequency band transition etc., frequency need significantly be changed.
(the 3rd execution mode)
Fig. 6 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 3rd execution mode of PLL circuit of the present invention for expression.In addition, in Fig. 6, be marked with same numeral, detailed for the part identical with component part shown in Figure 1.
In the manner shown in Figure 6, replacement has the voltage-controlled oscillator of different frequency variable range and is provided with the resonant circuit group 434 that is made of a plurality of resonant circuits with different resonance frequencys on the part shown in the 1st execution mode, and, obtain and the identical effect of effect shown in the 1st execution mode by switching a plurality of resonant circuits.In addition, resonant circuit is made of inductor and capacitor usually.
(the 4th execution mode)
Fig. 7 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 4th execution mode of PLL circuit of the present invention for expression.In addition, be marked with same numeral, detailed for the part identical with component part shown in Figure 1.
In the manner shown in Figure 7, replacement has the voltage-controlled oscillator of different frequency variable range and is provided with the resonant circuit group 434 that is made of a plurality of resonant circuits with different resonance frequencys on the part shown in the 2nd execution mode, and, obtain and the identical effect of effect shown in the 2nd execution mode by switching a plurality of resonant circuits.In addition, resonant circuit is made of inductor and capacitor usually.
(the 5th execution mode)
Fig. 8 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 5th execution mode of PLL circuit of the present invention for expression.In addition, be marked with same numeral, detailed for the part identical with component part shown in Figure 1.
In the manner shown in Figure 8, on the part shown in the 1st execution mode, replace the ring oscillator 435 that has the voltage-controlled oscillator of different frequency variable range and adopt the variable a plurality of inverters of continuous connection time of delay.In the manner,, can in wide region, change frequency by switching the number of connection of ring oscillator 435.
(the 6th execution mode)
Fig. 9 has been suitable for the block diagram of configuration example of 4 multiple circuits of the 6th execution mode of PLL circuit of the present invention for expression.In addition, be marked with same numeral, detailed for the part identical with component part shown in Figure 1.
In the manner shown in Figure 9, on the part shown in the 2nd execution mode, replace the ring oscillator 435 that has the voltage-controlled oscillator of different frequency variable range and adopt the variable a plurality of inverters of continuous connection time of delay.In the manner,, can in wide region, change frequency by switching the number of connection of ring oscillator 435.
In addition, in 6 above-mentioned execution modes, though be that the situation that comprises 4 voltage-controlled oscillators with different control voltage-frequency of oscillation characteristics is illustrated,, can constitute 4 multiple circuits equally for the situation of the voltage-controlled oscillator that comprises 2 above any number.
In addition, in the above-described embodiment, as shown in Figure 4, though used the voltage potential of control signal S4 to uprise the voltage-controlled oscillator of the characteristic that frequency of oscillation then uprises, also can use the opposite action characteristic is that the voltage potential of control signal S4 uprises the then voltage-controlled oscillator of the characteristic of frequency of oscillation step-down.In this case, if directly use threshold voltage Vref1, Vref2, then the voltage of signal S4 just switches to the frequency characteristic higher than present characteristic of the characteristic of PLL locking less than threshold voltage Vref1, and is just to switch to the low characteristic of frequency more than the threshold voltage Vref2.
In addition, constitute in 4 voltage-controlled oscillators of voltage-controlled oscillator group 4 at each, though be that all identical situation of threshold voltage Vref1, Vref2 is illustrated, also can consider to make each threshold voltage Vref1, the Vref2 difference in 4 voltage-controlled oscillators.
The present invention is suitable for using a plurality of voltage-controlled oscillators with different control voltage-frequency of oscillation characteristics and realizes the multiband radio function promptly with the mobile communication system of the receiving and transmitting signal function of a plurality of frequency bands, and relates to the PLL circuit that can select required voltage-controlled oscillator according to desirable oscillation frequency at short notice.
Claims (27)
1. PLL circuit is characterized in that having:
Phase bit comparison mechanism, its phase place to reference signal and internal signal compares, and the output phase signal corresponding with its phase difference;
A plurality of oscillators, it has mutually different changeable frequency scope, and according to each phase control signal control frequency of oscillation;
Selection mechanism, it is according to described phase signal or described phase control signal, selects 1 in the output of described a plurality of oscillators; With
Frequency division mechanism, it generates described internal signal by the output frequency division of the oscillator that will be selected by described selection mechanism;
Also have the output phase that when the selection mode of described oscillator changes, makes described frequency divider and the approaching mechanism of phase place of described reference signal.
2. PLL circuit as claimed in claim 1, wherein, the changeable frequency scope of described a plurality of oscillators is overlapped.
3. PLL circuit as claimed in claim 1, wherein, the action threshold voltage value of described a plurality of oscillators is different mutually.
4. as each described PLL circuit in the claim 1 to 3, wherein, described selection mechanism is switched the output of described a plurality of oscillators according to the resume of described phase signal or described phase control signal.
5. as each described PLL circuit in the claim 1 to 4, wherein,
Described oscillator is a voltage-controlled oscillator,
Has the mechanism that described phase signal is converted to magnitude of voltage.
6. PLL circuit as claimed in claim 5, wherein, has following mechanism: set its value mutually different 2 threshold voltages in the variable reference voltage of described phase control voltage, when the selection mode of described voltage-controlled oscillator changes, the value of described phase control voltage temporarily is set in the scope of described 2 threshold voltage clampings.
7. PLL circuit as claimed in claim 6 wherein, has following mechanism: the resume when changing according to the selection mode of described voltage-controlled oscillator change the value of the temporary transient described phase control voltage of setting.
8. PLL circuit as claimed in claim 6, wherein, when described phase control voltage outside the scope of described 2 threshold voltage clampings and when switching the selection mode of described voltage-controlled oscillator, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
9. PLL circuit as claimed in claim 6, wherein, described phase control voltage is outside the scope of described 2 threshold voltage clampings and when switching the selection mode of described voltage-controlled oscillator, continuous more than 2 times under the extraneous situation at described 2 threshold voltage clampings at described phase control voltage, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
10. PLL circuit as claimed in claim 6, wherein, when described phase control voltage is outside the scope of described 2 threshold voltage clampings,, control whether greater than described 2 threshold voltages or not less than described 2 threshold voltages according to this phase control voltage so that described phase control voltage is set for height or set for low with respect to the intermediate potential of described 2 threshold voltages.
11. a PLL circuit is characterized in that having:
Phase bit comparison mechanism, its phase place to reference signal and internal signal compares, and the output phase signal corresponding with its phase difference;
A plurality of resonant circuits, it has mutually different resonance frequency;
Oscillator, it is according to described resonant circuit and phase control signal control frequency of oscillation;
Selection mechanism, it selects 1 in described a plurality of resonant circuit according to described phase signal or described phase control signal; With
Frequency division mechanism, it generates described internal signal by the output frequency division to described oscillator;
Also have the output phase that when the selection mode of described resonant circuit changes, makes described frequency divider and the approaching mechanism of phase place of described reference signal.
12. PLL circuit as claimed in claim 11, wherein, described selection mechanism is switched described a plurality of resonant circuit according to the resume of described phase signal or described phase control signal.
13. as claim 11 or 12 described PLL circuit, wherein,
Described oscillator is a voltage-controlled oscillator,
Has the mechanism that described phase signal is converted to magnitude of voltage.
14. PLL circuit as claimed in claim 13, wherein, has following mechanism: set its value mutually different 2 threshold voltages in the variable reference voltage of described phase control voltage, when the selection mode of described resonant circuit changes, the value of described phase control voltage temporarily is set in the scope of described 2 threshold voltage clampings.
15. PLL circuit as claimed in claim 14 wherein, has following mechanism: the resume when changing according to the selection mode of described resonant circuit change the value of the temporary transient described phase control voltage of setting.
16. PLL circuit as claimed in claim 14, wherein, when described phase control voltage outside the scope of described 2 threshold voltage clampings and when switching the selection mode of described resonant circuit, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
17. PLL circuit as claimed in claim 14, wherein, when described phase control voltage outside the scope of described 2 threshold voltage clampings and when switching the selection mode of described resonant circuit, continuous more than 2 times under the extraneous situation at described 2 threshold voltage clampings at described phase control voltage, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
18. PLL circuit as claimed in claim 14, wherein, when described phase control voltage is outside the scope of described 2 threshold voltage clampings,, control whether greater than described 2 threshold voltages or not less than described 2 threshold voltages according to this phase control voltage so that described phase control voltage is set for height or set for low with respect to the intermediate potential of described 2 threshold voltages.
19. a PLL circuit is characterized in that having:
Phase bit comparison mechanism, its phase place to reference signal and internal signal compares, and the output phase signal corresponding with its phase difference;
Oscillator, it connects and composes by controlled a plurality of delay circuits of time of delay according to each phase control signal;
Selection mechanism, it selects the number of connection of described delay circuit according to described phase signal or described phase control signal; With
Frequency division mechanism, the output frequency division that it passes through the oscillator of being selected by described selection mechanism generates described internal signal;
Also have the output phase that when the selection mode of described oscillator changes, makes described frequency divider and the approaching mechanism of phase place of described reference signal.
20. PLL circuit as claimed in claim 19, wherein, described selection mechanism is switched the number of connection of described delay circuit according to the resume of described phase signal or described phase control signal.
21. as claim 19 or 20 described PLL circuit, wherein,
Described oscillator is a voltage-controlled oscillator,
Has the mechanism that described phase signal is converted to magnitude of voltage.
22. PLL circuit as claimed in claim 21, wherein, has following mechanism: set its value mutually different 2 threshold voltages in the variable reference voltage of described phase control voltage, when the selection mode of the number of connection of described delay circuit changes, the value of described phase control voltage temporarily is set in the scope of described 2 threshold voltage clampings.
23. PLL circuit as claimed in claim 22 wherein, has following mechanism: the resume when changing according to the selection mode of the number of connection of described delay circuit change the value of the temporary transient described phase control voltage of setting.
24. PLL circuit as claimed in claim 22, wherein, when described phase control voltage outside the scope of described 2 threshold voltage clampings and when switching the selection mode of number of connection of described delay circuit, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
25. PLL circuit as claimed in claim 22, wherein, when described phase control voltage outside the scope of described 2 threshold voltage clampings and switch described delay circuit the selection mode of number of connection the time, continuous more than 2 times under the extraneous situation at described 2 threshold voltage clampings at described phase control voltage, the described phase control voltage of temporarily setting is set near the threshold voltage of the described phase control voltage side in described 2 threshold voltages.
26. PLL circuit as claimed in claim 22, wherein, when described phase control voltage is outside the scope of described 2 threshold voltage clampings,, control whether greater than described 2 threshold voltages or not less than described 2 threshold voltages according to this phase control voltage so that described phase control voltage is set for height or set for low with respect to the intermediate potential of described 2 threshold voltages.
27., wherein, make the output phase of described frequency division mechanism and the Phase synchronization of described reference signal as each described PLL circuit in the claim 1 to 26.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP339395/2002 | 2002-11-22 | ||
| JP2002339395A JP2004173177A (en) | 2002-11-22 | 2002-11-22 | Pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1714509A true CN1714509A (en) | 2005-12-28 |
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ID=32375773
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2003801037272A Pending CN1714509A (en) | 2002-11-22 | 2003-11-21 | PLL circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7180375B2 (en) |
| JP (1) | JP2004173177A (en) |
| CN (1) | CN1714509A (en) |
| WO (1) | WO2004049575A1 (en) |
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| CN102281066A (en) * | 2011-04-15 | 2011-12-14 | 上海迦美信芯通讯技术有限公司 | Frequency synthesizer applied to binary channel and multi-mode radio frequency receiver |
| CN102279403A (en) * | 2011-04-25 | 2011-12-14 | 上海迦美信芯通讯技术有限公司 | Dual channel navigation radio frequency receiver |
| CN102857221A (en) * | 2011-06-30 | 2013-01-02 | 中兴通讯股份有限公司 | Phase locked loop, wide band transmitter and carrier wave leakage correction method of wide band transmitter |
| CN102857221B (en) * | 2011-06-30 | 2017-07-21 | 中兴通讯股份有限公司 | The carrier wave leakage calibration method of phaselocked loop, wideband transmitter and wideband transmitter |
| CN102445699A (en) * | 2011-10-18 | 2012-05-09 | 上海迦美信芯通讯技术有限公司 | System structure for double-channel navigating radio-frequency receiver sharing radio-frequency front end |
| CN102522985A (en) * | 2011-12-31 | 2012-06-27 | 杭州士兰微电子股份有限公司 | Locking-phase ring and voltage-controlled oscillator thereof |
| CN102522985B (en) * | 2011-12-31 | 2014-02-19 | 杭州士兰微电子股份有限公司 | Locking-phase ring and voltage-controlled oscillator thereof |
| CN104702271A (en) * | 2013-12-10 | 2015-06-10 | 展讯通信（上海）有限公司 | Phase-locked loop circuit and calibration method for characteristic curves of voltage-controlled oscillator |
| CN104702271B (en) * | 2013-12-10 | 2018-06-05 | 展讯通信（上海）有限公司 | The characteristic calibration method of phase-locked loop circuit and voltage controlled oscillator |
| CN106170920A (en) * | 2014-04-11 | 2016-11-30 | 高通股份有限公司 | Single phase-locked loop is utilized to lock multiple voltage controlled oscillators |
Also Published As
| Publication number | Publication date |
|---|---|
| US20050253658A1 (en) | 2005-11-17 |
| US7180375B2 (en) | 2007-02-20 |
| JP2004173177A (en) | 2004-06-17 |
| WO2004049575A1 (en) | 2004-06-10 |
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