CN1707790A - 具有高反差标志的金属层的半导体器件及制造方法 - Google Patents
具有高反差标志的金属层的半导体器件及制造方法 Download PDFInfo
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- CN1707790A CN1707790A CNA2005100729879A CN200510072987A CN1707790A CN 1707790 A CN1707790 A CN 1707790A CN A2005100729879 A CNA2005100729879 A CN A2005100729879A CN 200510072987 A CN200510072987 A CN 200510072987A CN 1707790 A CN1707790 A CN 1707790A
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Abstract
一种功率半导体器件,它包括一个具有电活性第一和第二表面的半导体单元片。一个标志位于第二表面上,配置该标志以利于该器件的辨认,而在半导体单元片的第二表面以及标志上形成一金属层,配置该金属层以传导该器件的电流并使该标志清晰可见,以供辨认。
Description
技术领域
本发明一般地涉及半导体器件,更具体地讲,涉及这样的半导体器件,它有两个相对表面都具有电活性的基片,在表面上形成图案并涂以一种金属,从而提供与该半导体器件相关的信息。
背景技术
电子学系统的制造商们持续要求降低集成电路和其它半导体器件的费用以减小电子学系统的成本。相应地,许多半导体制造商正在提供没有封装的半导体单元片(die)或芯片,它能以一种倒装芯片的方式,即从第一单元片表面直接连接到系统电路母板上,来安装。这种方法减小半导体器件的直接成本,并由于减小了导线电感和其它寄生因素而改进了这些器件的性能。然而倒装芯片技术常常增加了间接成本,因为这样一个未封装的半导体芯片很少给出或没有给出关于芯片类型的信息,诸如部件号或制造商。在系统出现故障的情况下,难于去追踪缺陷直至一个具体的制造商或制作过程。
为了避免这个问题,某些芯片制作成具有一个标以关于半导体器件信息的单元片表面涂层,以有利于在有缺陷的情况下,追踪该器件至其制造商。然而,这样导致的信息标志反差小,从而清晰度低,在某些情况下,即使通过显微镜或其它视觉设备也是如此。为了弥补低反差的缺点,已有的技术涂层以大的字体来标志,这就减少能够提供的信息量,尤其在小的单元片上。其结果是,追踪一有缺陷的半导体器件直至一特定处理步骤的能力就减小,从而更难于防止将来的缺陷,而这种追踪能力能提高单元片的产率和可靠性,从而降低器件和系统的整体制作成本。
另外,在芯片两个表面都是电活性,并载有诸如功率器件,如场效应晶体管(FET),二极管或绝缘栅双极晶体管(IGBT),这样器件的一个电流的器件上在涂层上作标志要损伤涂层,从而降低器件性能并甚至能引起器件失效。另外,作标志减小了涂层的平面性,从而使热漏或其它散热结构的有效接触变得困难。
因而,就有对这样一种半导体器件及其制造方法的需要,这种器件有传导器件电流的涂层,这种方法提供与半导体器件相关的容易识别的信息,以减少半导体器件的制造成本并提高其可靠性和性能。
附图说明
图1是一半导体晶片的轴测图;
图2是一张截面图,它给出晶片的一部分的细节;
图3是一张截面图,它给出连结到晶片该部分的一个热漏;
图4是一个电系统的一张分解图,该系统包括从半导体晶片切单出的一个封装的半导体单元片所形成的一个半导体器件;
图5是一张截面图,它给出和晶片该部分连结的一个夹。
具体实施方式
在图中,有类似参照数字的部件有类似的功能。
图1是一片半导体晶片10的轴侧图,它制备成具有许多半导体单元片,其中一个被指定为半导体基片或单元片20。在一个实施方案中,基片20包括硅材料,其厚度17在约75和400微米之间。在另一个实施方案中,基片20包括硅锗材料。一个晶片平直区12提供关于晶片10结晶学取向的信息。一第一电活性或顶侧表面14被用来形成半导体器件或芯片20,它可以包括晶体管和/或其它有源器件。半导体器件20有一个第二电活性或背侧表面15。电活性背侧表面15传导半导体器件的一个电流IBS。在一个实施方案中,半导体器件20包括一个功率半导体器件20,诸如一个场效应晶体管(FET),二极管,绝缘栅双极晶体管(IGBT)或要求单元片20的背侧15和顶侧14是电活性的其它功率器件。如同本技术领域所熟知的那样,背侧15与顶侧14所不同之处在于,如果基片20要被减薄,基片材料是用普通减薄方法或“背研磨”方法从背侧15去除,例如用,但不限于,研磨,腐蚀或抛光及其它等方法。通常用进行这种基片材料去除或减薄来除去在加工过程中由晶片处理所引起的背侧缺陷,来减薄晶片或在背侧金属形成之前进行。
图2是一张截面图,它更细致地给出包括半导体单元片20在内的晶片10的一部分。请注意,半导体单元片20是以一种“倒装芯片”取向给出的,它与图1的取向相反。
在背侧表面15上形成金属层16之前,用引导电磁幅射的射线30来从基片20的背侧表面15选择性地除去材料以在背侧表面15上标出信息,从而形成标志21。在一个实施方案中,射线30是一激光束,它被编程以产生表示所需信息的以字母数字符号或其它符号形状的标志21。象激光器件的电流大小或激光强度,激光束的脉冲率,光束直径和扫描时间等参数,如果需要的话可以被调整,以保证从背侧表面15除去材料并在半导体单元片20的背侧表面15上产生最小的渣包22。渣包22是在标志21形成时重新淀积在背侧表面上的被除去的材料。渣包22可以在背侧表面15上形成约3微米的高度。标志21形成典型的深度24约5微米,宽度25约40微米。
注意到这一点是重要的,即标志需要一个相当大的面积37和除去相当多的材料的数量或体积以建立一个可见的标志。因而,因为半导体单元片的尺寸和厚度在将来预期要减小,标志的面积37和体积在有效单元片面积和体积中的百分数预期要增加。例如,有一个2乘2球栅阵列而节距为0.8毫米的单元片有一个1.6毫米乘1.6毫米的可用的标志面积或尺寸。因而,当提供9个标志(一个典型的数目),而每一个约0.42毫米高,0.23毫米宽,在后侧表面上利用了0.87平方毫米,所用面积的量为背侧表面的约百分之36(100×0.87/2.56)。同样,将来单元片厚度的减小将使标志体积消耗愈来愈多有效基片体积的问题加重。
不幸的是,电活性的后侧表面15传导器件20的一个电流IBS,增加标志面积和/或标志体积将增加硅晶格的损伤,从而引起荷载电流能力的下降和引起在标志的边缘38上收集电流产生的局域化热点。这样,当顾客要求增加电流荷载能力和改进热性能并同时要求更薄和更小的单元片时,就十分需要来解决由于增加标志面积和体积所引起的问题。在一个实施方案中,半导体单元片20包括一个功率场效应晶体管,其横向或沟道电流(IBS)大于约0.5安培。
虽然在图上给出的通常是矩形,但用以形成标志21的材料去除可以形成各种几何形状的标志21,诸如直的或弧状的沟道或沟槽。
在另一个实施方案中,标志21可以用在背侧表面15上涂以一层光致抗蚀层(未示出),并用通常可行的湿性或干性腐蚀技术选择性腐蚀以去除材料来形成。
标志21可以用于各种目的。例如,标志可以指明在其上形成标志的半导体器件的类型。该标志也可以置于某一位置,例如置于一个特定的角上,以使可以确定该器件的取向。器件取向之所以重要的一个理由是,这样就可以恰当地把器件放置在并连接到印刷电路板上。在顶侧表面14和背侧表面15之间的对准,例如在标志21和半导体单元片20之间的对准是用一标准对准工具来获得的。
一金属层16被加到背侧表面15上以传导器件20的电流IBS。在一个实施方案中,金属层16包括机焊接的背金属,形成的厚度在约15000到约20000的范围内。可焊接背金属16的例子包括含有钛,镍,银,铬,金,硅化镍,或镍钒的金属或合金,根据适当的可焊接性,粘附性,以及机械强度来加以选择。金属层16的一个例子是铝,但由于它差的可焊接性而不认为是可焊接背金属。背侧金属16必须还选具有较大厚度26,并具有这样的材料性质以最适应地复盖并封住由标志引起的渣包22,以及反复地从被标志损坏的这些区域携带器件的电流IBS而没有不适应地限止电流或引起局部热偏离或“热点”的增加。因而较厚的背侧金属16会减小电流电阻,以及一般地改善器件20的热性能。另外,因为在有双侧电活性的器件上的薄的背侧金属将得到渣包22和标志21损伤区的差的复盖以及标志的差的可检测和可辨认性,这种背金属16也必须足够厚以使在表面上的标志可以被辨认。为了改进可辨认性所要求的金属厚度16的意想不到的增加,对于具有双侧电活性的器件,想来是独特的,厚度增加显示为提高可辨认性,而不是人们可能预期的减小可辨认性。另外,当单元片厚度下降到400微米以下时,金属16的厚度增加时,可辨认性显得进一步增加。
可以用众所周知的溅射方法来加上金属层16。溅射用在原子水平上淀积金属以在一个表面上涂一种金属。加上金属层16的其它方法包括蒸汽淀积或化学镀。
在顶侧表面14上形成许多导电凸块18,以在顶侧表面14上的电路和一个系统电路板60,封装接线框(未示出)或另一个单元片诸如堆层单元片情况下。(未示出)之间形成电连接和机械连接。导电凸块18通常用一种低温焊接金属,电镀铜或其它导电材料来形成,这些材料要适合形成必需的电的和/或机械的接触而没有使在半导体单元片20上形成的电路性能恶化。
半导体单元片20被一圈锯带23所包围,该锯带用以在金属层16形成之后,把半导体单元片20从半导体晶片10中切单(singulate)出来。这种切单可以在形成导电凸块18之前或之后进行。
图3给出安装在背金属层16上的一个热漏(heat sink)50。热漏安装是用各种粘结材料56来完成的,包括,但不限于,环氧粘结剂,导热粘结剂,焊剂或其它。热漏50粘结区55尽可能平坦并仍然有标志21的可辨认性是重要的,以提供热漏50理想的机械接触和热传导。因而,用金属16的较大厚度26改进了平面性,因为较厚的金属16使标记21平滑。另外,如上所述,较厚的金属16也增加标志的可辨认性,同时改进器件20的电流IBS传导。
图4给出一张电系统70的分解图,电系统70包括一个系统电路板60和一个用半导体单元片20形成的封装的半导体器件80。电路板60包括一个安装区64,以把未封装半导体器件80的导电凸块18安装到许多个导电接合焊垫62上。
如上所述,通过选择性地从基片20除去材料并涂以金属层16,从而以明显的反差提供可看清的符号和/或字母数字符号21,以给出与封装半导体器件80有关的信息。在封装半导体器件80中所示的字母数字符号21形成的高度约250微米。
这种信息的例子包括终端用户或系统制造商商标或顾客部件号以减少半导体器件80的盘存或其它成本。可以提供半导体器件制造商的商标或其它标志以在封装的半导体器件80被发现缺陷的情况下,有利于通报。晶片和单元片处理信息,诸如批号,晶片和单元片标志,以及部件号和/或系列号可以让半导体制造商来追踪未封装半导体器80直至特定的处理步骤,以确定缺陷来源的范围。许多缺陷可以和一个特定的处理步骤相关连,以及常常能用修改处理步骤予以改正,从而改进了相同处理器件的可靠性并降低了该器件整体制造成本。另外,也可以提供对于终端用户或系统制造商有用的信息,诸如单元片取向和/或参照引线的位置,如管脚“1”。除了字母数字符号以外,由上述结构提供的加强的反差也适合于提供以机器可读符号式条状码形成的信息。
图5给出安装在半导体单元片20的背金属层16上的一金属片或金属夹77,以代替热漏50。金属片或金属夹典型地是几乎矩形的一片导电金属,诸如铜或镀锡铜,用冲压或腐蚀的方法得到,用以形成从半导体单元片20到另一个半导体单元片99之间的一个电接触,或者作为一个引线98以把半导体单元片20电连接和机械连接到一个电路板,接线框,另一个单元片,以及其它等。虽然图中所示引线98是使外表面18a与单元片20底部在一个平面上,但也可以提供其它的配置和取向。引线98还可以包括在其外表面18A上的一个导电凸块18。金属夹77的安装是用各种粘结剂56来完成的,包括,但不限于1环氧粘结剂,热导粘结剂,焊剂或其它。下面一点是重要的,即金属夹77粘结区55应是尽可能地平,同时又仍然使标志21可辨,以提供金属夹77理想的机械接触和电连接。因而用金属16的较大的厚度26改进了平面性,因为标志21被较厚的金属16所平滑化。重要的是,金属16的改进了的平面性,减小了在金属夹77粘结过程中金属夹的转动和移动,从而减少了通常和大的标志21面积和体积相关连的连接缺陷。
总之,描述了一种半导体器件及描述提供关于该半导体器件信息的方法。该半导体器件包括一个半导体单元片,它有电活性的第一和第二表面,位于第二表面上有一个标志,以有利于该器件的识别,以及形成一金属层复盖在半导体单元片的第二表面及标志上。金属层被配置得可以传导器件的电流并使得标志清晰可见以用以辨认。
Claims (10)
1.一种功率半导体器件,包括:
半导体单元片,它有一个第一表面和一个第二表面,其中该第一和第二表面是电活性的;
位于第二表面上的标志,配置该标志以利于该器件的辨认;以及
在该半导体单元片的第二表面上以及标志上形成的一金属层,配置该金属层以传导该器件的电流并使得该标志可见,以供辨认。
2.权利要求1的功率半导体器件,其中该标志覆盖大于约百分之三十五的半导体单元片的第二表面。
3.权利要求1的功率半导体器件,其中该金属层用一种可焊接背金属形成,它选自包括镍,银,铬,金,硅化镍,和镍钒的组。
4.权利要求1的功率半导体器件,还包括在半导体单元片的第一表面上形成的导电凸块,以作外部电的和机械的连接。
5.权利要求1的功率半导体器件,还包括一个附着到半导体单元片第二表面的一个夹子,以作为外部电的和机械的连接。
6.权利要求5的功率半导体器件,还包括在夹子的一个外表面上形成的导电凸块,以作为外部电的和机械的连接。
7.一种半导体器件,包括:
半导体基片,它有一个第一表面,其中该第一表面是电活性的;
位于第一表面上的标志,配置该标志以利于该器件的辨认;以及
在该半导体基片的第一表面上和标志上形成的一金属层,配置该金属层以传导该器件的电流并使该标志可见以供辨认。
8.权利要求7的半导体器件,其中该信息包括字母数字字符,它的高度小于约300微米。
9.权利要求7的半导体器件,其中半导体基片有相对于第一表面的第二表面,它形成为具有导电凸块以作外部电的和机械的连接。
10.一种制造半导体器件的方法,包括以下步骤:
提供具有一个第一电活性表面的半导体基片;
在第一电活性表面上除去基片材料以形成标志,配置该标志以利于器件的辨认;以及
在半导体基片的第一电活性表面上和标志上形成一金属层,配置该金属层以传导该器件的电流并使该标志可见以供辩认。
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US10/854,465 | 2004-05-27 | ||
US10/854,465 US6984876B2 (en) | 2004-05-27 | 2004-05-27 | Semiconductor device formed having a metal layer for conducting the device current and for high contrast marking and method thereof |
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CN1707790A true CN1707790A (zh) | 2005-12-14 |
CN100435332C CN100435332C (zh) | 2008-11-19 |
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US (1) | US6984876B2 (zh) |
CN (1) | CN100435332C (zh) |
HK (1) | HK1084233A1 (zh) |
Cited By (2)
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CN101807511B (zh) * | 2009-02-13 | 2012-03-28 | 万国半导体股份有限公司 | 激光标识晶片水平芯片级封装的方法 |
CN106257665A (zh) * | 2015-06-16 | 2016-12-28 | 意法半导体(马耳他)有限公司 | 制作电子元件的方法及相应的电子元件 |
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EP2023387A4 (en) * | 2006-05-26 | 2010-04-14 | Murata Manufacturing Co | SEMICONDUCTOR DEVICE, ELECTRONIC ELEMENT MODULE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE |
WO2008018332A1 (fr) * | 2006-08-09 | 2008-02-14 | Honda Motor Co., Ltd. | Dispositif à semi-conducteurs |
US20080157342A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Package with a marking structure and method of the same |
DE102007002807B4 (de) | 2007-01-18 | 2014-08-14 | Infineon Technologies Ag | Chipanordnung |
US7960800B2 (en) * | 2008-12-12 | 2011-06-14 | Fairchild Semiconductor Corporation | Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same |
US7842543B2 (en) * | 2009-02-17 | 2010-11-30 | Alpha And Omega Semiconductor Incorporated | Wafer level chip scale package and method of laser marking the same |
JP5146490B2 (ja) | 2010-06-07 | 2013-02-20 | 三菱電機株式会社 | 半導体素子 |
CN102842556B (zh) * | 2011-06-21 | 2015-04-22 | 万国半导体(开曼)股份有限公司 | 双面外露的半导体器件及其制作方法 |
US8450152B2 (en) * | 2011-07-28 | 2013-05-28 | Alpha & Omega Semiconductor, Inc. | Double-side exposed semiconductor device and its manufacturing method |
FR3061600B1 (fr) * | 2017-01-03 | 2020-06-26 | Stmicroelectronics (Grenoble 2) Sas | Dispositif electronique comprenant une puce rainuree |
US10804217B2 (en) | 2018-08-10 | 2020-10-13 | STATS ChipPAC Pte. Ltd. | EMI shielding for flip chip package with exposed die backside |
US11355452B2 (en) | 2018-08-10 | 2022-06-07 | STATS ChipPAC Pte. Ltd. | EMI shielding for flip chip package with exposed die backside |
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JP2000114129A (ja) * | 1998-10-09 | 2000-04-21 | Toshiba Corp | 半導体装置及びその製造方法 |
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US6524881B1 (en) | 2000-08-25 | 2003-02-25 | Micron Technology, Inc. | Method and apparatus for marking a bare semiconductor die |
US6448632B1 (en) * | 2000-08-28 | 2002-09-10 | National Semiconductor Corporation | Metal coated markings on integrated circuit devices |
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JP4256115B2 (ja) * | 2002-05-28 | 2009-04-22 | 富士通マイクロエレクトロニクス株式会社 | マーク認識方法及び半導体装置の製造方法 |
-
2004
- 2004-05-27 US US10/854,465 patent/US6984876B2/en not_active Expired - Lifetime
-
2005
- 2005-05-25 CN CNB2005100729879A patent/CN100435332C/zh not_active Expired - Fee Related
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101807511B (zh) * | 2009-02-13 | 2012-03-28 | 万国半导体股份有限公司 | 激光标识晶片水平芯片级封装的方法 |
CN106257665A (zh) * | 2015-06-16 | 2016-12-28 | 意法半导体(马耳他)有限公司 | 制作电子元件的方法及相应的电子元件 |
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US20050263859A1 (en) | 2005-12-01 |
HK1084233A1 (en) | 2006-07-21 |
CN100435332C (zh) | 2008-11-19 |
US6984876B2 (en) | 2006-01-10 |
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